DE102006023609A1 - Programmable resistive memory cell for use in e.g. flash RAM, has programmable layer surrounded by insulating layer, where resistance of programmable layer and temperature dependence of resistance are adjusted by metal oxides - Google Patents

Abstract

The memory cell has a programmable resistance layer (11) surrounded by an insulating layer. The programmable resistance layer is provided with transition metal oxides, which are formed by transition metals such as chromium. One of the transition metal oxides is oxidized in a highest oxidation degree. An initial electrical resistance of the programmable resistance layer at an ambient temperature and the temperature dependence of the resistance of the programmable resistance layer are adjusted by the transition metal oxides. An independent claim is also included for a method for manufacturing a resistive memory cell.

Description

The The invention relates to a programmable resistive memory cell with a programmable resistive layer, as well as a process for producing a resistive memory cell with a programmable Resistance layer.

conventional Electronic data storage, such as the Dynamic Random Access Memory (DRAM) or Flash RAM are increasingly reaching their limits when They should meet modern requirements. conventional Concepts for electronic data storage, as with the DRAM or flash RAM are used to store information units in capacitors, wherein a charged or uncharged state of a capacitor can represent about the two logic states "1" or "0".

in the In the case of the DRAM, the capacitors are made extremely small to to achieve and require a high density of information and integration therefore a permanent one Refresh the stored information content. This requires in addition to additional memory controllers for refreshment also a considerable energy requirement. The flash RAM keeps though the information content stored in it even without supply of Energy, however, need the individual flash RAM memory cells have a high voltage for writing information and the number of possible switching cycles is limited. Modern electronic data storage systems must therefore be able to a high information density, a short access time and a non-volatility to unite. The non-volatility here denotes the property of an electronic data store that this the information content even without external energy input longer Time reliable can save.

The Requirements for integration density and non-volatility are particularly evident in portable applications, since there both the available Limited space is as well as serving as a power supply batteries only one limited Can provide energy and voltage. To the non-volatility with a short access time and a high integration will be in science and industry intensively on alternatives for the DRAM or the flash RAM worked. Among other things, make the so-called resistive electronic memory is a promising concept.

Next for example, solid-state electrolytes, Phase transition cells and other special materials can also be used in transition metal oxide layers a corresponding high and low impedance electrical state reliable and stably impressed on such an oxide layer. A low impedance State can thus, for example, a logic state "1", and a high-impedance State are assigned a logical state "0." Such Layers also allow a differentiation of several resistive states, so in a cell also several reliably distinguishable logical conditions can be saved what also as a multi-capability referred to as.

The information storage in a transition metal oxide (TMO) layer is based on the principle that a low-resistance filament can be formed in a TMO by local heating. The local heating is generated by a current through the initially high-resistance ÜMO. The filament thereby short-circuits the otherwise high-resistance ÜMO and thereby substantially changes the effective electrical resistance. By applying a voltage, a sufficiently low measuring current can be determined to determine the resistive and therefore logical state of a ÜMO memory cell. An existing filament can be interrupted again by a sufficiently high current and the ÜMO memory cell thus returns to a high-impedance state. This process is reversible and has already been demonstrated for technically relevant repetition rates in the range of 10 ⁶ . A ÜMO memory cell is usually formed from a lower electrode, an upper electrode and a thin ÜMO layer arranged therebetween. The minimum size of such a ÜMO memory cell is given mainly by lithographic limitations with regard to the structuring of the electrodes.

One single filament, the electrical resistance of a ÜMO memory cell significantly lower, is often much smaller in cross-section than the contact surface the electrodes produced by modern lithography and structuring techniques getting produced. They form during programming of a TMO memory cell first several filaments out until a first filament is the top and the lower electrode shorts. This completes the further training of the other filaments, starting from the Short circuit through the first continuous filament not further to grow. Is a first continuous filament once formed, so this filament can by a corresponding extinguishing current be interrupted again. The resulting interruption of the Filaments leads the TMO memory cell back to a high-impedance state.

Reprogramming the ÜMO memory cell into a low-resistance state can therefore be based on a change in the resistance in that region of the initially formed filament Therefore, it requires much less energy and time than a first transfer of the UM memory cell from an initial high-impedance state to a low-impedance state. The first formation of filaments usually requires, depending on the defect concentration, a significantly higher programming voltages than switching a TMO memory cell back and forth during normal operation. A first programming with a high voltage, however, is usually necessary in the first place.

The however, high initial programming voltages are in conflict with the integration of UMM memory cells. The smaller ÜMO memory cells be structured, the lower the breakdown voltage the insulators used and the ÜMO layer. The creation of a higher voltage in the area of the breakdown voltage, the memory cell changes adversely and can lead to their failure after only a few switching cycles.

Conventional UM memory cells use an oxidation deficit of the TMO layer to reduce the initial resistance and thus also to reduce the required initial programming voltage. In this case, the transition metal oxide used is formed with less oxygen than stoichiometrically possible. As a result, both the initial electrical resistance at room temperature and its temperature dependence are lowered or flattened. A characterization of the temperature dependence of a resistance ρ (T) can generally with an activation energy E by ρ (T) = ρ 0 exp {-E / (kT)} (1) where k represents the Boltzmann constant and is approximately 1.38 × 10 ^-23 J / K, and where, according to (1), the resistance ρ (T) decreases for increasing temperatures T.

A Lowering the temperature dependence of resistance to that the ÜMO layer can be programmed with a lower voltage, and thus lowered the required programming voltage even during heating can be. In the formation of oxygen-deficient transition metal oxides However, both occur in the production as well as in regular operation Problems on. Such is the controlled and well-defined oxygen deficient deposition of transition metal oxides difficult and not reproducibly possible in a satisfactory manner. Further can oxygenate the finished structured OMO storage cell diffuse in and out of the cell, and the electrical Properties of the finished ÜMO storage cell can so a posteriori, especially during subsequent manufacturing steps, which may be part of a so-called back-end of line (BEOL), or even while change the operation.

It It is therefore an object of the present invention to provide an improved programmable resistive memory cell with a programmable resistance layer provide. It is a further object of the present invention a method of making a programmable resistive To provide memory cell with a programmable resistance layer. This task is accomplished by the programmable resistive memory cell according to claim 1 and the method of making a programmable resistive Memory cell according to claim 14 solved. Further advantageous embodiments of the invention are specified in the dependent claims.

According to one The first aspect of the present invention is a programmable one resistive memory cell having a first electrode, a programmable Resistor layer and provided with a second electrode. The Programmable resistance layer contains a first transition metal oxide and a second transition metal oxide.

According to one second aspect of the present invention is a method for Provided a resistive memory cell, the following Steps comprises: forming a first electrode, forming a programmable resistance layer and forming a second An electrode, wherein the programmable resistance layer is a first transition metal oxide and a second transition metal oxide contains.

By providing two transition metal oxides according to the invention, both the initial resistance of the programmable resistance layer at room temperature and the temperature dependence of the resistance of the programmable resistance layer can be set. By mixing a first transition metal oxide with a higher electrical initial resistance at room temperature and a steeper temperature dependence with a second transition metal oxide having a lower initial electrical resistance at room temperature and a flatter temperature dependence, a programmable resistive layer having an intermediate initial electrical resistance at room temperature and a second intermediate temperature dependence of the resistance can be formed. This advantageously reduces the required voltages and currents for programming the programmable resistance layer, and substantially reduces the energy requirement of a memory device or logic circuit having programmable resistive memory cells according to the invention reduced.

According to one embodiment of the present invention, the first and the second transition metal oxide formed by a transition metal. Thus, the inventive programmable Resistive memory cell with minimal use of materials and possible easy to be realized.

According to one another embodiment the present invention, the first transition metal oxide of a first transition metal and the second transition metal oxide from a second transition metal educated. Thus, advantageously, the initial resistance the programmable resistance layer at room temperature and the temperature dependence of the resistance of the programmable resistor layer in one preferably huge Area under recourse on the range of transition metals be set.

According to one another embodiment The present invention is at least one of the transition metal oxides highest Oxidation degree oxidized. The resistive memory cell according to the invention can therefore without elaborate Liner and diffusion barriers are carried out as an installation of Oxygen is reduced or not taking place in the mixed oxide and the properties of the programmable resistor layer not to be influenced. This not only simplifies the production, but allows also advantageously a further miniaturization and a higher Integration of the resistive memory cells. Furthermore, the Process for producing the resistive memory cell according to the invention simplified and made possible in a well-defined and advantageous manner a reproducible implementation of Manufacturing process. In particular, the resistive invention remains Memory cell even while Subsequent manufacturing steps, which are part of a so-called back-end of line (BEOL), and also while stable and reliable.

According to one another embodiment The present invention provides at least one of the transition metal oxides with one of the transition metals Niobium, titanium, nickel, zirconium, chromium, cobalt, manganese, vanadium, tantalum or iron formed. The transition metals mentioned allow in advantageously, forming stable transition metal oxide layers, which are also used in established manufacturing processes, such as in the CMOS process, integrate. By mixing oxides of two above called transition metals can also be advantageously for the programmable resistor layer favorable initial resistances at room temperature and their temperature dependencies. The Resistance layer may further contain nickel oxide and cobalt oxide, where on the one hand a reliable and stable programmable resistance layer can be formed and on the other hand, both the initial electrical resistance and their temperature dependence can be set in one area, so that the programming required voltages below the breakdown voltages of used insulators and the programmable resistor layer lie. Furthermore, the programmable resistance layer can be at least one of the metals strontium, lead, praseodymium, tungsten or calcium. These metals are used for doping and wear in an advantageous manner for precise Adjustment of the electrical parameters of the programmable resistor layer at. Furthermore, can the above metals with established and reproducible Method introduced into the programmable resistance layer become.

According to a further embodiment of the present invention, the initial electrical resistance of the programmable resistance layer is less than the initial electrical resistance of a high-resistance transition metal oxide layer, such as a nickel oxide, hafnium oxide or zirconium oxide, in particular less than 10 ⁹ Ωcm.

According to one another embodiment of the present invention the temperature dependence the electrical resistance of the programmable resistor layer flatter than the temperature dependence the electrical resistance of a nickel oxide layer, in particular with an activation energy less than 0.7 eV.

According to one another embodiment of the present invention the lower and / or the upper electrode of at least one of the metals tungsten, Platinum, titanium or palladium. The above metals, in general high-temperature melting metals, form in an advantageous manner the electrodes, as in the programmable resistor layer and in their environment locally occurring high temperatures the Do not change electrodes or the electrode material significantly.

According to one another embodiment The present invention is the programmable resistance layer surrounded by an insulating layer. Thus, individual resistive memory cells also be placed close to each other without any interaction neighboring memory cells to the reliability of the storage of logical states reduced.

According to another embodiment of the present invention is between the lower electrode and the programmable resistor a contact is disposed, wherein the contact is surrounded by an insulating contact-forming layer and wherein the contact reduces a contact area to the programmable resistance layer with respect to the surface of the lower electrode. The contact can also be carried out tapering down. Thus, during manufacture, the size of the contact can be adjusted and reduced by defined resetting, for example by polishing. The contact reduces the effective area from the electrode and thereby helps to reduce the formation of unwanted additional filaments while still maintaining the formation of at least one conductive filament to store a resistive state.

According to one another embodiment In accordance with the present invention, the formation of the programmable Resistive layer by reactive sputtering of an elemental target. Furthermore, can while of reactive co-sputtering, at least two transition metals are atomized in an oxygen-containing process atmosphere, wherein the oxygen partial pressure of the oxygen-containing process atmosphere at least saturated is, so the transition metals in their highest Oxidize the degree of oxidation. Furthermore, the formation of the programmable Resistive layer by RF sputtering of corresponding oxide targets respectively. The process atmosphere does not have to contain oxygen.

In order to is a stoichiometric ensures balanced formation of the two transition metal oxides, and local oxygen and oxidation deficiencies do not occur. Thus, the formed programmable resistive layer is both in terms of their initial resistance as well as in terms of their temperature-dependent Resistant adjustable and further by a saturated oxidation the transition metals stable. elaborate Diffusion protection barriers and other encapsulations can thus omitted. The process atmosphere In addition, an inert gas, e.g. Argon, included.

According to one another embodiment The present invention includes forming the lower electrode the steps: etching a trench in a substrate, filling the trench with a conductive Material and polishing of the conductive material. Is the substrate insulating, so can several lower electrodes or also conductor tracks for contacting several contacts are structured next to each other, these are electrically isolated from each other.

According to one another embodiment According to the present invention, the formation of the lower electrode further comprising the steps of: forming a contact molding layer; Forming a trench in the contact forming layer, filling in the trench in the contact forming layer with a conductive material, and polishing the contact forming layer and the conductive material in the trench. The trench can taper downwards in the contact forming layer be educated. The polishing of the conductive material in the trench and the contact forming layer can thus be used to reduce an upper area of the contact. The effective contact surface can thus not only be adjusted be changed and by a separate step of polishing, but can also be done sublithographically, i. the contact surface can possibly over existing lithographic restrictions further reduced become.

According to one another embodiment In the present invention, the polishing is carried out by a chemical-mechanical Process. Chemical-mechanical polishing processes (CMP) are already established Part of reproducible manufacturing processes and have a constant and well manageable material removal and can also be well defined Time points are stopped and thus also allow well-defined layer thicknesses.

preferred embodiments The present invention will now be described with reference to the accompanying drawings explained in more detail. It demonstrate:

1A and 1B schematically conventional programmable resistive memory cells;

2A to 2C schematically the course of a temperature-dependent resistance;

3A to 3C schematically a programmable resistive memory cell at various stages during manufacture according to a first embodiment of the present invention;

4A to 4H schematically a programmable resistive memory cell at various stages during manufacture according to a second embodiment of the present invention; and

5A and 5B schematically a programmable resistive memory cell as part of an integrated circuit according to a third embodiment of the present invention.

1A schematically shows a programmable resistive memory cell with a lower electrode 10 , a programmable resistor layer 11 and an upper electrode 12 , By applying electrical signals to the lower electrode 10 and upper electrode 12 can a stream through the pro programmable resistance layer 11 flow, which is the programmable resistance layer 11 locally heats up, which can change the electrical resistance locally. A finite local current density in the programmable resistive layer 11 leads to a local heating and thus overall to the formation of a conductive region 13 , as in 1B shown. Once a filament 13 a short circuit between the lower electrode 10 and the upper electrode 12 forms, the programmable resistive memory cell assumes a low-impedance state.

2A shows schematically the course of the temperature-dependent resistance of a nickel oxide layer. The resistance ρ is plotted against the temperature T. As can be seen, for example, in a temperature range from room temperature T ₁ to a T ₂ of about 300 ° C, the temperature-dependent resistance drops substantially linearly from 10 ⁸ to 10 ⁹ Ωcm to 10 ⁵ to 10 ⁶ Ωcm. Initially, therefore, has a low-defect stoichiometric nickel oxide at room temperature an electrical resistance of about 10 ⁹ Ωcm. Thus, a high voltage is required for conducting an electric current and for local heating by the programmable resistance layer. In low-defect stoichiometric layers, the breakdown voltage of the programmable resistance layer is reached with this voltage. Therefore, applying such a high voltage to the initial generation of conductive filaments in the programmable resistive layer may result in destruction or at least adverse change in the programmable memory cell or in a reduction in the number of possible switching cycles.

2 B shows schematically the course of the temperature-dependent resistance of a nickel oxide layer with different oxygen deficiency: as a solid line the course of a NiO _1-x layer, and as a dotted line the course of a NiO _{1-x '} layer. In this case, x often lies in a range of 0.15 to 0.65 and leads in this range to a significant change in the resistance in a range of 3 to 4 orders of magnitude. In order to achieve a well-defined initial electrical resistance and a well-defined temperature-dependent resistance curve of a NiO _1-x layer, the relevant layer of NiO _1-x must be deposited with a precision of ± 3% of the target value and this stoichiometric oxygen deficit must also be reliable retained in the nickel oxide layer. Both the reliable and reproducible deposition of a nickel oxide layer with a deficiency of x with an accuracy of ± 3% is difficult and can be maintained in a finished element only by elaborate diffusion barriers.

2C shows schematically the course of the temperature-dependent resistance of a mixture of two transition metal oxides, as shown here, cobalt oxide and nickel oxide. In this case, the mixture of the two transition metal oxides ÜMO ₁ and ÜMO _{2 takes place} in a mixing ratio M v = ÜMO 1 / (UEMO 1 + ÜMO 2 (2) where ÜMO ₁ and ÜMO ₁ denote the atomic portion of the first and second transition metal oxides, respectively. The ratio M _v sets both the initial electrical resistance at room temperature and the course of the temperature dependence of the electrical resistance of the mixed oxide layer. Advantageously, the mixing ratio M _v can be set reliably and reproducibly during the deposition, for example during sputtering by the corresponding sputtering rates, and this ratio mixing ratio M _v is stably maintained even without elaborate diffusion barriers or other measures in the programmable resistance layer. By using appropriate transition metal oxides, both the initial electrical resistance and the temperature dependence of the resistance of the programmable resistive layer can be adjusted within a wide range. Advantageous resistances can be achieved, for example, by a mixture of cobalt oxide and nickel oxide in a mixing ratio M _v of 0.1 to 0.15, or a maximum of 0.25, wherein a mixing ratio M _v in a range from 0 to 0.5 the resistance can be varied by about 6 orders of magnitude.

The 3A to 3C show schematically a resistive memory cell at various stages during manufacture according to a first embodiment of the present invention. As in 3A First, a lower electrode is shown 10 provided. On the electrode 10 will, as in 3B shown a programmable resistor layer 11 formed by, for example, reactive co-sputtering. During sputtering, DC, MF or RF plasma excitation can occur. At least two transition metals, a first transition metal 101 and a second transition metal 102 for use. The process atmosphere during the formation of the programmable resistance layer 11 contains oxygen 100 to form the corresponding oxides 110 . 120 , As shown, the process atmosphere contains at least as much oxygen 100 so that the atomized transition metals 101 and 102 oxidize in their highest degree of oxidation, and so, depending on the respective sputtering rate, a stable and fully oxidized first transition metal oxide 110 and a second transition metal oxide 120 in the programmable resistance layer 11 form. Possible oxides are, for example, nickel oxide, titanium dioxide, niobium oxide, hafnium oxide, zirconium oxide, chromium oxide, tantalum oxide, vanadium oxide, iron oxide or cobalt oxide. In this case, for example, nickel oxide, hafnium oxide and zirconium oxide have a relatively high resistance and, for example, chromium oxide, cobalt oxide, tantalum oxide or vanadium oxide has a relatively low resistance. The transition metal oxides used in this case have different resistances, so that a desired value of the initial resistance and a temperature dependence of the resistance is established by appropriate mixing of the two transition metal oxides. However, two different oxides of a transition metal can also be used to set the desired values, for example Fe ₂ O ₃ with FeO and / or Fe ₃ O ₄ .

As in 3C shown is on the programmable resistor layer 11 an upper electrode 12 deposited. Electrical signals at the electrodes 10 . 12 can then be used to form conductive filaments in the programmable resistor layer 11 and for interrogating the resistive state of the programmable resistor layer 11 be created. Suitable materials for the lower electrode 10 and the ready electrode 12 For example, tungsten, platinum, palladium or titanium.

The 4A to 4H show a resistive memory cell at various stages during manufacture according to a second embodiment of the present invention. First, as in 4A shown a substrate 40 provided. As in 4B is shown on the substrate 40 a ditch 400 educated. The substrate 40 For example, a silicon substrate or other already structured elements - as usual in semiconductor manufacturing - included. The ditch 400 in the substrate 40 serves to form a lower electrode 41 , as in 4C shown. The surface of the lower electrode 41 and the substrate 40 can be polished to provide a planar surface for the following process steps.

As in 4D shown is on the substrate 40 and the lower electrode 41 a contact forming layer 420 and a contact 430 educated. The contact forming layer 420 can be deposited by a CVD method, for example, SiO ₂ or Si ₃ N ₄ . Advantageously, in this case, the contact 430 a downwardly tapering shape. Furthermore, the opening in the contact forming layer 420 sublithographically, leaving a contact surface of the contact 430 to the lower electrode 41 as small as possible, but essentially small compared to conventional lithography process, can be formed. Starting from the in 4D shown contact forming layer 420 and the contact 430 may be the contact molding layer 420 and the contact 430 polished and thus reduced in height. By the downwardly tapering execution of the contact 430 becomes a surface of the contact 43 reduced by polishing, as in 4E shown. Is the desired surface of the contact 43 or the desired height of the contact 43 and the contact molding layer 42 achieved, so is a middle insulating layer 44 structured with a ditch. On the contact 43 becomes the trench with a programmable resistance layer 45 filled. Then it can be polished again.

On the programmable resistor layer 45 becomes an upper electrode 46 trained as in 4F shown. For passivation and protection of the programmable resistive memory cell may, as in 4G shown an upper insulating layer 47 be applied. According to this embodiment of the present invention, the male contact reduces consisting of the lower electrode 41 and the contact 43 the effective contact area between the contact 43 and the programmable resistor layer 45 , and thus limits the area in which a conductive filament 48 can form, strong, as in 4H shown.

With regard to the production and the materials of the electrodes or contacts 41 . 43 . 46 and the resistance layer 45 come in contact with the 3A to 3C described methods or materials are used.

The 5A and 5B schematically show a programmable resistive memory cell as part of an integrated circuit according to a third embodiment of the present invention. As in 5A shown are initially doped areas 51 in a substrate 50 intended. It is a doped area 51 over a via 53 with a bitline 55 connected. Word Lines 52 comprise a gate electrode and thus control the conduction between doped regions 51 , Doped areas 51 can also with vias 54 to lower electrodes 56 be coupled. Between the lower electrodes 56 and an upper electrode 58 is a programmable resistance layer 57 in which filaments can be formed and broken through electrical signals. The upper electrode 58 is via a via 59 connected to other components of the integrated circuit.

By activating the corresponding bit line 55 and the corresponding wordline 52 can be an electrical signal between the via 59 , the upper electrode 58 , the programmable resistance layer 57 , the lower electrode 56 , the Via 54 , two adjacent doped areas 51 - Coupled by means of the corresponding Wordline 52 , the Via 53 and the bitline 55 for programming or for reading a resitive state of a Area of the fourth programmable resistance layer 58 be created.

In 5B are a circuit diagram of two resistive memory cells 73 shown. The resisitive memory cells 73 are via selection transistors 72 on a common bitline 70 connected. By activating the selection transistors accordingly 72 with the wordlines 71 can be an electrical signal between the bitline 70 , via an enabled selection transistor 72 , a resistive memory cell 73 and the electrode 74 be created. This electrical signal may be used to carry a current through the corresponding resistive memory cell 73 for programming or reading out the resistive state of the resistive memory cell 73 respectively. An integrated memory module then contains a multiplicity of sensitive memory cells 73 each having a selection transistor 72 are assigned, and a corresponding, often mutually perpendicular array of bitlines 70 and a crowd of Wordlines 71 ,

0 Regarding the production and materials of the electrodes or contacts 56 . 58 and the resistance layer 57 come in contact with the 3A to 3C described methods or materials are used.

10

lower electrode

11

programmable resistance layer

12

upper electrode

13

senior Area

100

oxygen

101

first transition metal

102

second transition metal

110

first transition metal oxide

120

second transition metal oxide

40

substratum

41

lower electrode

42

Contact form layer

43

Contact

44

middle insulating

45

programmable resistance layer

46

upper electrode

47

upper insulating

48

senior Area

400

dig

420

Contact form layer

430

Contact

50

substratum

51

doped Area

52

Word Line

53

Via

54

Via

55

bitline

56

lower electrode

57

programmable resistance layer

58

upper electrode

59

Via

70

bitline

71

Word Line

72

selection transistor

73

resistive memory cell

74

electrode 74

Claims (29)

Programmable resistive memory cell with - a lower electrode ( 10 . 41 . 56 ); A programmable resistive layer ( 11 . 44 . 57 ); and with - an upper electrode ( 12 . 46 . 58 ), wherein the programmable resistive layer ( 11 . 44 . 57 ) a first transition metal oxide ( 110 ) and a second transition metal oxide ( 120 ) contains. A memory cell according to claim 1, wherein a single transition metal comprises the first transition metal oxide ( 110 ) and the second transition metal oxide ( 120 ). A memory cell according to claim 1, wherein a first transition metal ( 101 ) the first transition metal oxide ( 110 ) and a second transition metal ( 102 ) the second transition metal oxide ( 120 ). A memory cell according to any one of claims 1 to 3, wherein at least one of the transition metal oxides ( 110 . 120 ) is oxidized in the highest degree of oxidation. Memory cell according to one of claims 1 to 4, wherein the programmable resistance layer is at least one of the transition metals Niobium, titanium, nickel, zirconium, chromium, cobalt, manganese, vanadium, Contains tantalum, hafnium or iron. A memory cell according to claim 5, wherein the programmable resistive layer (16) 11 . 44 . 57 ) Contains nickel oxide and cobalt oxide. Memory cell according to one of claims 1 to 6, wherein the programmable resistance layer ( 11 . 44 . 57 ) contains at least one of the metals strontium, lead, praseodymium, tungsten, or calcium. Memory cell according to one of claims 1 to 7, wherein an initial electrical resistance of the programmable resistance layer ( 11 . 44 . 57 ) is smaller than the initial electrical resistance of a nickel oxide layer, and preferably less than 10 ⁹ Ωcm. Memory cell according to one of claims 1 to 8, wherein the temperature-dependent electrical resistance of the programmable resistance layer ( 11 . 44 . 57 ) is flatter than the temperature-dependent electrical resistance of a nickel oxide layer, preferably with an activation energy less than 0.7 eV. Memory cell according to one of claims 1 to 9, wherein the lower electrode ( 10 . 41 . 56 ) and / or the upper electrode ( 12 . 46 . 58 ) Contains / contains at least one of the metals tungsten, platinum, titanium or palladium. Memory cell according to one of claims 1 to 10, wherein the programmable resistance layer ( 11 . 44 . 57 ) is surrounded by an insulating layer. Memory cell according to one of claims 1 to 11, wherein between the lower electrode ( 10 . 41 . 56 ) and the programmable resistance layer ( 11 . 44 . 57 ) a contact ( 43 . 430 ), the contact ( 43 . 430 ) of an insulating contact forming layer ( 42 . 420 ) and the contact ( 43 . 430 ) a contact surface to the per programmable resistance layer ( 11 . 44 . 57 ) with respect to the surface of the lower electrode ( 10 . 41 . 56 ) decreased. A memory cell according to claim 12, wherein the contact ( 43 . 430 ) is tapered downwards. Method for producing a resistive memory cell, comprising the steps: - forming a lower electrode ( 10 . 41 . 56 ); Forming a programmable resistive layer ( 11 . 44 . 57 ); Forming an upper electrode ( 12 . 46 . 58 ), wherein the programmable resistive layer ( 11 . 44 . 57 ) a first transition metal oxide ( 110 ) and a second transition metal oxide ( 120 ) contains. The method of claim 14, wherein the first transition metal oxide ( 110 ) and the second transition metal oxide ( 120 ) are formed by a transition metal. The method of claim 14, wherein the first transition metal oxide ( 110 ) from a first transition metal ( 101 ) and the second transition metal oxide ( 120 ) of a second transition metal ( 102 ) is formed. Process according to any one of claims 14 to 16, wherein at least one of the transition metal oxides ( 110 . 120 ) is oxidized in the highest degree of oxidation. The method of any of claims 14 to 17, wherein forming the programmable resistive layer (16) 11 . 44 . 57 ) by a reactive sputtering. Process according to claim 16, wherein at least two transition metals ( 101 . 102 ) are atomized in an oxygen-containing process atmosphere, and wherein the oxygen partial pressure ( 100 ) of the oxygen-containing process atmosphere is at least saturated, so that the transition metals ( 101 . 102 ) are oxidized in their highest degree of oxidation. The method of claim 19, wherein the process atmosphere is an inert Contains gas, preferably argon. The method of any of claims 14 to 17, wherein forming the programmable resistive layer (16) 11 . 44 . 57 ) by sputtering at least two transition metal oxide targets. The method of claim 21, wherein a process atmosphere is an inert Contains gas, preferably argon. Method according to one of claims 14 to 22, wherein an initial electrical resistance of the programmable resistor layer ( 11 . 44 . 57 ) by a proportion of the first transition metal oxide ( 110 ) to the second transition metal oxide ( 120 ), and wherein the initial electrical resistance of the programmable resistor layer ( 11 . 44 . 57 ) is smaller than the initial electrical resistance of a nickel oxide layer, and preferably less than 10 ⁹ Ωcm. Method according to one of claims 14 to 23, wherein a temperature-dependent electrical resistance of the programmable resistance layer ( 11 . 44 . 57 ) by a proportion of the first transition metal oxide ( 110 ) to the second transition metal oxide ( 120 ), and wherein the temperature-dependent electrical resistance of the programmable resistance layer ( 11 . 44 . 57 ) is flatter than the temperature-dependent electrical resistance of a nickel oxide layer, preferably with an activation energy that is less than 0.7eV. A method according to any one of claims 14 to 24, wherein forming the lower electrode ( 10 . 41 . 56 ) comprises the steps of: - etching a trench ( 400 ) in a substrate ( 40 ); - filling the trench ( 400 ) with a conductive material; and - polishing the conductive material. The method of claim 25, further comprising the steps of: forming a contact molding layer; 420 ); Forming a trench in the contact forming layer ( 420 ); Filling in the trench in the contact forming layer ( 420 ) with conductive material; and polishing the contact-forming layer ( 42 . 420 ) and the conductive material in the trench so that a contact ( 43 ) surrounded by the contact-forming layer ( 42 ), on the lower electrode ( 41 ) is formed. The method of claim 26 wherein the trench tapers downwardly in the contact forming layer (16). 42 . 420 ) is formed. The method of claim 27, wherein polishing the conductive material in the trench and the contact forming layer (16). 42 . 420 ) for reducing an upper surface of the contact ( 43 . 430 ) he follows. A method according to any one of claims 26 to 28, wherein the polishing done by a chemical-mechanical process.