DE102006019372B4 - Arrangement of active elements and methods for testing an array of active elements - Google Patents

Abstract

An array of active elements comprising: a substrate including a display area and an edge area; a plurality of scan lines arranged on the substrate; a plurality of data lines disposed on the substrate, the data lines and scan lines including a plurality of pixel areas in the display area and a plurality of pixel test areas in the edge area; a plurality of pixel units disposed on the substrate and in the pixel areas connected to the scanning lines and the data lines, respectively; a plurality of test fields arranged on the substrate and in the edge region, each of the test fields being arranged in one of the pixel test regions and being connected to one of the data lines; and a plurality of second active elements disposed on the substrate and in the pixel test areas, the second active elements being always on and in each of the pixel test areas ...

Description

BACKGROUND OF THE INVENTION

Field of the invention

The present invention relates to an arrangement of active elements. In particular, the present invention relates to an array of active elements and a method for testing an array of active elements with high accuracy of testing.

Description of the associated technique

The demand for screens is getting bigger. For this reason, the industry is making great efforts in their research and development. Among various screen types, the flat screen takes the predominant role due to its excellent characteristics such as high picture quality, low installation depth, low power consumption and freedom from radiation.

Currently, the main types of flat panel displays include liquid crystal display (LCD), organic electro-luminescence display (OELD), and plasma display panel (PDP). Of the above, the LCD screen and the OELD screen are generally controlled by active elements to shorten the response time of screens.

In addition, due to the demand for higher resolution and smaller size, the technology of incorporating and integrating in-circuit integrated circuits (ICs) in video screens has gradually changed from on-board chip (COB) to tape-automated bonding (TAB). and then to Chip on Glass (COG), where there are fine trenches between the pins of integrated circuits.

1 Fig. 10 is a schematic diagram showing a display screen controlled by active elements using the conventional COG technology. With reference to 1 includes the display screen controlled by the active elements 100 the display area 102 and the border area 104 , The display area 102 includes a plurality of scanning lines 112 , a variety of data lines 114 and a plurality of pixel units 116 that with the scan lines 112 and the data lines 114 are connected. The border area 104 includes a variety of gate controls 120 and a variety of data controls 130 , The gate controls 120 are electrical with the scan lines 112 connected while the data controls 130 electrically with the data lines 114 are connected. In other words, the scanning lines become 112 and the data lines 114 each from the gate controllers 120 and the data controllers 130 controlled.

In the manufacturing process of the active flat screen closes to the completion of the flat screen 100 in 1 usually a circuit test to check if any errors in the circuit of the display screen during the manufacturing process 100 were generated. 2 shows the conventional distribution of test fields for testing the display screen 100 in 1 , With reference to 1 and 2 includes the border area 104 of the display screen 100 except the gate controls 120 and the data controllers 130 a variety of test fields 140 for testing the circuit. The test fields 140 are each with the receiving fields 132 the data controllers 130 (or the gate controls 120 ) connected.

In the above-mentioned circuit test, the tester uses the probe 108 to test signals to the test fields 140 to send. The test signals are transmitted via the test fields 140 to the display area 102 delivered to the pixel units 116 within the display area 102 to test. To save space in medium and small size display screens, the receiving fields are 132 the gate controls 120 and the data controllers 130 on the display screen in an intermediate manner, as in FIG 2 shown.

Furthermore, the sizes of and the distances between the test fields become 140 and the receiving fields 132 progressively smaller to increase the resolution of popular medium and small size display screens. For example, considering a 5.5-inch display screen, the area of a test field is 140 about 36 microns by 150 microns, and the distance d is about 24 microns. For test fields of this size, the probe used in the test must be 108 be smaller and more accurate. However, such probes are expensive and increase the cost of testing the display screen 100 ,

In addition, the accuracy of the test will inevitably worsen, since the probe 108 can key in wrong places and adjacent test signals can overlap during the circuit test, since the distance d between the test fields 140 becomes smaller.

In the US 2004/0119917 A1 US 5,143,842 discloses a liquid crystal display device having a substrate with a display and a peripheral area, scan lines disposed on the substrate, data lines, and test pads. The However, the type of connection according to the invention between the test fields and the data lines or scan lines as well as the advantage of using permanently active second elements on the substrate and in the pixel test areas has not been recognized.

In the US 2003/01800975 A1 An arrangement of active elements with pixel test areas is disclosed in which the test fields are arranged in one of the pixel test areas.

From the DE 103 17 628 A1 For example, an arrangement of active elements in the form of a TFT array substrate is known which has test fields in the edge region of the substrate, wherein each of the test fields is connected to one of the data lines or scan lines.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an array of active elements whose test fields help to reduce the difficulty in the circuit test and to increase the accuracy of the circuit test.

The present invention is also directed to a method for testing an array of active elements for improving the accuracy of the circuit test in active element arrays. According to the invention the object is achieved by the subject matters of the independent claims.

In accordance with one embodiment of the present invention, an array of active elements is provided. The arrangement comprises a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel units and a plurality of test fields. The substrate comprises a display area and a peripheral area. The scanning lines and the data lines are arranged on the substrate and each include a plurality of pixel areas and pixel test areas in the display area and the peripheral area. The pixel units are arranged in the pixel areas and connected to the scanning lines and the data lines, respectively. Finally, the test fields are located near the scan lines and / or the data lines and are disposed on the substrate and in the edge region. Each test field is connected to a data line or a scan line.

In an embodiment of the present invention, each pixel unit comprises a first active element and a pixel electrode. The first active element is connected to the corresponding scan line and the corresponding data line. The pixel electrode is formed of, for example, Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO, Indium Zinc Oxide) and is connected to the first active element.

In one embodiment of the present invention, each of the test fields is located in one of the pixel test areas and connected to the corresponding data line. The test fields are formed, for example, from indium tin oxide (ITO) or indium zinc oxide (IZO). Furthermore, the arrangement of active elements in one embodiment of the present invention further comprises a plurality of second active elements. The second active elements are arranged on the substrate and in the pixel test areas. The second active elements are always switched on and in each pixel test area the corresponding test field is connected to the corresponding data line via the corresponding second active element. In addition, the second active elements are, for example, thin-film transistors, and the source and drain of each thin-film transistor are connected together.

In accordance with another embodiment of the present invention, a method for testing an array of active elements is provided. The method is suitable for testing an array of active elements. The array of active elements includes a plurality of pixel structures and a plurality of pixel test structures. Each of the pixel structures includes a first active element while each of the pixel test structures comprises a second active element. The pixel test structures are each connected to the pixel structures. The method includes the steps of turning on the first active elements, turning on the second active elements, and providing a test signal for each of the pixel test structures to transmit the test signals to the pixel structures via the pixel test structures.

In an embodiment of the present invention, each pixel test structure of the array of active elements further comprises a pixel test electrode, and the step of providing the test signal further comprises providing the test signals for the pixel test electrodes. The test signals are transmitted from the pixel test electrodes to the pixel structures via the second active elements.

The sizes of and the distances between the test fields in the active element arrays according to the present invention are large enough to reduce the difficulty of the circuit test of active element arrays and to improve its accuracy. In addition, it is no longer necessary to spend a lot of money on expensive probes with high accuracy.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a more thorough understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

1 Fig. 10 is a schematic diagram showing a display screen controlled by active elements using the conventional COG technology.

2 shows the conventional distribution of test fields for testing the display screen 100 in 1 ,

3 Fig. 10 is a schematic diagram showing a part of an arrangement of active elements according to the first embodiment of the present invention.

4 Fig. 10 is a schematic diagram showing a part of an arrangement of active elements according to the second embodiment of the present invention.

5 Fig. 12 is a schematic diagram showing a part of an arrangement of active elements according to the third embodiment of the present invention.

6 Fig. 12 is a schematic diagram showing part of a general arrangement of active elements.

7 FIG. 5 is the flow diagram of a method for testing an array of active elements according to one embodiment of the present invention. FIG.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. As far as possible, the same reference numbers are used in the drawings and in the description when reference is made to the same or similar parts.

The present invention uses test pixels (dummy pixels) present in general arrangements of active elements as test fields to transmit test signals so as to prevent adjacent signals from interfering with each other in the circuit test. The following are detailed descriptions of the embodiments of the present invention.

3 Fig. 10 is a schematic diagram showing a part of an arrangement of active elements according to the first embodiment of the present invention. With reference to 3 includes the arrangement 300 of active elements the substrate 302 , a variety of scanning lines 312 , a variety of data lines 314 , a variety of test fields 316 and a plurality of pixel units 320 , The substrate 302 is divided into two areas, namely the display area 304 and the border area 306 , The scan lines 312 and the data lines 314 are on the substrate 302 arranged and comprise a plurality of pixel areas 305 in the display area 304 , In addition, the scan lines include 312 and the data lines 314 a variety of pixel test areas 307 in the border area 306 ,

In addition, each of the pixel units 320 in a single pixel area 305 arranged and a pixel unit 320 includes a first active element 322 and a pixel electrode 324 , The pixel electrode 324 is with the first active element 322 connected, and the first active element 322 is with a scan line 312 and a data line 314 connected. The first active element 322 controls the pixel electrode 324 in response to signals coming from the scan line 312 and the data line 314 be received. In one embodiment of the present invention, the first active element is 322 for example, a thin film transistor, and the pixel electrode 324 is formed, for example, from indium tin oxide (ITO) or indium zinc oxide (IZO).

With reference to 3 have the test fields 316 in this embodiment, the same width w as the pixel electrodes 324 , In addition, because the transparent electrodes 326 in the pixel test areas 307 also with the data lines 314 During the test, the probe (not shown) connects test signals to the test fields 316 or the transparent electrodes 326 supply, allowing the test signals over the data lines 314 to the pixel units 320 be transmitted. In other words, the transparent electrodes 326 as part of the test fields 316 to be viewed as. In one embodiment of the present invention, the width w of a test field is 316 for example 63 microns and the total length L of a test field 316 together with a transparent electrode 326 is for example 508 microns. That is why the size of a test field 316 enough so that the probe is prevented from feeling in wrong places during the circuit test.

In this embodiment, the test fields are 316 with the data lines 314 connected. So can test signals over the scan lines 312 or the data lines 314 to the pixel units 320 be transmitted. Therefore, the present invention is not limited by whether the test fields for transmitting the test signal with the data lines 314 or the scan lines 312 are connected.

4 Fig. 10 is a schematic diagram showing a part of an arrangement of active elements according to the second embodiment of the present invention. With reference to 4 are the test fields in this embodiment 416 with the scan lines 312 connected. The pixel areas 305 For example, the storage capacitors Cs. The test fields 416 are, for example, between the bus electrodes connected to the storage capacitors Cs 350 arranged. In particular, in this arrangement, the distance D between adjacent test fields 416 For example, to be increased to 242 microns, the difficulty in testing the arrangement 400 of active elements and increase the accuracy. In addition, the length L of a test field 416 for example, 275 microns and the width w of a test field 416 for example, 50 microns. Of course, the size of the test fields 416 sufficient to prevent the probe (not shown) from testing the assembly 400 from active elements in wrong places.

In addition, the present invention can directly use electrodes arranged in the pixel test areas as test fields and thus achieves advantages similar to those of the above-mentioned embodiments. This will be explained with reference to the following embodiment.

5 Fig. 12 is a schematic diagram showing a part of an arrangement of active elements according to the third embodiment of the present invention. It should be noted that the main components of the arrangement 500 of active elements in 5 essentially the same as the main components of the arrangement 300 of active elements in 3 , For this reason, only the differences between the arrangement will be described below 500 of active elements and the arrangement 300 of active elements.

With reference to 5 become the test fields 516 on the substrate 302 arranged. Each of the test fields 516 is in a single pixel test area 307 arranged and is connected to a corresponding data line 314 connected. It should be noted that in a preferred embodiment, the test fields are, for example, transparent electrodes made in the same step of the manufacturing process as the pixel electrodes 324 , In other words, the test fields 516 for example, formed of the same material as the pixel electrodes 324 namely ITO or IZO.

In particular, the arrangement comprises 500 of active elements in this embodiment, for example, a plurality of second active elements 318 that are always on. The second active elements 318 For example, thin film transistors are used, and the source and drain of each of the thin film transistors are connected together. Each of the second active elements 318 is in a pixel test area 307 arranged and the test field 516 in every pixel test area 307 is with the data lines 314 via a second active element 318 connected.

Again with reference to 5 be in the test of the arrangement 500 of active elements, the test signals after the tester via the feeler (not shown) to the test fields 516 has delivered over those with the test fields 516 connected data lines 324 transferred to each of the pixel units 320 to test. In this embodiment, the size of a test field becomes 516 according to the size of a pixel test area 307 determined, and the size of a pixel test area 307 is generally the same as that of the pixel area 305 , That's why the size of the test fields 516 enough to prevent the probe from feeling in wrong places during the circuit test.

In this embodiment, the second active elements are 318 in the pixel test areas 307 the arrangement 500 always turned on, leaving the electrodes in the pixel test areas 307 as the test fields 516 can be used, so that in the arrangement 500 is saved by active elements installation space. In addition, the test fields 516 in the same step of the manufacturing process as the pixel electrodes 324 , Therefore, the manufacturing price of the arrangement 500 of active elements may be lower than that of the prior art, since the step of producing the test fields is not necessary.

Although, however, the second active elements 318 in the pixel test areas 307 the same conventional active elements as the first active elements 322 in the pixel area 305 However, the present invention may still be the transparent ones in the pixel test areas 307 arranged electrodes directly as the test fields 516 use to send test signals to the pixel units 320 in the display area 304 to deliver. This will be explained with reference to the following embodiment.

6 Fig. 12 is a schematic diagram showing part of a general arrangement of active elements. 7 FIG. 5 is the flow diagram of a method for testing an array of active elements according to one embodiment of the present invention. FIG. First of all, with reference to 6 the order 600 of active elements a variety of pixel structures 610 in the display area 602 and a plurality of pixel test structures 620 in the edge area 604 are arranged. The pixel structures 610 divide the scan lines 606 and the data lines 608 with the pixel test structures 620 , In other words, the pixel test structures are 620 each over the scan lines 606 or the data lines 608 with the pixel structures 610 connected. In addition, the pixel structures include 610 furthermore, the first active elements 612 and the pixel electrodes 614 , The first active elements 612 are with the scan lines 606 and the data lines 608 connected and the pixel electrodes 614 are with the first active elements 612 connected. Similarly, the pixel test structures include 620 furthermore, the second active elements 622 and the pixel test electrodes 624 , The second active elements 622 are with the scan lines 606 and the data lines 608 connected and the pixel test electrodes 624 are with the second active elements 622 connected.

With reference to 6 and 7 be in the test of the arrangement 600 of active elements the first active elements 612 first turned on, as described in step S700. The first active elements 612 For example, these are turned on by sending signals to the scan lines 606 delivered with the first active elements 612 are connected. This is followed by step S702, in which the second active elements 622 be turned on. Similarly, the second active elements become 622 This turns on signals to those with the second active elements 622 connected scan lines 606 to be delivered.

Finally, in step S704, test signals are sent to each of the pixel test structures 620 delivered to the test signals via the pixel test structures 620 to the pixel structures 610 to transfer to the pixel structures 610 to test. Here, the test signals become, for example, by inputting the test signals to the pixel test electrodes 624 provided. For example, in one embodiment of the present invention, the test signals are applied to the pixel test electrodes by probes (not shown) 624 delivered. At this time, the second active elements are 622 already switched on, the test signals are transmitted via the pixel test electrodes 624 to the data lines 608 transmitted and then over the data lines 608 to the pixel electrodes 614 every pixel structure 610 transferred to the functions of the pixel structures 610 to test.

In view of the foregoing, this embodiment uses the pixel test electrodes 624 in the pixel test structures 620 directly as test fields to the pixel structures 610 to test. In other words, the arrangement requires 600 no additional test fields from active elements to receive test signals. This feature not only saves the installation space of the arrangement 600 of active elements, but it also saves manufacturing costs.

Overall, the sizes of the test pads in the active device arrays of the present invention are sufficient to allow testers to easily place the probes on the proper test pads during the circuit test. In other words, the present invention helps reduce the difficulties of the circuit test of active element arrays. In addition, it is no longer necessary to spend a lot of money on expensive probes with high accuracy.

In addition, the distances between the test fields of the active element arrays according to the present invention are also sufficient to prevent test signals on adjacent test arrays from interfering with each other during the circuit test. For this reason, it is possible to obtain test results with high accuracy from the arrangements of active elements according to the present invention.

Further, the method for testing an array of active devices according to the present invention not only saves the installation space of test panels on conventional display screens, but also saves a step in the manufacture of the test panels, thereby reducing the manufacturing cost of active element arrays becomes.

Claims (7)

An array of active elements, comprising: a substrate comprising a display area and a peripheral area; a plurality of scanning lines arranged on the substrate; a plurality of data lines disposed on the substrate, the data lines and the scan lines including a plurality of pixel areas in the display area and a plurality of pixel test areas in the edge area; a plurality of pixel units disposed on the substrate and in the pixel areas, the each connected to the scanning lines and the data lines; a plurality of test pads disposed on the substrate and in the edge region, each of the test pads disposed in one of the pixel test areas and connected to one of the data lines; and a plurality of second active elements disposed on the substrate and in the pixel test areas, wherein the second active elements are always turned on and in each of the pixel test areas the corresponding test field is connected to the corresponding data line via the corresponding second active element. The array of active elements of claim 1, wherein each of the pixel units comprises: a first active element connected to the corresponding scan line and the corresponding data line; and a pixel electrode connected to the first active element. The array of active elements according to claim 2, wherein the pixel electrodes are formed of indium tin oxide (ITO) or indium zinc oxide (IZO). The array of active elements according to claim 1, wherein the first test fields are formed of indium tin oxide (ITO) or indium zinc oxide (IZO). The array of active elements according to claim 1, wherein the second active elements are thin film transistors and the source and drain of each thin film transistor are interconnected. A method of testing an array of active elements suitable for testing an array of active elements, the array of active elements comprising a plurality of pixel structures and a plurality of pixel test structures, and each of the pixel structures comprises a first active element and each the pixel test structures comprises a second active element and the pixel test structures are connected to the pixel structures and the method comprises: Switching on the first active elements; Switching on the second active elements; and Providing a test signal for each of the pixel test structures to transmit the test signals to the pixel structures. The method for testing an array of active elements according to claim 6, wherein each pixel test structure of the array of active elements further comprises a pixel test electrode, and the step of providing the test signals further comprises: Providing the test signals for the pixel test electrodes to transmit the test signals to the pixel structures via the pixel test electrodes.

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