DE102006015789B4 - Processor arrangement, method for exchanging configuration data and / or communication data between a first processor and a plurality of second processors and computer program element - Google Patents

Abstract

Processor arrangement
• with a first processor,
• with several second processors,
With a first coupling unit for coupling the first processor to the plurality of second processors,
With a coupling memory coupled to the first processor for storing configuration data and / or communication data, and
With a second coupling unit for coupling the coupling memory with the second processors
With an access control unit coupled to the coupling memory and the second coupling unit, which is arranged between the first coupling unit and the coupling memory and at the same time is arranged between the second coupling unit and the coupling memory and which is set up for allocating access rights for accessing the coupling memory that corresponding real-time requirements are ensured
Wherein the first processor or at least one of the second processors store configuration data for at least one further of the second processors in the coupling memory, and
• wherein the second processors the configuration data by means of the second coupling unit ...

Description

The invention relates to a processor arrangement, a method for exchanging configuration data and / or communication data between a first processor and a plurality of second processors and a computer program element.

A modem baseband processor arrangement typically includes a central microcontroller and a plurality of dedicated hardware accelerators or peripheral components coupled to the central microcontroller via a peripheral bus. By means of the peripheral bus, the central microcontroller acts as a bus master unit and configures or reconfigures, for example, the peripheral components which act as bus slave devices on the peripheral bus.

Out DE 697 33 314 T2 For example, a CPU is known that writes code and data to system memory via a bus to configure a microcontroller to perform desired functions. The microcontroller accesses code and data written by the CPU over the same bus.

Out US 5,872,919 A For example, a communication system is known that can recognize and adapt to various types of communication protocols.

Out DE 10 2004 046 612 A1 For example, a communication unit is known in which an application processor can access various peripheral devices and memory devices via a bus.

A standard modem baseband processor arrangement 100 is in 1 shown.

The modem baseband processor arrangement 100 has a central microcontroller 101 on, by means of a first interface 102 with a local store 103 is coupled. Furthermore, the central microcontroller 101 by means of a second interface 104 with a master peripheral bus 105 coupled, with which n peripheral units 106 . 107 . 108 where n is any natural number.

In a real-time environment, otherwise expressed in an application with real-time requirements, it is necessary that the central microcontroller 101 the peripheral units 106 . 107 . 108 in real time depending on the specific and individual latency and / or data throughput requirements of the respective peripheral units 106 . 107 . 108 configured or reconfigured.

Even in the event that the central microcontroller 101 could generate the required configuration data in advance and thus on time and this example, in the form of a table in the local memory 103 would still exist for the central microcontroller 101 a task in writing or copying the previously stored configuration data from the local memory 103 in real time to the respective peripheral unit 106 . 107 . 108 ,

In order to meet all specific timing conditions, it is usually necessary to have the computing speed of the central microcontroller 101 beyond the computational speed that would be required to accomplish only the task of generating the configuration data.

2 shows another conventional modem baseband processor arrangement 200 ,

Same or identical units in the modem baseband processor arrangement 200 compared to the modem baseband processor arrangement 100 according to 1 are in 2 provided with identical reference numerals and will not be described again in detail below.

Additionally, in the modem baseband processor arrangement 200 according to 2 a DMA controller 201 (Direct Memory Access) provided which by means of a first DMA controller interface 202 with the local store 103 and by means of a second DMA controller interface 203 with the peripheral bus 105 connected is.

The DMA controller 201 On request, copies the configuration data stored in local storage 103 are stored from the local memory 103 to the respective specific peripheral unit 106 . 107 . 108 , bringing the computational burden of the central microcontroller 101 is reduced.

In both processor arrangements described above 100 . 200 becomes the central microcontroller 101 or the DMA controller 202 in other words, it receives an interrupt when a time event to configure a specific peripheral unit 106 . 107 . 108 occurs.

In a system with many configuration events or re-configuration events, it is not trivial to predict when to set the timing events for configuration or reconfiguration at the beginning of the corresponding operation, in any event, even at worst. Case consideration to ensure that a specified time constraint is never missed under the real-time configuration conditions.

3 shows in a time diagram 300 the timing of the configuration process for the modem baseband processor arrangement 200 according to 2 ,

It is assumed that the configuration process is based on a first timer event TE1 301 starts. In a system with processes (in 3 symbolized by means of a first process G1 302 and a second process C1 303 ), which can be interrupted, it is not trivial to calculate the timing in advance and to ensure that the configuration is completed and the configuration data before expiration of the time limit to the peripheral units 106 . 107 . 108 be transmitted.

In an in 3 right illustrated second diagram 310 is shown that to a logic event LE2 311 configuration data generation process G2 taking place 312 the configuration data for the peripheral unit 107 previously generated (based on the second logic event LE2 311 available input data). In this case, only one configuration data write process C2 is based 314 on a second timer event TE2 313 ,

The invention is based on the problem of providing real-time requirements when exchanging configuration data and / or communication data between a first processor and a plurality of second processors in a processor arrangement, without having to increase the computing power of the first processor.

The problem is solved by a processor arrangement, by a method for exchanging configuration data and / or communication data between a first processor and a plurality of second processors, and by a computer program having the features according to the independent patent claims.

A processor arrangement comprises a first processor and a plurality of second processors. Furthermore, it has a first coupling unit for coupling the first processor to the plurality of second processors and a coupling memory for storing configuration data and / or communication data. The first processor is coupled to the coupling memory and the second processors are coupled by means of a second coupling unit for coupling the coupling memory. An access control unit is coupled to the coupling memory and the second coupling unit, and is disposed between the first coupling unit and the coupling memory and is at the same time disposed between the second coupling unit and the coupling memory, and is arranged to assign access rights for accessing the coupling memory, so that corresponding ones Real-time requirements are guaranteed. The first processor or at least one of the second processors stores configuration data for at least one further of the second processors in the coupling memory. The second processors write the configuration data by means of the second coupling unit in the coupling memory or read from the coupling memory. The first coupling unit is a first bus or a plurality of separate first electrically conductive connections. The second coupling unit is a second bus or a plurality of separate second electrically conductive connections. The first processor is not coupled to the second coupling unit. The first processor has no access to the second coupling unit. Each of the second processors is set up to read its configuration data from the coupling memory at a re-configuration time specified for the respective second processor.

In a method for exchanging configuration data and / or communication data between a first processor and a plurality of second processors, data is exchanged between the first processor and the plurality of second processors by means of a first coupling unit for coupling the first processor to the plurality of second processors. Configuration data for at least one other of the second processors is stored by the first processor or at least one of the second processors in a coupling memory, wherein the second processors write the configuration data by means of a second coupling unit in the coupling memory or read from the coupling memory. The first processor is not coupled to the second coupling unit. An access control unit coupled to the coupling memory and the second coupling unit assigns access rights for accessing the coupling memory, so that corresponding real-time requirements are ensured, wherein the access control unit is arranged between the first coupling unit and the coupling memory and at the same time arranged between the second coupling unit and the coupling memory is. The first coupling unit is a first bus or a plurality of separate first electrically conductive connections, and the second coupling unit is a second bus or a plurality of separate second electrically conductive connections. The first processor has no access to the second coupling unit. Each of the second processors reads its configuration data from the coupling memory to a specified for the respective second processor re-configuration time.

A computer program for exchanging configuration data and / or communication data between a first processor and a plurality of second processors has the above-described steps when executed by one or more processors.

According to one exemplary embodiment of the invention, an additional coupling unit between the second processors and the coupling memory is illustratively provided, by means of which the configuration data and / or communication data which are temporarily stored in the coupling memory are exchanged, without additionally burdening the computing power of the central microcontroller. The first processor is connected, for example by means of the first coupling unit, to the coupling memory and writes the configuration data and / or communication data into the coupling memory or, for example, reads out communication data therefrom.

Exemplary embodiments of the invention will become apparent from the dependent claims. The described embodiments of the invention relate, as far as appropriate, the processor arrangement, the method for exchanging configuration data and / or communication data between a first processor and a plurality of second processors and the computer program element.

The first processor may be configured as a master processor and the second processors may be configured as slave processors.

At least two, according to an embodiment of the invention, all second processors of the plurality of second processors may be designed differently, wherein at least one of the second processors may be a processor specialized in its design (eg processor architecture) for at least one predetermined function.

Illustratively, the second processors according to this embodiment of the invention form inhomogeneous components, for example peripheral units, which are integrated in a different temporal context and, for example, have different temporal requirements with regard to a configuration and / or reconfiguration and / or for communication with other components. In other words, a distributed system with a plurality of processors is formed in this way, in which, due to the different time requirements with regard to the configuration and / or communication, in general with regard to the data exchange with the first processor, very different real-time requirements can arise Access conflicts can occur in the access to the respective required components, wherein it could come in the context of communication with the first processor to a beat, which are avoided by the embodiments of the invention.

At least one second processor of the plurality of second processors may be a peripheral component processor which is controllable with regard to its setting or its operation, for example by the first processor, for example by means of configuration data specifically provided for the respective second processor, which is the second processor can be specified by the first processor.

• • Universal Mobile Telecommunications System (UMTS);
• • General Packet Radio Services (GPRS);
• • Enhanced Data-Rates for GSM Evolution (EDGE);
• • Code Division Multiple Access 2000 (CDAM2000);
• • Freedom of Mobile Multimedia Access (FOMA).

At least one second processor of the plurality of second processors may be a peripheral component processor, which is set up to provide at least one function of a physical communication protocol layer of a radio communication device, for example a mobile radio communication device and, for example, a mobile radio communication device of the third Generation, such as a mobile communication device, which is set up according to one of the following mobile communication standards:

• • Universal Mobile Telecommunications System (UMTS);
• • General Packet Radio Services (GPRS);
• • Enhanced Data Rates for GSM Evolution (EDGE);
• • Code Division Multiple Access 2000 (CDAM2000);
• • Freedom of Mobile Multimedia Access (FOMA).

• • Kanalkodierung, anders ausgedrückt, der zweite Prozessor ist in diesem Fall ein Kanalkodierer;
• • Kanaldekodieren von Daten, anders ausgedrückt, der zweite Prozessor ist in diesem Fall ein Kanaldekodierer;
• • Messen von Kanaleigenschaften, anders ausgedrückt, der zweite Prozessor ist in diesem Fall eine Messeinrichtung zum Messen von Signal-Empfangsparametern in einem bestimmten vorgegebenen Zeitbereich und/oder Frequenzbereich, d. h. in einem oder mehreren vorgegebenen Zeitschlitzen und/oder Frequenzkanälen;
• • Empfangen von Funksignalen, anders ausgedrückt ist der zweite Prozessor in diesem Fall ein Funk-Empfänger;
• • Senden von Funksignalen, anders ausgedrückt ist der zweite Prozessor in diesem Fall ein Funksender,
• • Suchen von Funk-Synchronkanälen, anders ausgedrückt ist der zweite Prozessor in diesem Fall eine Sucheinheit (Searcher) zum Suchen von Synchronkanälen in dem Funkbereich, beispielsweise in dem Mobilfunk-Bereich, beispielsweise einer Mobilfunkzelle, in welchem sich die Prozessor-Anordnung befindet, wenn die Prozessor-Anordnung Teil einer Funk-Kommunikationseinrichtung, beispielsweise einer Mobilfunk-Kommunikationseinrichtung, ist.

The second processors may be configured to each perform at least one of the following functions:

• Channel coding, in other words, the second processor is a channel coder in this case;
• Channel decoding data, in other words, the second processor is a channel decoder in this case;
• In other words, the second processor is a measuring device for measuring signal reception parameters in a specific predetermined time range and / or frequency range, ie in one or more predetermined time slots and / or frequency channels;
• Receiving radio signals, in other words, the second processor is a radio receiver in this case;
• Transmitting radio signals, in other words the second processor is a radio transmitter in this case,
• • Searching radio synchronous channels, in other words, the second processor in this case is a searcher for searching Synchronous channels in the radio range, for example in the mobile area, for example a mobile radio cell in which the processor arrangement is located, when the processor arrangement is part of a radio communication device, such as a mobile communication device.

For example, in the field of radio transmission and radio communication in a communication device, for example in a communication terminal, the embodiments of the invention are very advantageously used, since in this application more and more performance and functionality is shifted to the peripheral components and thus the processors have an ever greater performance and more and more communication with the first processor, in this case, the central microcontroller, thus, under real-time requirements, more and more communication events, also referred to as timing events or interrupts occur.

The first coupling unit is a first bus or a plurality of separate first electrically conductive connections, wherein according to one embodiment of the invention, the first coupling unit is a master peripheral bus for coupling the first processor to the plurality of second processors.

According to another embodiment of the invention, it is provided that the processor is coupled to the first coupling memory by means of the first coupling unit. The second coupling unit is a second bus or a plurality of separate second electrically conductive connections.

The coupling memory may be a volatile memory or a non-volatile memory, for example a random access memory (RAM), according to an embodiment of the invention, a statistical random access memory, for example a synchronous random access memory (synchronous SRAM). It may also be any nonvolatile memory, such as flash memory, such as an Electrically Erasable Read Only Memory (EEPROM), such as a floating gate flash memory or a nitrided read only memory (NROM) flash -Storage. Alternatively, the coupling memory may be a volatile dynamic random access memory (DRAM).

The configuration data are configuration data for at least one of the second processors of the plurality of second processors, with which, for example, the operation of the respective second processor is predetermined.

Thus, the configuration data represent, for example, operating parameters for the respective second processor.

Furthermore, an access control unit coupled to the coupling memory and the second coupling unit is provided, which is set up for assigning access rights for accessing the second coupling unit, wherein the access control unit is for example a bus arbiter which controls the accesses to the second coupling unit.

According to another embodiment of the invention, at least one third processor is provided, which is coupled to the coupling memory, for exchanging communication data with at least one second processor of the plurality of second processors. In other words, this embodiment clearly indicates that other peripheral components can also be provided in the processor arrangement, which likewise can exchange data with the first processor or else the plurality of second processors by means of the coupling memory.

The third processor may be a processor of a functionally higher, in other words higher-level communication protocol layer than the physical communication protocol layer, for example in the sense of the OSI (Open System Interconnection) reference model of the ISO (International Standardization Organization).

At least one of the third processors may be a medium access control processor (MAC), in other words a processor that provides the function of the MAC communication protocol layer.

Further, at least one of the third processors may be a radio link control processor, in other words a processor that provides the function of the Radio Link Control Communication Protocol (RLC) layer.

According to yet another embodiment of the invention, at least one of the third processors may be a radio resource control processor, in other words a processor providing the function of the radio resource control communication protocol layer (RRC).

Thus, according to various embodiments of the invention, one of the third processors may be a layer 2 processor or a layer 3 processor.

The third processor can also be a processor that does not have any function in itself However, for example, a crypto-processor that is configured to encrypt and / or decrypt data according to a correspondingly provided encryption algorithm.

At least one of the third processors may be a peripheral component processor configured to provide at least one function of a physical communication protocol layer, a second generation mobile communication device, for example according to GSM.

Although in the following the embodiments only describe mobile radio communication devices, it should be pointed out that the invention can be applied to any processor arrangement, also in the area of fixed network data transmission, particularly suitable in the area of layer 1 communication (physical layer ) between two communication devices, for example, each modem, in which at least a part of the problems presented above occur.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Show it

1 a modem baseband processor arrangement;

2 another modem baseband processor arrangement;

3 a timing diagram in which a configuration process for the modem baseband processor arrangement according to 2 is shown;

4 a communication system according to an embodiment of the invention;

5 a representation of a protocol structure of the UMTS air interface;

6 a modem baseband processor arrangement of a mobile communication terminal according to a first embodiment of the invention;

7 Timing diagrams in which a configuration process for the modem baseband processor arrangement according to 6 is shown;

8th a modem baseband processor arrangement of a mobile radio communication terminal according to a second embodiment of the invention; and

9 a message flow diagram in which the message flow is shown according to an embodiment of the invention.

4 shows a UMTS mobile communication system 400 for the sake of simplicity, in particular, the components of the UMTS Terrestrial Radio Access Network (UTRAN), which comprises a plurality of Radio Network Subsystems (RNS). 401 . 402 each having means of a so-called Iu interface 403 . 404 with the core UMTS network (CN) 405 are connected. A mobile network subsystem 401 . 402 each has a wireless network controller (RNC) 406 . 407 on and one or more UMTS base stations 408 . 409 . 410 . 411 which according to UMTS are also called NodeB.

Within the mobile access network, the mobile network control units are 406 . 407 the individual mobile network subsystems 401 . 402 by means of a so-called Iur interface 412 connected with each other. Any mobile network control unit 406 . 407 monitors in each case the assignment of mobile radio resources of all mobile radio cells in a mobile radio network subsystem 401 . 402 ,

A UMTS base station 408 . 409 . 410 . 411 is in each case by means of a so-called Iub interface 413 . 414 . 415 . 416 with one of the UMTS base station 408 . 409 . 410 . 411 associated mobile network control unit 406 . 407 connected.

Every UMTS base station 408 . 409 . 410 . 411 vividly biases one or more mobile radio cells (CE) within a mobile radio network subsystem 401 . 402 on. Between a respective UMTS base station 408 . 409 . 410 . 411 and a subscriber device 418 (User Equipment, UE), hereinafter also referred to as a mobile radio communication terminal, in a mobile radio cell, message signals or data signals by means of an air interface, referred to as UMTS Uu-air interface 417 , preferably transmitted according to a multiple access transmission method.

For example, according to the UMTS FDD (Frequency Division Duplex) mode, a separate signal transmission in the uplink and downlink direction (uplink: signal transmission from the mobile radio communication terminal 418 to the respective UMTS base station 408 . 409 . 410 . 411 ; Downlink: Signal transmission from the respective assigned UMTS base station 408 . 409 . 410 . 411 to the mobile communication terminal 418 ) achieved by a corresponding separate allocation of frequencies or frequency ranges.

Several subscribers, in other words several activated or in the mobile network access network registered mobile communication terminals 418 in the same mobile radio cell preferably by means of orthogonal codes, in particular according to the so-called CDMA method (Code Division Multiple Access) separated by signal technology.

In this context, it should be noted that in 4 for the sake of simplicity, only one mobile communication terminal 418 is shown. However, in general, any number of mobile communication terminals 418 in the mobile radio system 400 intended.

The communication of a mobile communication terminal 418 with another communication device can be constructed by means of a complete mobile communication link to another mobile communication terminal, alternatively to a landline communication device.

As in 5 is the UMTS air interface 417 logically divided into three protocol layers (in 5 symbolized by a protocol layer arrangement 500 ). The units (entities) which ensure and realize the functionality of the respective protocol layers described below are both in the mobile radio communication terminal 418 as well as in the UMTS base station 408 . 409 . 410 . 411 or in the respective mobile network control unit 406 . 407 , implemented.

In 5 is the protocol structure 500 from the point of view of the dedicated transport channel DCH (Dedicated Channel).

In the 5 The lowest layer shown is the physical layer PHY 501 which according to the OSI reference model (Open System Interconnection) according to ISO (International Standardization Organization) the protocol layer 1 represents.

The above the physical layer 501 arranged protocol layer is the backup layer 502 , according to OSI reference model protocol layer 2 , which in turn has several sub-protocol layers, namely the medium access control protocol layer (MAC protocol layer) 503 , the radio link control protocol layer 504 (RLC protocol layer), the Packet Data Convergence Protocol protocol layer 505 (PDCP protocol layer), as well as the broadcast / multicast control protocol layer 506 (BMC protocol layer).

The top layer of the UMTS air interface Uu is the cellular network layer (according to the OSI reference protocol layer protocol 3 ), comprising the mobile radio resource control unit 507 (Radio Resource Control protocol layer, RRC protocol layer).

Each protocol layer 501 . 502 . 503 . 504 . 505 . 506 . 507 The protocol layer above it offers its services via predefined, defined service access points.

The service access points are provided with common and unique names, such as logical channels, for better understanding of the protocol layer architecture 508 between the MAC protocol layer 503 and the RLC protocol layer 504 , Transport channels 509 between the physical layer 501 and the MAC protocol layer 503 , Radio Bearer (RB) 510 between the RLC protocol layer 504 and the PDCP protocol layer 505 or the BMC protocol layer 506 , as well as Signaling Radio Bearer (SRB) 513 between the RLC protocol layer 504 and the RRC protocol layer 507 ,

In the 5 illustrated protocol structure 500 According to UMTS, it is not only divided horizontally into the protocol layers and units of the respective protocol layers described above, but also vertically into a so-called control protocol level 511 (Control-Plane, C-Plane), which parts of the physical layer 501 , Parts of the MAC protocol layer 503 , Parts of the RLC protocol layer 504 as well as the RRC protocol layer 507 contains and the user log level 512 (User-Plane, U-Plane), which parts of the physical layer 501 , Parts of the MAC protocol layer 503 , Parts of the RLC protocol layer 504 , the PDCP protocol layer 505 and the BMC protocol layer 506 contains.

By means of the units of the control protocol level 511 Only control data required to set up, break down and maintain a communication link is transmitted, whereas the user-level units 512 the actual user data are transported.

Each protocol layer or unit (entity) of a respective protocol layer has certain predefined functions in the context of mobile radio communication.

On the transmitter side, the task is the physical layer 501 or units of the physical layer 501 that secure transmission of from the MAC protocol layer 503 coming data over the air interface 417 to ensure. The data in this context is based on physical channels (not shown in FIG 5 ). The physical layer 501 offers its services the MAC protocol layer 503 via transport channels 509 which determines how and with what characteristic the data over the air interface 417 to be transported. The essential functions of the units of the physical layer 501 include channel coding, modulation and CDMA code spreading. The physical layer performs in the same way 501 or the entities of the physical layer 501 on the receiver side, the CDMA code despreading, the demodulation and the decoding of the received data and then passes them to the MAC protocol layer 503 for further processing.

The MAC protocol layer 503 or the units of the MAC protocol layer 503 provides or provides their services to the RLC protocol layer 504 using logical channels 508 as service access points, which characterize which type of file is the transported data. The task of the MAC protocol layer 503 in the transmitter, ie in data transmission in the uplink direction in the mobile radio communication terminal 418 , in particular, lies in the data being sent to a logical channel 508 above the MAC protocol layer 503 abut on the transport channels 509 the physical layer 501 map. The physical layer 501 offers the transport channels 509 For this purpose, discrete transmission rates. Therefore, an important function of the MAC protocol layer 503 or the entities of the MAC protocol layer 503 in the mobile communication terminal 418 in the transmission case, the selection of a suitable transport format (TF) for each configured transport channel as a function of the respectively current data transmission rate and the respective data priority of the logical channels 508 pointing to the respective transport channel 509 are shown, as well as the available transmission power of the mobile communication terminal 418 (UE). In a transport format, among other things, it defines how many MAC data packet units, referred to as transport block, per transmission time length TTI (Transmission Time Interval) over the transport channel 509 to the physical layer 501 in other words, be transmitted. The permissible transport formats and the permissible combinations of transport formats of the various transport channels 509 become the mobile communication terminal 418 from the mobile network control unit 406 . 407 in the establishment of a communication connection signals in the form of the so-called uplink TFCS (Transport Format Combination Set, amount of allowed transport format combinations). By being receivers are from the units of the MAC protocol layer 503 on the transport channels 509 received transport blocks back to the logical channels 508 divided up.

The MAC protocol layer or the units of the MAC protocol layer 503 usually has three logical units. The so-called MAC-D unit (MAC-D unit) treats the payload data and the control data, which are sent via the dedicated dedicated DICH (DICH) and DED (dedicated control channel) logical channels to the dedicated DCH (Dedicated Channel ). The MAC-c / sh unit (MAC control / shared unit) handles the payload data and the control data of logical channels 508 on the common transport channels 509 , such as the common transport channel RACH (Random Access Channel) in the uplink direction or the common transport channel FACH (Forward Access Channel) are mapped in the downlink direction. The MAC-b unit (MAC broadcast unit) treats only the mobile radio cell-relevant system information, which is mapped via the BCCH (Broadcast Control Channel) to the transport channel BCH (Broadcast Channel) and broadcast to all mobile radio communication terminals 418 be transmitted in the respective mobile radio cell.

• • Transparent Mode (TM),
• • Unacknowledged Mode (UM), oder
• • Acknowledged Mode (AM).

Using the RLC protocol layer 504 or by means of the units of the RLC protocol layer 504 become the RRC protocol layer 507 their services by means of Signaling Radio Bearer (SRB) 513 as service access points and the PDCP protocol layer 505 and the BMC protocol layer 506 by means of radio bearer (RB) 510 offered as service access points. The Signaling Radio Bearer and the Radio Bearer characterize how the RLC protocol layer 504 to deal with the data packets. This is done, for example, by the RRC protocol layer 507 The transmission mode is defined for each configured Signaling Radio Bearer or Radio Bearer. According to UMTS, the following transmission modes are provided:

• Transparent Mode (TM),
• • Unacknowledged Mode (UM), or
• • Acknowledged Mode (AM).

The RLC protocol layer 504 is modeled so that there is one stand-alone RLC entity per radio bearer or signaling radio bearer. Furthermore, the task of the RLC protocol layer or its entities 504 in the transmitting device, the user data and the signaling data of radio bearers or Signaling Radio Bearern split into data packets or put together. The RLC protocol layer 504 transfers the data packets resulting after the division or merging to the MAC protocol layer 503 for further transport or further processing.

The PDCP protocol layer 505 or the units of the PDCP protocol layer 505 is or are set up for the transmission or for the reception of data of the so-called packet-switched domain (packet-switching domain, PS domain). The main function of the PDCP protocol layer 505 is the compression or decompression of the IP header information (Internet Protocol header information).

The BMC protocol layer 506 or their entities is or are used to transmit or receive via the air interface so-called cell broadcast messages.

The RRC protocol layer 507 or the entities of the RRC protocol layer 507 is or are for the construction and the dismantling and reconfiguration of physical channels, transport channels 509 , logical channels 508 , Signaling Radio Bearers 513 and Radio Bearers 510 as well as for negotiating all parameters of the protocol layer 1 ie the physical layer 501 and the protocol layer 2 , responsible. This is done by exchanging the RRC units, ie the units of the RRC protocol layer 507 in the mobile network control unit 406 . 407 and the respective mobile communication terminal 418 via the Signaling Radio Bearers 513 corresponding RRC messages.

6 shows a modem baseband processor arrangement 600 the mobile communication terminal 418 in detail.

• • einen Kanal-Encoder 605, beispielsweise einen Viterbi-Kanalencoder 605;
• • einen Kanal-Decoder 606, beispielsweise einen Viterbi-Kanaldecoder 606;
• • eine erste Kanal-Messeinrichtung 607, beispielsweise einen Delay Profile Estimator 607;
• • und eine Empfänger-Einheit 608, beispielsweise eine Rake Receiver-Einheit 608.

The modem baseband processor arrangement 600 has a central microcontroller 601 , For example, a digital signal processor (DSP), which, by means of a first microcontroller interface 602 (set up as master interface) with a local memory 603 of the microcontroller 601 is coupled. Furthermore, the processor arrangement 600 a single-master peripheral bus 604 and a plurality of peripheral units, according to this embodiment of the invention the following four peripheral units:

• • a channel encoder 605 , for example a Viterbi channel encoder 605 ;
• • a channel decoder 606 , for example a Viterbi channel decoder 606 ;
• • a first channel measuring device 607 for example, a Delay Profile Estimator 607 ;
• • and a receiver unit 608 For example, a rake receiver unit 608 ,

The peripheral units 605 . 606 . 607 . 608 can be extended arbitrarily and provide according to this embodiment of the invention functionalities of the physical layer 501 the mobile communication terminal 418 ready. The peripheral units 605 . 606 . 607 . 608 are by means of the single-master peripheral bus 604 and by means of a second microcontroller interface 609 (set up as master interface) with the central microcontroller 601 coupled.

Furthermore, a multi-master arbiter 610 provided and a configuration memory 611 , alternatively or additionally a communication data memory (in 6 not shown). The central microcontroller 601 is by means of the second microcontroller interface 609 and by means of the single-master peripheral bus 604 with the multi-master arbiter 610 and by means of an arbiter interface 612 (set up as master interface) with the configuration data memory 611 coupled. The peripheral units 605 . 606 . 607 . 608 are not using the single-master peripheral bus 604 with the multi-master arbiter 610 coupled, but only with the central microcontroller 601 , so while having a data exchange with the central microcontroller 601 by means of the single-master peripheral bus 604 is possible, but not access to the configuration data store 611 using the multi-master arbiter 610 using the single-master peripheral bus 604 ,

According to this embodiment of the invention, in the modem baseband processor arrangement 600 a configuration data bus 613 intended.

The configuration data bus 613 (in 6 symbolized by means of individual separate electrically conductive lines between the multi-master arbiter 610 and the respective peripheral units 605 . 606 . 607 . 608 ) connects the multi-master arbiter 610 and thus the configuration data memory 611 with the respective peripheral units 605 . 606 . 607 . 608 by means of respective peripheral unit interfaces 614 . 615 . 616 . 617 , which are each set up as master interfaces.

The central microcontroller 601 has no access to the configuration data bus 613 and is not coupled with this.

Each peripheral unit 605 . 606 . 607 . 608 Each has its own microprocessor or a comparable local control unit, which can read the configuration data and control the functions of the peripheral unit according to the configuration, wherein the peripheral units 605 . 606 . 607 . 608 each in their architecture in terms of their assigned physical layer function 501 are specifically designed.

The peripheral units 605 . 606 . 607 . 608 are operated according to the central microcontroller 601 or configuration data specified by another unit.

The configuration data according to this embodiment of the invention is provided by the central microcontroller 601 generated and by means of the single-master peripheral bus 604 into the configuration data store 611 saved.

In accordance with this embodiment of the invention, the configuration data at the beginning of the method are provided by the central microcontroller 601 generated in tabular form and either in its local memory 603 stored from which they are read before the respective peripheral unit 605 . 606 . 607 . 608 should be configured according to the respective table entry. In this case, the configuration data will be from local storage 603 into the configuration data store 611 or the configuration data is copied from the central microcontroller 601 generated in tabular form and directly into the configuration data memory 611 written.

The configuration data are for example for the channel encoder 605 the permissible transport format combinations or even a selected transport format, which is the physical layer 501 should be used for reading data packets from the buffer memory of the medium access control unit and for transmitting the read data packets via the radio interface.

Corresponding to the channel decoder 606 in the configuration data contain the information about the transport format, which is to be used in each case for channel decoding. The transport format is called configuration data from the configuration data store 611 read. The respective transport format for the channel decoder 606 is provided by the mobile radio network control unit 406 . 407 given and to the mobile communication terminal 418 transmitted and there by means of a unit of the mobile radio resource control unit (RRC) and by means of the central microcontroller 601 as configuration data in the configuration data memory 611 saved.

The Delay Profile Estimator 607 receives as configuration data, for example, different measurement rules, in which specified how he has to perform the measurement of different mobile radio channels. Parameters of the configuration data for the Delay Profile Estimator 607 For example, the indication of the channel to be measured, the measurement accuracy, further channel information, information about the mobile radio cell, an indication of the measurement quality (for example, whether the measurement should be fast or accurate), an indication of the measurement interval to be used, etc.

The measured data is taken from the Delay Profile Estimator 607 either directly by means of the single-master peripheral bus 604 alternatively by means of the configuration data bus 613 via the configuration data memory 611 to the central microcontroller 601 transferred, alternatively to an RRC unit. The measurement data are from the central microcontroller 601 evaluated and according to the central measurement data configuration data for the Rake Receiver 608 which generates the rake receiver 608 also by means of the configuration data memory 611 to provide.

The individual peripheral units 605 . 606 . 607 . 608 Now meet in operation their respective function assigned to them according to those of them by means of the configuration data bus 613 from the configuration data store 610 read out configuration data.

Clearly, therefore, has every peripheral unit 605 . 606 . 607 . 608 an additional master interface 614 . 615 . 616 . 617 which is coupled to the configuration data memory 611 , more specifically with the multi-master arbiter 610 ,

The central microcontroller 601 can by means of appropriate data transfer via the single-master peripheral bus 604 to the peripheral units 605 . 606 . 607 . 608 turn them on or off (enable or disable) and initialize (initial configure); such as the central microcontroller 601 the respective peripheral unit 605 . 606 . 607 . 608 by means of the peripheral bus 604 tell at what locations (locations) in the configuration data store 611 the respective peripheral unit 605 . 606 . 607 . 608 can find their respective reconfiguration configuration data.

The multi-master arbiter 610 controls the access of the peripheral units 605 . 606 . 607 . 608 by means of the configuration data bus 613 and the central microcontroller 601 by means of the peripheral bus 604 to the configuration data store 611 by, for example, providing each unit with a maximum latency per access or a minimum bandwidth.

The multi-master arbiter 610 is preconfigured taking into account a worst-case analysis in the timing of the respective peripheral units 605 . 606 . 607 . 608 that the corresponding real-time requirements are guaranteed. For this purpose, a known system analysis is usually carried out, for example by means of appropriate system simulation.

In accordance with these embodiments of the invention, at least a portion of the peripheral units are reconfigured 605 . 606 . 607 . 608 after each elapsed time slot, according to UMTS every 667 microseconds.

7 shows a first time chart 700 and a second time chart 710 in which the configuration process is represented symbolically, wherein in the first time diagram 700n Configuration data generation processes 701 . 702 . 703 (Each one configuration data generation process for each peripheral unit 605 . 606 . 607 . 608 to a respective logic or timer event 704 . 705 . 706 ) are shown.

The configuration data generation processes according to this embodiment of the invention include writing the configuration data into the configuration data memory 611 ,

In the second time diagram 710 are the self-configuration processes 711 . 712 . 713 the respective peripheral units 605 . 606 . 607 . 608 , taking place at respective process times 714 . 715 . 716 , wherein it is ensured that when the respective processes overlap in time with respect to the access of the peripheral units 605 . 606 . 607 . 608 to the configuration data store 611 the respective accesses according to their real-time requirements to the configuration data memory 611 what is guaranteed by the multi-master arbiter 610 ,

It should be noted that the configuration data generation process and the self-configuration process are independent and time-decoupled from each other.

8th shows a modem baseband processor arrangement 800 the mobile communication terminal 418 according to a second embodiment of the invention.

Same or identical elements of the modem baseband processor arrangement 800 compared to the modem baseband processor arrangement 600 are provided with identical reference numerals and will not be explained again below.

According to the second embodiment of the invention is additionally a communication data memory 801 which is also provided by means of a second multi-master arbiter interface 802 with the multi-master arbiter 610 and above that with the central microcontroller 601 (by means of the single-master peripheral bus 604 ) and with the peripheral units 605 . 606 . 607 . 608 (using the configuration data bus 613 ) is coupled. Further, a physical layer unit 803 provided and by means of the communication data bus 806 with the multi-master arbiter 610 coupled, which is adapted to provide the functionality of a mobile data transmission according to a second generation mobile communication standard, for example according to GSM. Alternatively, units of other mobile communication standards, or units of the physical layer of the respective mobile communication standards of the third or a subsequent generation may be provided, for example according to CDMA, according to FOMA, according to 3GPP2, etc.

The configuration data store 611 or the communication data memory 801 are designed as Static Random Access Memory (SRAM).

Further, with the single-master peripheral bus 604 a crypto unit 804 for encrypting and / or end-keying, generally for providing a cryptographic function or a cryptographic service. Furthermore, units of the mobile radio communication terminal 418 with the single-master peripheral bus 604 be coupled, for example, units with processors, which functionalities of the higher-quality communication protocol layers, such as the layers 2 and or 3 , be provided in 8th For example, a mobile radio resource control unit (RRC) is shown. 805 connected to the communication data bus 806 is coupled.

According to this embodiment of the invention, the peripheral units 605 . 606 . 607 . 608 if necessary with the units additionally provided in each case 803 . 804 . 805 Exchange communication data using the communication data memory 801 , again by means of the configuration data bus 613 from the peripheral units 605 . 606 . 607 . 608 to the communication data memory 801 and by means of the communication data bus 806 for data transmission between the communication data memory 801 and the additional units 803 . 804 . 805 ,

It should be noted in this regard that the communication by means of the respective buses 604 . 613 can be bidirectional.

9 shows in a message flow diagram 900 an example of a message flow according to an embodiment of the invention.

In a first time slot 901 be from the central microcontroller 601 in a first step (step 902 ) the settings of the tasks of the Delay Profile Estimator 607 specified and a system timer 903 is (re) -programmed by means of a (re) -programming message 904 , Furthermore, the central microcontroller transmits 601 in a DPE configuration message 905 the settings for the Delay Profile Estimator 607 to the configuration data store 611 ,

The system timer 903 generates a periodic time slot trigger 906 which of the system timer 903 is generated at the beginning of each new timeslot and transmits the timeslot trigger 906 to the rake receiver unit 608 which depends on the reception of the timeslot trigger 906 checked their configuration (step 907 ).

Below is the rake receiver unit 608 the RAKE process (step 908 ) according to the rake receiver unit 608 assigned configuration.

Furthermore, the system generates timers 903 a DPE task trigger event 909 and submit it to the Delay Profile Estimator 607 which indicates the reception of the DPE task trigger event 909 his task is initialized (step 910 ), from the configuration data store 611 read out the configuration data provided for this purpose (step 911 ) and performs the task (step 912 ).

At the beginning of a second time slot 913 the system generates timers 903 again a periodic time slot trigger 914 and transmits the timeslot trigger 914 to the rake receiver unit 608 which depends on the reception of the timeslot trigger 914 Check your configuration again (step 915 ). Below is the rake receiver unit 608 the RAKE process (step 916 ) according to the rake receiver unit 608 assigned configuration.

At the beginning of a third time slot 917 the system generates timers 903 again a periodic time slot trigger 918 and transmits the timeslot trigger 918 to the rake receiver unit 608 which depends on the reception of the timeslot trigger 918 Check your configuration again (step 919 ). Below is the rake receiver unit 608 the RAKE process (step 920 ) according to the rake receiver unit 608 assigned configuration.

After the Delay Profile Estimator 607 he has fulfilled his assigned task, he transmits the central microcontroller 601 its results in a DPE result message 921 ,

Upon receipt of the DPE result message 921 and taking into account the received results of the Delay Profile Estimator 607 updates the central microcontroller 601 the configuration data for the Rake Receiver unit 608 (Step 922 ) and stores the updated configuration data for the Rake Receiver unit 608 in the configuration data store 611 by means of an update configuration data storage message 923 , Furthermore, the central microcontroller transmits 601 an update information message 924 to the rake receiver unit 608 with which the central microcontroller 601 the rake receiver unit 608 informed about a performed update and storage of the configuration data.

At the beginning of a fourth time slot 925 the system generates timers 903 again a periodic time slot trigger 926 and transmits the timeslot trigger 926 to the rake receiver unit 608 which depends on the reception of the timeslot trigger 926 Check your configuration again (step 927 ) and the previously received update information message 924 now the updated configuration data from the configuration data memory 611 reads out (step 928 ). Below is the rake receiver unit 608 the RAKE process according to the read new configuration data (step 929 ).

At the beginning of a fifth time slot, the system generates timers 903 again a regular time slot trigger 930 and transmits the timeslot trigger 930 to the rake receiver unit 608 which depends on the reception of the timeslot trigger 930 Check your configuration again (step 931 ) and continues the process in the manner described above.

In summary, the following aspects of the invention should be pointed out:
According to one embodiment of the invention, the central microcontroller generates re-configuration data in advance (ie, as soon as possible) when, for example, all input data is available and writes it into the central configuration memory as described above. The central microcontroller as well as the peripheral units have simultaneous access to this central configuration data memory. Each peripheral unit reads its configuration data from the configuration data memory at its respectively specified (scheduled) re-configuration time.

An access arbiter for the configuration data store and / or for the communication data store controls the access bandwidth for each entity accessing the communication data store or configuration data store and thus ensures that the specific data throughput and the latency requirements are ensured.

• • Die beiden Aufgaben des Erzeugens von Konfigurationsdaten bzw. Kommunikationsdaten und des Schreibens der Kommunikationsdaten bzw. Konfigurationsdaten zu den Peripherie-Einheiten werden voneinander entkoppelt;
• • der zentrale Mikrocontroller wird hinsichtlich der zeitkritischen Konfiguration des Schreibens entlastet;
• • es werden Rechenbelastungs-Spitzen für den zentralen Mikrocontroller oder gegebenenfalls einen DMA-Controller vermieden, wenn eine große Anzahl von zeitkritischen Konfigurations-Schreib-Aufgaben einander zeitlich überlappen.

Advantages of the above-described embodiments of the invention are, for example:

• • The two tasks of generating configuration data or communication data and writing the communication data or configuration data to the peripheral units are decoupled from each other;
• The central microcontroller is relieved of the time-critical configuration of the writing;
• • Computational load peaks for the central microcontroller or possibly a DMA controller are avoided when a large number of time-critical configuration write tasks overlap in time.

LIST OF REFERENCE NUMBERS

100

Modem baseband processor arrangement

101

Central microcontroller

102

First microcontroller interface

103

Local memory

104

Second microcontroller interface

105

peripheral

106

Peripheral unit

107

Peripheral unit

108

Peripheral unit

200

Modem baseband processor arrangement

201

DMA controller

202

First DMA controller interface

203

Second DMA controller interface

300

First time diagram

301

First timer event

302

Configuration data generation process

303

Configuration data writing process

310

Second time diagram

311

Second timer event

312

Configuration data generation process

313

Third timer event

314

Configuration data writing process

400

UMTS mobile radio communication system

401

Mobile network subsystem

402

Mobile network subsystem

403

Iu interface

404

Iu interface

405

UMTS core network

406

Mobile network control unit

407

Mobile network control unit

408

UMTS base station

409

UMTS base station

410

UMTS base station

411

UMTS base station

412

Lur interface

413

Lub interface

414

Lub interface

415

Lub interface

416

Lub interface

417

Uu air interface

418

UE

500

protocol structure

501

Physical layer

502

Data link layer

503

MAC protocol layer

504

RLC protocol layer

505

PDCP protocol layer

506

BMC protocol layer

507

RRC protocol layer

508

Logical channel

509

transport channel

510

Radio Bearer

511

Control protocol level

512

User protocol level

513

Signaling Radio Bearer

600

Modem baseband processor arrangement

601

Central microcontroller

602

First microcontroller interface

603

Local memory

604

Single master peripheral bus

605

Peripheral unit

606

Peripheral unit

607

Peripheral unit

608

Peripheral unit

609

Second microcontroller interface

610

Multi-master arbiter

611

Configuration data memory

612

Arbiter interface

613

configuration data

614

Peripheral master interface

615

Peripheral master interface

616

Peripheral master interface

617

Peripheral master interface

700

First time diagram

701

Configuration data generation process

702

Configuration data generation process

703

Configuration data generation process

704

First timer event

705

Second timer event

706

Third timer event

710

Second time diagram

711

First self-configuration process

712

Second self-configuration process

713

Third self-configuration process

714

Fourth timer event

715

Fifth timer event

716

Sixth timer event

800

Modem baseband processor arrangement

801

Communication data storage

802

Second arbiter interface

803

2G unit

804

Crypto unit

805

RRC unit

806

communications data

900

Message flow diagram

901

First time slot

902

step

903

System timer

904

Re-programming message

905

DPE configuration message

906

Time slot trigger

907

step

908

step

909

DPE task trigger event

910

step

911

step

912

step

913

Second time slot

914

Time slot trigger

915

step

916

step

917

Third time slot

918

Time slot trigger

919

step

920

step

921

DPE result message

922

step

923

Update configuration data store message

924

Update information message

925

Fourth time slot

926

Time slot trigger

927

step

928

step

929

step

930

Time slot trigger

931

step

Claims (25)

Processor arrangement • with a first processor, • with several second processors, With a first coupling unit for coupling the first processor to the plurality of second processors, With a coupling memory coupled to the first processor for storing configuration data and / or communication data, and With a second coupling unit for coupling the coupling memory with the second processors With an access control unit coupled to the coupling memory and the second coupling unit, which is arranged between the first coupling unit and the coupling memory and at the same time is arranged between the second coupling unit and the coupling memory and which is set up for allocating access rights for accessing the coupling memory that corresponding real-time requirements are ensured Wherein the first processor or at least one of the second processors store configuration data for at least one further of the second processors in the coupling memory, and Wherein the second processors write the configuration data into the coupling memory by means of the second coupling unit or read from the coupling memory, Wherein the first coupling unit is a first bus or a plurality of separate first electrically conductive connections, Wherein the second coupling unit is a second bus or a plurality of separate second electrically conductive connections, and Wherein the first processor is not coupled to the second coupling unit, Wherein the first processor does not have access to the second coupling unit, Wherein each of the second processors is arranged to read its configuration data from the coupling memory at a given for the respective second processor Re-configuration time. The processor arrangement of claim 1, wherein the first processor is configured as a master processor. Processor arrangement according to claim 1 or 2, wherein the second processors are arranged as slave processors. Processor arrangement according to claim 3, wherein at least two of the second processors are formed differently. Processor arrangement according to claim 3 or 4, wherein at least one of the second processors is a processor specialized in at least one predetermined function in its design. Processor arrangement according to one of claims 1 to 5, wherein at least one of the second processors is a peripheral component processor, which is controlled by the first processor. Processor arrangement according to one of claims 1 to 6, wherein at least one of the second processors is a peripheral component processor, which is adapted to provide at least one function of a physical communication protocol layer of a radio communication device. The processor arrangement of claim 7, wherein at least one of the second processors is a peripheral component processor configured to provide at least one function of a physical communication protocol layer of a mobile communication device. The processor arrangement of claim 8, wherein at least one of the second processors is a peripheral component processor configured to provide at least one function of a physical communication protocol layer of a third generation mobile communication device. A processor arrangement according to claim 8 or 9, wherein the second processors are arranged to each perform at least one of the following functions: channel coding of data, channel decoding of data, measurement of channel characteristics, reception of radio signals, transmission of radio signals , • Search for radio sync channels. The processor arrangement according to one of claims 1 to 10, wherein the first coupling unit is a master peripheral bus. The processor arrangement according to one of claims 1 to 11, wherein the first processor is coupled to the first coupling memory by means of the first coupling unit. Processor arrangement according to one of claims 1 to 12, wherein the coupling memory is a volatile memory or a non-volatile memory. The processor arrangement according to one of claims 1 to 13, wherein the coupling memory is a multiple access memory. The processor arrangement of claim 14, wherein the coupling memory is a static random access memory. The processor arrangement of claim 1, wherein the access control unit is a bus arbiter. Processor arrangement according to one of claims 1 to 16, with at least one third processor which is coupled to the coupling memory for exchanging communication data with at least one second processor of the plurality of second processors. The processor arrangement of claim 17, wherein at least one of the third processors is a processor of a functionally higher communication protocol layer than the physical communication protocol layer. The processor arrangement of claim 18, wherein at least one of the third processors is a medium access control processor. The processor arrangement of claim 18 or 19, wherein at least one of the third processors is a radio link control processor. The processor arrangement of claim 18, wherein at least one of the third processors is a radio resource control processor. The processor arrangement of claim 18, wherein at least one of the third processors is a crypto processor configured to encrypt or decrypt data. The processor arrangement of claim 18, wherein at least one of the third processors is a peripheral component processor configured to provide at least one function of a physical communication protocol layer of a second generation mobile communication device. Method for exchanging configuration data and / or Communication data between a first processor and a plurality of second processors, wherein data is exchanged between the first processor and the plurality of second processors by means of a first coupling unit for coupling the first processor to the plurality of second processors, wherein configuration data for at least one other of the second processors of the first processor or at least one of the second processors are stored in a coupling memory, wherein the second processors write the configuration data by means of a second coupling unit in the coupling memory or read from the coupling memory, the first processor is not coupled to the second coupling unit and wherein one with access control unit coupled to the coupling memory and the second coupling unit assigns access rights for access to the coupling memory, so that corresponding real-time requirements are ensured, wherein the accesses is arranged between the first, coupling unit and the coupling memory and at the same time is arranged between the second coupling unit and the coupling memory, wherein the first coupling unit is a first bus or a plurality of separate first electrically conductive connections, and wherein the second coupling unit is a second bus or a plurality of separate second electrically conductive connections, wherein the first processor does not have access to the second coupling unit, wherein each of the second processors reads its configuration data from the coupling memory at a re-configuration time predetermined for the respective second processor. A computer program element for exchanging configuration data and / or communication data between a first processor and a plurality of second processors which, when executed by one or more processors, comprises the steps of the method of claim 24.

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