[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

DE102005019574A1 - Contact arrangement for semiconductor component e.g. integrated circuit (IC) has reinforcement layer formed on contact surface and protrudes above insulating layer - Google Patents

Contact arrangement for semiconductor component e.g. integrated circuit (IC) has reinforcement layer formed on contact surface and protrudes above insulating layer Download PDF

Info

Publication number
DE102005019574A1
DE102005019574A1 DE200510019574 DE102005019574A DE102005019574A1 DE 102005019574 A1 DE102005019574 A1 DE 102005019574A1 DE 200510019574 DE200510019574 DE 200510019574 DE 102005019574 A DE102005019574 A DE 102005019574A DE 102005019574 A1 DE102005019574 A1 DE 102005019574A1
Authority
DE
Germany
Prior art keywords
layer
contacting
arrangement according
insulating layer
contacting arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE200510019574
Other languages
German (de)
Other versions
DE102005019574B4 (en
Inventor
Reinhold Dr. Bayerer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE200510019574 priority Critical patent/DE102005019574B4/en
Publication of DE102005019574A1 publication Critical patent/DE102005019574A1/en
Application granted granted Critical
Publication of DE102005019574B4 publication Critical patent/DE102005019574B4/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48455—Details of wedge bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48744—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48755—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An insulating layer (1) is formed such that a contact surface (3) on a semiconductor chip (7) is enclosed. A reinforcement layer (9) formed on the contact surface has a thickness such that the reinforcement layer protrudes above the insulating layer. A contact wire (4) is connected to the reinforcement layer. An independent claim is also included for a contact arrangement manufacturing method.

Description

Die vorliegende Erfindung betrifft eine Kontaktierungsanordnung für ein Halbleiterbauelement mit einem Halbleiterchip, bei der ein Kontaktierungsdraht elektrisch mit einer auf einem Halbleiterkörper vorgesehenen Kontaktierungsfläche verbunden ist, die im Wesentlichen von einer Isolierschicht umgeben ist, so dass die Oberfläche der Isolierschicht in Bezug auf den Halbleiterkörper höher liegt als die Kontaktierungsfläche.The The present invention relates to a contacting arrangement for a semiconductor device having a semiconductor chip in which a bonding wire is electrically with one provided on a semiconductor body contacting surface is connected, which is surrounded by an insulating layer substantially is, so the surface the insulating layer is higher than the contacting surface with respect to the semiconductor body.

Zur elektrischen Kontaktierung von Halbleiterbauelementen, wie beispielsweise auch integrierten Schaltkreisen, haben diese Kontaktierungsflächen, die auch als Bondinseln bezeichnet werden. Diese Kontaktierungsflächen, die gewöhnlich auf der Oberfläche des Halbleiterkörpers des Halbleiterbauelements vorgesehen sind, sind metallisiert und mit einem Kontaktierungsdraht aus beispielsweise Gold oder Aluminium verbunden. Dieses Verbinden erfolgt gewöhnlich durch Bonden.for electrical contacting of semiconductor devices, such as also integrated circuits, have these bonding pads, the also referred to as bond islands. These contacting surfaces, the usually on the surface of the semiconductor body of the semiconductor device are metallized and with a bonding wire of, for example, gold or aluminum connected. This bonding is usually done by bonding.

Die Metallisierung der Kontaktierungsfläche besteht beispielsweise aus einer Aluminiumschicht mit einer Schichtdicke von wenigen Mikrometern.The Metallization of the contact surface is, for example from an aluminum layer with a layer thickness of a few micrometers.

Die Kontaktierungsflächen sind in der Regel von Passivierungsschichten umgeben, welche nicht zu kontaktierende Bereiche des Halbleiterbauelements vor Umwelteinflüssen schützen. Solche Passivierungsschichten werden auf den Halbleiterkörper nach dessen Metallisierung aufgebracht, so dass deren Oberfläche gegenüber der Oberfläche der Kontaktierungsfläche bzw. Bondinsel erhöht ist. Mit anderen Worten, ein zu einer solchen Kontaktierungsfläche geführter Kontaktierungsdraht muss in die durch eine Passivierungsschicht gebildete Öffnung auf die zur Oberseite dieser Öffnung tiefer liegende Kontaktie rungsfläche geführt werden, ohne dabei die Passivierungsschicht zu beschädigen. Mit anderen Worten, der Kontaktierungsdraht muss sicher und zuverlässig innerhalb der zur Kontaktierungsfläche führenden Öffnung in der Isolierschicht platziert werden.The contacting surfaces are usually surrounded by passivation layers, which are not too protect contacting areas of the semiconductor device from environmental influences. Such Passivation layers revert to the semiconductor body whose metallization is applied so that its surface is opposite to the surface the contacting surface or bond pad increased is. In other words, a contacting wire guided to such a contacting surface must be in the opening formed by a passivation layer which to the top of this opening deeper contact surface guided without damaging the passivation layer. With In other words, the bonding wire must be secure and reliable within the to the contact surface leading opening in the insulating layer are placed.

Durch die Verformung der Kontaktierungsdrähte beim Bonden auf der Kontaktierungsfläche treten auch oft Überstände von Drahtmetall auf, welches sich flach von der Kontaktierungsfläche aus nach außen in Richtung auf die Kante der zur Kontaktierungsfläche führenden Öffnung in der Passivierungsschicht erstreckt.By the deformation of the bonding wires during bonding on the contacting surface occur also often supernatants of Wire metal, which is flat from the contact surface after Outside in the direction of the edge of the leading to the contact surface opening in the passivation layer extends.

Die oben geschilderte Situation ist in den 1A und 1B veranschaulicht: 1A zeigt die Oberfläche einer eine Passivierungsschicht bildenden Isolierschicht 1 aus beispielsweise Siliziumdioxid, in welcher sich eine Öffnung 2 befindet, die zu einer Kontaktierungsfläche 3 auf einem Halbleiterkörper 7 (in 1A nicht näher dargestellt) führt. Die Kontaktierungsfläche 3 besteht aus einer dünnen Metallschicht aus beispielsweise Aluminium und bildet eine Bondinsel, welche innerhalb der Öffnung 2 durch die Isolierschicht 1 umgeben ist.The situation described above is in the 1A and 1B illustrates: 1A shows the surface of an insulating layer forming a passivation layer 1 from, for example, silicon dioxide, in which there is an opening 2 located, leading to a contact surface 3 on a semiconductor body 7 (in 1A not shown) leads. The contact surface 3 consists of a thin metal layer of, for example, aluminum and forms a bonding pad, which within the opening 2 through the insulating layer 1 is surrounded.

Soll auf diese Kontaktierungsfläche 3 ein Kontaktierungsdraht 4 gebondet werden, dann besteht die Gefahr, dass infolge der Verformung des Kontaktierungsdrahtes 4 im Bereich der Kontaktierungsfläche 2 ein Überstand 5 entsteht, der eine Kante 6 der Isolierschicht 1 an der Öffnung 2 berührt und dadurch die Isolierschicht 1 beschädigt. Mit anderen Worten, durch die Verformung des Kontaktierungsdrahtes 4 beim Bonden der Kontaktierungsfläche 3 bildet sich der Überstand 5 von Drahtmetall, welches sich flach von der Kontaktierungsfläche 3 bzw. der Bondstelle des Kontaktierungsdrahtes 4 auf dieser Kontaktierungsfläche 3 nach außen in Richtung auf die Kante 6 der Isolierschicht 1 erstreckt.Should be on this contact surface 3 a bonding wire 4 Bonded, then there is a risk that due to the deformation of the bonding wire 4 in the area of the contact surface 2 a supernatant 5 arises, which is an edge 6 the insulating layer 1 at the opening 2 touched and thereby the insulating layer 1 damaged. In other words, by the deformation of the bonding wire 4 when bonding the contacting surface 3 the supernatant forms 5 of wire metal, which is flat from the contacting surface 3 or the bonding point of the bonding wire 4 on this contact surface 3 outward towards the edge 6 the insulating layer 1 extends.

Um nun zuverlässig eine Beschädigung der Isolierschicht 1 durch einen derartigen Überstand 5 des Kontaktierungsdrahtes 9 zu vermeiden, muss die für den Kontaktierungsdraht 4 frei liegende Kontaktierungsfläche 3 größer gewählt werden als die eigentliche Verbindungsfläche zwischen dem Kontaktierungsdraht 9 und der Kontaktierungsfläche 2.Reliable damage to the insulating layer 1 by such a supernatant 5 of the contacting wire 9 To avoid that, it must be for the bonding wire 4 exposed contact surface 3 be chosen larger than the actual connection area between the Kontaktierungsdraht 9 and the contacting surface 2 ,

Diese Situation ist nochmals in 1B veranschaulicht: die Abmessung D – bei einer kreisrunden Öffnung 2 deren Durchmesser – muss größer gewählt werden als die eigentliche Verbindungsfläche zwischen dem Kontaktierungsdraht 4 und der Kontaktfläche 3 innerhalb der Öffnung 2 der Isolierschicht 1. Mit anderen Worten, ein Halbleiterkörper 7 muss mit einer Kontaktierungsfläche 3 in einer Öffnung 2 einer Isolierschicht 1 ausgestattet werden, deren Fläche größer als die tatsächlich für die Verbindung des Kontaktierungsdrahtes 4 mit der Kontaktierungsfläche 3 benötigte Verbindungsfläche ist. Dies bedeutet aber, dass der Halbleiterchip aus dem Halbleiterkörper 7, der Isolierschicht 1, der Kontaktierungsfläche 3 und dem Kontaktierungsdraht 4 zusätzliche "Chipfläche" benötigt, um ausreichend große Bondinseln zur Verfügung stellen zu können.This situation is in again 1B illustrates: the dimension D - at a circular opening 2 their diameter - must be greater than the actual connection area between the bonding wire 4 and the contact surface 3 inside the opening 2 the insulating layer 1 , In other words, a semiconductor body 7 must have a contact surface 3 in an opening 2 an insulating layer 1 be equipped, whose area is greater than that actually for the connection of the bonding wire 4 with the contact surface 3 required connection area is. However, this means that the semiconductor chip from the semiconductor body 7 , the insulating layer 1 , the contacting surface 3 and the bonding wire 4 additional "chip area" needed to provide sufficiently large bonding islands available.

Bei solchen großen Kontaktierungsflächen 3 mit der Abmessung D wird damit mehr Chipfläche verbraucht, als dies bei dem eigentlichen Durchmesser des Kontaktierungsdrahtes 4 und der Größe der Verbindungsfläche zwischen dem Kontaktierungsdraht 4 und der Kontaktierungsfläche 3, dem so genannten Bondfleck, notwendig wäre.For such large contact surfaces 3 the dimension D consumes more chip area than the actual diameter of the contacting wire 4 and the size of the bonding surface between the bonding wire 4 and the contacting surface 3 , the so-called bond spot, would be necessary.

Wird zur Vermeidung solcher großer Bondinseln eine "Überbondung" zugelassen, wie diese mit dem Überstand 5 in 1A schematisch dargestellt ist, so besteht die Gefahr einer eventuellen Schädigung der Isolierschicht 1 im Bereich der Kante 6 der Öffnung 2 zur Kontaktierungsfläche 3.Is to avoid such large bonding islands, an "overbonding" allowed, as this with the supernatant 5 in 1A is shown schematically, so there is a risk of possible damage supply of the insulating layer 1 in the area of the edge 6 the opening 2 to the contact surface 3 ,

1C zeigt noch einen ähnlichen Sachverhalt bei einer so genannten Kugel- bzw. "Ball"-Bondung: ein Kontaktierungsdraht 9 ist hier mit seinem Ende in einer Öffnung 2 auf eine Bondinsel bzw. Kontaktierungsfläche 3 gepresst, wodurch eine Kugel 8 entsteht, bei der der eigentliche Bondfleck 11, nämlich die Verbindungsfläche zwischen der Kugel 8 und der Kontaktierungsfläche 3, erheblich kleiner ist als die Öffnung 2 bzw. die Kontaktierungsfläche 3. 1C shows a similar situation with a so-called ball or "ball" -Bondung: a Kontaktierungsdraht 9 is here with its end in an opening 2 on a bonding pad or contact surface 3 pressed, creating a bullet 8th arises when the actual bond spot 11 namely, the interface between the ball 8th and the contacting surface 3 , is considerably smaller than the opening 2 or the contacting surface 3 ,

Es ist somit Aufgabe der vorliegenden Erfindung, eine Kontaktierungsanordnung anzugeben, bei der keine zusätzliche Chipfläche benötigt wird, um zuverlässig eine Schädigung insbesondere einer Isolierschicht durch einen Überstand des Kontaktierungsdrahtes zu vermeiden.It is therefore an object of the present invention, a contacting arrangement indicate, with no additional chip area needed is going to be reliable a damage in particular an insulating layer by a projection of the Kontaktierungsdrahtes to avoid.

Diese Aufgabe wird bei einer Kontaktierungsanordnung der eingangs genannten Art erfindungsgemäß dadurch gelöst, dass auf der Kontaktierungsfläche eine Verstärkungsschicht aufgetragen ist, deren Schichtdicke so groß gewählt ist, dass die Oberfläche der Verstärkungsschicht, mit der der Kontaktierungsdraht verbunden ist, in Bezug auf die Oberfläche des Halbleiterkörpers etwa gleich hoch oder höher ist als die Oberfläche der Isolierschicht im Bereich der Umgebung der Verstärkungsschicht.These Task is in a contacting arrangement of the aforementioned Type according to the invention thereby solved, that on the contacting surface a reinforcing layer is applied, whose layer thickness is chosen so large that the surface of the Reinforcing layer with which the contacting wire is connected, with respect to the surface of the Semiconductor body about the same or higher is as the surface the insulating layer in the vicinity of the reinforcing layer.

Bei der erfindungsgemäßen Kontaktierungsanordnung wird so letztlich durch zusätzliche Metallisierung der auf dem Halbleiterkörper vorgesehenen Kontaktierungsfläche die ursprünglich durch diese gebildete Bondinsel so weit erhöht, dass die dann durch die Oberfläche der Verstärkungsschicht gebildete "neue" Bondinsel höher oder etwa so hoch wie die Oberfläche der Isolierschicht liegt. Es ist dann ausreichend, die durch die Verstärkungsschicht gebildete Bondinsel so groß zu bemessen, dass die eigentliche Verbindungsfläche, der so genannte Bondfleck, zwischen dem Kontaktierungsdraht und der Bondinsel sicher auf letzterer platzierbar ist. Zusatzflächen für über stehende Drahtbereiche, also einen Überstand des Kontaktierungsdrahtes, sind nicht mehr notwendig, weil diese Überstände zwangsläufig höher liegen als die Oberfläche der Isolierschicht und diese somit nicht mehr berühren können. Unter "etwa so hoch" soll verstanden werden, das die Oberseite der Verstärkungsschicht auch geringfügig niedriger sein kann als die Oberseite der Isolierschicht.at the contacting arrangement according to the invention so will ultimately be through additional Metallization of provided on the semiconductor body contacting surface the originally increased by this formed bond island so far that then by the surface the reinforcing layer higher or higher formed "new" bond island about as high as the surface the insulating layer is located. It is then sufficient that through the reinforcing layer formed bond island so big measure that the actual interface, the so-called between the bonding wire and the bonding pad sure on the latter is placeable. additional areas for over standing Wire areas, so a supernatant of Kontaktierungsdrahtes are no longer necessary, because these supernatants are necessarily higher as the surface the insulating layer and thus can not touch them. Under "about as high" should be understood The top of the reinforcing layer will also be slightly lower can be considered the top of the insulating layer.

Wesentlich an der vorliegenden Erfindung ist also, dass durch Anbringen der Verstärkungsschicht auf der ursprünglichen Kontaktierungsfläche des Halbleiterkörpers die dann durch diese Verstärkungsschicht gebildete "neue" Bondinsel angehoben wird und somit letztlich höher liegt als die in der Umgebung dieser "neuen" Bondinsel vorhandene Topografie des durch den Halbleiterkörper, die Isolierschicht und Metallisierungen gebildeten Halbleiterchips. Dabei können selbstverständlich auch weitere Erhöhungen außerhalb der Kante der Isolierschicht im Bereich der Kontaktierungsfläche berücksichtigt werden, also Erhöhungen, die nicht durch die Isolierschicht und insbesondere die durch diese gebildete Passivierungsschicht verursacht sind.Essential to the present invention is therefore that by attaching the Reinforcement layer on the original one contacting surface of the semiconductor body then through this reinforcement layer raised formed "new" bond island and thus ultimately higher lies as the existing in the vicinity of this "new" Bondinsel topography of through the semiconductor body, the insulating layer and metallizations formed semiconductor chips. It can Of course also more increases outside taken into account the edge of the insulating layer in the region of the contacting surface become, so elevations, not through the insulating layer and especially through it formed passivation layer are caused.

Die Erfindung ermöglicht so ein Halbleiterbauelement, unter dem auch eine integrierte Schaltung, ein Einzelhalbleiter-Bauelement und ein Leistungshalbleiter-Bauelement zu verstehen ist, das sich durch kleine Abmessungen von Kontaktierungsflächen bzw. Bondinseln auszeichnet. Diese Miniaturisierung der Kontaktierungsflächen bzw. Bondinseln wird durch eine an sich überraschend einfache Maßnahme erreicht: die Bondinseln werden von den auf der Oberfläche des Halbleiterkörpers befindlichen Kontaktierungsflächen nach "oben" verlagert, so dass sie im Wesentlichen bündig mit der Oberfläche der den Halbleiterkörper bedeckenden Isolierschicht, insbesondere Passivierungsschicht, sind, wodurch Überstände des Kontaktierungsdrahtes akzeptiert werden können.The Invention allows such a semiconductor device, including an integrated circuit, a single-semiconductor device and a power semiconductor device is to be understood characterized by small dimensions of bonding pads or bonding islands. This miniaturization of the bonding pads or bonding islands is by a surprise in itself simple measure achieved: the bond islands are from the on the surface of the Semiconductor body located contacting surfaces shifted to "up", so that they are essentially flush with the surface of the the semiconductor body covering insulating layer, in particular passivation layer are, whereby supernatants of the Contact wire can be accepted.

Die Herstellung der erfindungsgemäßen Kontaktierungsanordnung kann in einfacher Weise erfolgen: der Halbleiterkörper wird nach Einbringung der Öffnungen für die Bondinseln zunächst chemisch bekeimt. Sodann wird chemisch beispielsweise eine Nickelschicht durch stromloses Plattieren ("electroless plating") aufgewachsen. Ist die Isolierschicht beispielsweise 3 μm dick, so wird auch eine etwa 3 μm dicke Nickelschicht chemisch aufgewachsen. Anstelle von Nickel kann selbstverständlich auch ein anderes geeignetes Material, wie beispielsweise Aluminium, verwendet werden. In diesem Fall sollte zuvor durch Aufdampfen oder Sputtern eine Haftschicht vorgesehen werden.The Production of the contacting arrangement according to the invention can be done in a simple way: the semiconductor body is after introduction of the openings for the Bond Islands first chemically germinated. Then, chemically, for example, a nickel layer by electroless plating ("electroless grown up ". If the insulating layer, for example, 3 microns thick, so is an approximately 3 μm thick Nickel layer chemically grown. Of course, too, instead of nickel another suitable material, such as aluminum become. In this case should be previously by vapor deposition or sputtering an adhesive layer may be provided.

Wird eine Nickelschicht für die Verstärkungsschicht vorgesehen, so kann diese optional zusätzlich mit einer Veredelungsschicht dünn beschichtet werden. Geeignet ist hierzu beispielsweise eine Goldschicht, die etwa 50 nm dick sein kann.Becomes a nickel layer for the reinforcing layer provided, this can optionally also with a finishing layer thinly coated. Suitable for this purpose, for example, a gold layer, which is about 50 nm can be thick.

Auf die Nickelschicht, die gegebenenfalls mit der Goldschicht veredelt ist, oder auf die Aluminiumschicht wird dann der Kontaktierungsdraht, für den beispielsweise ein Golddraht oder ein Aluminiumdraht eingesetzt werden kann, vorzugsweise durch Ultraschall gebondet.On the nickel layer, which optionally refines with the gold layer is or on the aluminum layer then the bonding wire, for example a gold wire or an aluminum wire can be used, preferably ultrasonically bonded.

Ist die Isolierschicht beispielsweise bei einem Leistungshalbleiter-Bauelement besonders dick und weist sie eine Schichtdicke von etwa 20 μm auf, so kann die Bekeimungsschicht chemisch aufgewachsen und danach mit einer Kupferschicht mit einer Schichtdicke von ebenfalls etwa 20 μm verstärkt werden. Diese Kupferschicht kann dann optional wieder dünn mit einer Nickelschicht oder einer Goldschicht veredelt werden.If the insulating layer is particularly thick, for example in the case of a power semiconductor component, and if it has a layer thickness of approximately 20 .mu.m, then the nucleation layer can chemically rise grow and then reinforced with a copper layer with a layer thickness of also about 20 microns. This copper layer can then optionally be refined thinly with a nickel layer or a gold layer.

Anstelle der angegebenen Materialien können, wie bereits erwähnt wurde, auch andere Materialien eingesetzt werden. Auch sind die angegebenen Schichtdicken lediglich Beispiele, so dass hierfür auch andere Werte, die größer oder kleiner sein können, anzunehmen sind.Instead of the specified materials, As already mentioned was, other materials are used. Also are the given layer thicknesses only examples, so that there are others Values that are greater or can be smaller, are to be accepted.

Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:following The invention will be explained in more detail with reference to the drawings. Show it:

1A in Perspektive eine herkömmliche Kontaktierungsanordnung, bei der ein Bonddraht eine Kante einer Passivierungsschicht mit einem Überstand berührt, 1A in perspective a conventional contacting arrangement in which a bonding wire contacts an edge of a passivation layer with a protrusion,

1B eine Schnittdarstellung durch die Verbindung zwischen einem Bonddraht und einem Halbleiterkörper mit einem Bondfleck innerhalb einer Bondinsel nach herkömmlicher Art, 1B a sectional view through the connection between a bonding wire and a semiconductor body with a bonding pad within a bonding pad according to conventional art,

1C in einer Schnittdarstellung eine "Ball"-Bondverbindung zwischen einem Kontaktierungsdraht und einer Kontaktierungsfläche nach herkömmlicher Art, 1C in a sectional view a "ball" -Bondverbindung between a Kontaktierungsdraht and a bonding pad according to a conventional manner,

2A eine Schnittdarstellung durch ein erstes Ausführungsbeispiel der Erfindung und 2A a sectional view through a first embodiment of the invention and

2B eine Schnittdarstellung durch ein zweites Ausführungsbeispiel der Erfindung. 2 B a sectional view through a second embodiment of the invention.

In den Figuren werden für einander entsprechende Bauteile jeweils die gleichen Bezugszeichen verwendet.In the figures are for each corresponding components used the same reference numerals.

Wie in den 2A und 2B dargestellt ist, wird bei der erfindungsgemäßen Kontaktierungsanordnung noch eine Verstärkungsschicht 9 auf der Kontaktierungsfläche 3 aufgebracht. Diese Verstärkungsschicht 9 weist eine solche Schichtdicke auf, dass ihre Oberseite gleich hoch oder höher ist als die Oberfläche des Halbleiterchips und insbesondere der Isolierschicht 1 aus beispielsweise Siliziumdioxid auf der Oberflä che des Halbleiterkörpers 7 im Bereich der durch die Verstärkungsschicht 9 gebildeten "neuen" Bondinsel. Unter dem Begriff "im Bereich der Bondinsel" ist zu verstehen, dass die Verstärkungsschicht 9 wenigstens eine solche Schichtdicke hat, dass ein Überstand 5 des Kontaktierungsdrahtes 4 keinesfalls die Isolierschicht 1 oder andere Teile des Halbleiterchips berührt. Mit anderen Worten, dieser Bereich sollte die n-fache Abmessung D' der Bondinsel, also der Verbindungsfläche zwischen dem Kontaktierungsdraht 4 und der Verstärkungsschicht 9 haben. Ein unter praktischen Gesichtspunkten geeignete Größe für diesen Faktor n beträgt etwa 1,3 ... 1,5. Selbstverständlich sind aber auch andere Werte für n möglich.As in the 2A and 2 B is shown in the contact arrangement according to the invention is still a reinforcing layer 9 on the contact surface 3 applied. This reinforcement layer 9 has such a layer thickness that its upper surface is equal to or higher than the surface of the semiconductor chip and in particular the insulating layer 1 from, for example, silicon dioxide on the surface of the semiconductor body Oberflä 7 in the area through the reinforcement layer 9 formed "new" bond island. The term "in the area of the bonding pad" is to be understood as meaning that the reinforcing layer 9 at least one such layer thickness has a supernatant 5 of the contacting wire 4 in no case the insulating layer 1 or other parts of the semiconductor chip touched. In other words, this area should be the n-fold dimension D 'of the bonding pad, that is, the bonding surface between the bonding wire 4 and the reinforcing layer 9 to have. A practical size for this factor n is about 1.3 ... 1.5. Of course, other values for n are also possible.

Für die Verstärkungsschicht 9 kann in vorteilhafter Weise beispielsweise Nickel eingesetzt werden. Auch andere Materialien, wie beispielsweise Aluminium sind geeignet. Wird Nickel für die Verstärkungsschicht 3 verwendet, dann kann zusätzlich noch eine Veredelungsschicht 10 aus Gold (in den 2A und 2B strichliert dargestellt) angebracht werden. Diese Veredelungsschicht 10 kann eine Schichtdicke von beispielsweise 50 nm aufweisen. Auch andere Schichtdicken hierfür sind möglich.For the reinforcing layer 9 For example, nickel can be used in an advantageous manner. Other materials such as aluminum are suitable. Will nickel for the reinforcing layer 3 used, then can additionally a finishing layer 10 of gold (in the 2A and 2 B shown in dashed lines) are attached. This finishing layer 10 may have a layer thickness of for example 50 nm. Other layer thicknesses for this are possible.

Ist beispielsweise die Isolierschicht 1, also in der Regel eine Passivierungsschicht beispielsweise aus Siliziumdioxid, mit einer Schichtdicke von 3 μm versehen, so weist die Verstärkungsschicht 9 aus Nickel ebenfalls eine Schichtdicke von etwa 3 μm auf, wobei – wie erwähnt – auf dieser Nickelschicht 9 noch Veredelungsschichten 10 aus beispielsweise Gold mit der erwähnten Schichtdicke von 50 nm angebracht sein können. Es sind auch Schichtdicken von beispielsweise 25 bis 700 nm vorteilhaft. Unter Veredelungsschichten sind eine oder vorzugsweise mehrere Schichten, beispielsweise drei Schichten, zu verstehen. Selbstverständlich können aber für die Schichtdicke auch andere Werte gewählt werden.Is for example the insulating layer 1 , So usually a passivation layer, for example, made of silicon dioxide, provided with a layer thickness of 3 microns, so has the reinforcing layer 9 made of nickel also has a layer thickness of about 3 microns, wherein - as mentioned - on this nickel layer 9 still finishing layers 10 may be made of, for example, gold with the mentioned layer thickness of 50 nm. Layer thicknesses of, for example, from 25 to 700 nm are also advantageous. Under finishing layers are one or preferably more layers, for example, three layers to understand. Of course, however, other values can also be selected for the layer thickness.

Wird für die Isolierschicht 9 anstelle von Nickel beispielsweise Aluminium eingesetzt, das dann ebenfalls eine Schichtdicke von 3 μm hat, dann kann zusätzlich noch eine Haftschicht 12 vorgesehen werden.Will for the insulating layer 9 Instead of nickel, for example, aluminum used, which then also has a layer thickness of 3 microns, then in addition an adhesive layer 12 be provided.

Zur Herstellung der Verstärkungsschicht 9 kann auf der Oberfläche des Halbleiterkörpers 7 zur Bildung der Kontaktierungsfläche 3 auch eine Bekeimungsschicht chemisch aufgewachsen werden, die, wenn die Isolierschicht 1 eine große Schichtdicke von beispielsweise 20 μm hat, dann mit einer Kupferschicht (entsprechend der Verstärkungsschicht 9) mit ebenfalls einer Schichtdicke von 20 μm verstärkt wird. Anstelle einer Schichtdicke von 20 μm können beispielsweise auch Schichtdicken von 10 μm bis 30 μm gewählt werden. Eine solche Kupferschicht kann dann optional wieder mit einer beispielsweise 50 nm dicken Nickel- und/oder Goldschicht veredelt werden.For producing the reinforcing layer 9 can on the surface of the semiconductor body 7 for the formation of the contact surface 3 Also, a germination layer can be chemically grown, which, when the insulating layer 1 has a large layer thickness of, for example, 20 microns, then with a copper layer (corresponding to the reinforcing layer 9 ) is also reinforced with a layer thickness of 20 microns. Instead of a layer thickness of 20 microns, for example, layer thicknesses of 10 microns to 30 microns can be selected. Such a copper layer can then optionally be refined again with, for example, a 50 nm-thick nickel and / or gold layer.

Wesentlich an der vorliegenden Erfindung ist also, dass durch die Verstärkungsschicht 9 der eigentliche Bondfleck auf die Höhe der Chipoberfläche, also auf die Höhe der Isolierschicht 1 im Bereich der Umgebung des Bondflecks angehoben wird.Essential to the present invention is therefore that through the reinforcing layer 9 the actual bonding spot on the height of the chip surface, ie on the height of the insulating layer 1 is raised in the vicinity of the bonding spot.

Wie aus einem Vergleich der 2A (Erfindung) mit der 1B (Stand der Technik) folgt, kann bei der Erfindung die Abmessung D' der Kontaktierungsfläche 3 bzw. der Bondinsel 11 wesentlich kleiner gewählt werden als die Abmessung D der Kontaktierungsfläche 3 beim Stand der Technik. Die Erfindung ermöglicht also mittels einer relativ einfachen Maßnahme, nämlich der Anbringung der Verstärkungsschicht 9, erhebliche Vorteile zur Miniaturisierung eines Halbleiterbauelements und damit auch einer integrierten Schaltung.As if from a comparison of 2A (Invention) with the 1B According to the prior art, in the invention, the dimension D 'of the contacting surface 3 or the bond island 11 be chosen much smaller than the dimension D of the contacting surface 3 in the prior art. The invention thus makes it possible by means of a relatively simple measure, namely the attachment of the reinforcing layer 9 , considerable advantages for miniaturization of a semiconductor device and thus also an integrated circuit.

11
Isolierschichtinsulating
22
Öffnungopening
33
Kontaktierungsflächecontacting surface
44
Kontaktierungsdrahtbonding wire
55
ÜberstandGot over
66
Kanteedge
77
HalbleiterkörperSemiconductor body
88th
KugelBullet
99
Verstärkungsschichtreinforcing layer
1010
Veredelungsschichtfinishing layer
1111
BondflächeBond area
1212
Bekeimungsschichtseeding layer

Claims (16)

Kontaktierungsanordnung für ein Halbleiterbauelement mit einem Halbleiterchip (7, 1), bei der ein Kontaktierungsdraht (4) elektrisch mit einer auf einem Halbleiterkörper (7) vorgesehenen Kontaktierungsfläche (3) verbunden ist, die im Wesentlichen von einer Isolierschicht (1) umgeben ist, so dass die Oberfläche der Isolierschicht (1) in Bezug auf den Halbleiterkörper (7) höher liegt als die Kontaktierungsfläche (3), dadurch gekennzeichnet, dass auf der Kontaktierungsfläche (3) eine Verstärkungsschicht (9) aufgetragen ist, deren Schichtdicke so groß gewählt ist, dass die Oberfläche der Verstärkungsschicht (9), mit der der Kontaktierungsdraht (4) verbunden ist, in Bezug auf die Oberfläche des Halbleiterkörpers (7) etwa gleich hoch oder höher ist als die Oberfläche der Isolierschicht (1) im Bereich der Umgebung der Verstärkungsschicht (9).Contacting arrangement for a semiconductor component with a semiconductor chip ( 7 . 1 ), in which a contacting wire ( 4 ) electrically with a on a semiconductor body ( 7 ) contacting surface ( 3 ), which essentially consists of an insulating layer ( 1 ), so that the surface of the insulating layer ( 1 ) with respect to the semiconductor body ( 7 ) is higher than the contact surface ( 3 ), characterized in that on the contacting surface ( 3 ) a reinforcing layer ( 9 ) whose layer thickness is chosen so large that the surface of the reinforcing layer ( 9 ), with which the contacting wire ( 4 ), with respect to the surface of the semiconductor body ( 7 ) is approximately equal to or higher than the surface of the insulating layer ( 1 ) in the vicinity of the reinforcement layer ( 9 ). Kontaktierungsanordnung nach Anspruch 1, dadurch gekennzeichnet, dass die Oberfläche der Verstärkungsschicht (9) höher ist als die Oberfläche des Halbleiterchips (7, 1) im Bereich der Verstärkungsschicht (9).Contacting arrangement according to claim 1, characterized in that the surface of the reinforcing layer ( 9 ) is higher than the surface of the semiconductor chip ( 7 . 1 ) in the region of the reinforcing layer ( 9 ). Kontaktierungsanordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die Verbindungsschicht (9) auf ihrer Oberfläche eine Bondinsel bildet.Contacting arrangement according to claim 1 or 2, characterized in that the connecting layer ( 9 ) forms a bonding pad on its surface. Kontaktierungsanordnung nach Anspruch 2 oder 3, dadurch gekennzeichnet, dass der Bereich ungefähr die n-fache Abmessung der Bondinsel hat.Contacting arrangement according to claim 2 or 3, characterized characterized in that the range is approximately n times the dimension of the Bond island has. Kontaktierungsanordnung nach Anspruch 4, dadurch gekennzeichnet, dass n > 1,3 ... 1,5 gilt.Contacting arrangement according to claim 4, characterized characterized in that n> 1.3 ... 1.5 applies. Kontaktierungsanordnung nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass die Isolierschicht (1) eine Passivierungsschicht ist.Contacting arrangement according to one of claims 1 to 5, characterized in that the insulating layer ( 1 ) is a passivation layer. Kontaktierungsanordnung nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die Schichtdicke, der Verstärkungsschicht (9) im Wesentlichen der Schichtdicke der Isolierschicht (1) entspricht.Contacting arrangement according to one of claims 1 to 6, characterized in that the layer thickness, the reinforcing layer ( 9 ) substantially the layer thickness of the insulating layer ( 1 ) corresponds. Kontaktierungsanordnung nach Anspruch 7, dadurch gekennzeichnet, dass die Schichtdicken der Isolierschicht (1) und der Verstärkungsschicht (9) im Wesentlichen jeweils etwa 3 μm betragen.Contacting arrangement according to claim 7, characterized in that the layer thicknesses of the insulating layer ( 1 ) and the reinforcing layer ( 9 ) are substantially each about 3 microns. Kontaktierungsanordnung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass die Verstärkungsschicht (9) eine Nickelschicht ist.Contacting arrangement according to one of claims 1 to 8, characterized in that the reinforcing layer ( 9 ) is a nickel layer. Kontaktierungsanordnung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, dass die Verstärkungsschicht (9) eine Kupferschicht ist.Contacting arrangement according to one of claims 1 to 8, characterized in that the reinforcing layer ( 9 ) is a copper layer. Kontaktierungsanordnung nach einem der Ansprüche 1 bis 10, dadurch gekennzeichnet, dass auf die Verstärkungsschicht (9) noch Veredelungsschichten (10) aufgetragen sind.Contacting arrangement according to one of claims 1 to 10, characterized in that on the reinforcing layer ( 9 ) or finishing layers ( 10 ) are applied. Kontaktierungsanordnung nach den Ansprüchen 9 und 11, dadurch gekennzeichnet, dass die Veredelungsschicht (10) eine Goldschicht ist.Contacting arrangement according to claims 9 and 11, characterized in that the finishing layer ( 10 ) is a gold layer. Kontaktierungsanordnung nach den Ansprüchen 10 und 11, dadurch gekennzeichnet, dass die Veredelungsschicht (10) eine Nickelschicht oder eine Goldschicht ist.Contacting arrangement according to claims 10 and 11, characterized in that the finishing layer ( 10 ) is a nickel layer or a gold layer. Kontaktierungsanordnung nach einem der Ansprüche 11 bis 13, dadurch gekennzeichnet, dass die Veredelungsschichten (10) eine Schichtdicke von etwa 25 bis 700 nm und insbesondere von etwa 50 nm aufweisen.Contacting arrangement according to one of claims 11 to 13, characterized in that the finishing layers ( 10 ) have a layer thickness of about 25 to 700 nm and in particular of about 50 nm. Kontaktierungsanordnung nach Anspruch 10, dadurch gekennzeichnet, dass die Kupferschicht eine Schichtdicke von etwa 10 bis 30 μm und insbesondere von 20 μm aufweist.Contacting arrangement according to claim 10, characterized characterized in that the copper layer has a layer thickness of about 10 to 30 μm and in particular of 20 μm having. Verfahren zum Herstellen der Kontaktierungsanordnung nach einem der Ansprüche 1 bis 15, dadurch gekennzeichnet, dass die Kontaktierungsfläche (3) zur Bildung einer Bekeimungsschicht (12) chemisch bekeimt und darauf dann die Verstärkungsschicht (9) abgeschieden wird.Method for producing the contacting arrangement according to one of Claims 1 to 15, characterized in that the contacting surface ( 3 ) to form a seeding layer ( 12 ) chemically germinated and then the reinforcing layer ( 9 ) is deposited.
DE200510019574 2005-04-27 2005-04-27 Contacting arrangement for a semiconductor device Expired - Fee Related DE102005019574B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE200510019574 DE102005019574B4 (en) 2005-04-27 2005-04-27 Contacting arrangement for a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE200510019574 DE102005019574B4 (en) 2005-04-27 2005-04-27 Contacting arrangement for a semiconductor device

Publications (2)

Publication Number Publication Date
DE102005019574A1 true DE102005019574A1 (en) 2006-11-09
DE102005019574B4 DE102005019574B4 (en) 2009-07-30

Family

ID=37111280

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200510019574 Expired - Fee Related DE102005019574B4 (en) 2005-04-27 2005-04-27 Contacting arrangement for a semiconductor device

Country Status (1)

Country Link
DE (1) DE102005019574B4 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012049087A3 (en) * 2010-10-13 2012-06-21 Abb Research Ltd Semiconductor module and method of manufacturing a semiconductor module
DE102015219183A1 (en) * 2015-10-05 2017-04-06 Infineon Technologies Ag Semiconductor device load connection

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476927A (en) * 1990-07-19 1992-03-11 Nec Corp Semiconductor integrated circuit
EP0720234A2 (en) * 1994-12-30 1996-07-03 SILICONIX Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same
JP2000058580A (en) * 1998-08-13 2000-02-25 Nec Corp Semiconductor device having bonding pad
EP1159413A2 (en) * 1999-02-26 2001-12-05 Millennium Pharmaceuticals, Inc. Secreted proteins and uses thereof
US20030102563A1 (en) * 2001-11-30 2003-06-05 Mercado Lei L. Semiconductor power device and method of formation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0182503B1 (en) * 1995-12-30 1999-04-15 김광호 Semiconductor chip with smaller bonding window than wire ball and its manufacturing method
DE102004036140A1 (en) * 2004-07-26 2006-03-23 Infineon Technologies Ag Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0476927A (en) * 1990-07-19 1992-03-11 Nec Corp Semiconductor integrated circuit
EP0720234A2 (en) * 1994-12-30 1996-07-03 SILICONIX Incorporated Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same
JP2000058580A (en) * 1998-08-13 2000-02-25 Nec Corp Semiconductor device having bonding pad
EP1159413A2 (en) * 1999-02-26 2001-12-05 Millennium Pharmaceuticals, Inc. Secreted proteins and uses thereof
US20030102563A1 (en) * 2001-11-30 2003-06-05 Mercado Lei L. Semiconductor power device and method of formation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012049087A3 (en) * 2010-10-13 2012-06-21 Abb Research Ltd Semiconductor module and method of manufacturing a semiconductor module
CN103155131A (en) * 2010-10-13 2013-06-12 Abb研究有限公司 Semiconductor module and method of manufacturing a semiconductor module
DE102015219183A1 (en) * 2015-10-05 2017-04-06 Infineon Technologies Ag Semiconductor device load connection
DE102015219183B4 (en) 2015-10-05 2019-06-06 Infineon Technologies Ag Power semiconductor device, semiconductor module, method for processing a power semiconductor device
US10756035B2 (en) 2015-10-05 2020-08-25 Infineon Technologies Ag Semiconductor device load terminal

Also Published As

Publication number Publication date
DE102005019574B4 (en) 2009-07-30

Similar Documents

Publication Publication Date Title
DE10333841B4 (en) A method of producing a benefit having semiconductor device locations arranged in rows and columns and methods of making a semiconductor device
DE19743767B4 (en) A method of manufacturing a semiconductor die package having a surface mount semiconductor die and a semiconductor die package having a semiconductor die fabricated therefrom
DE102006033222B4 (en) Module with flat structure and procedure for assembly
DE102005028951B4 (en) Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device
DE102011079708B4 (en) SUPPORT DEVICE, ELECTRICAL DEVICE WITH SUPPORT DEVICE, AND METHOD FOR MANUFACTURING SAME
DE102011053149C5 (en) Die arrangement and method for processing a die
DE102006015447A1 (en) Power semiconductor component with a power semiconductor chip and method for producing the same
DE102005034485A1 (en) Connecting element for a semiconductor component and method for its production
DE102007063308A1 (en) diode
DE102019202715A1 (en) FILM-BASED PACKAGE WITH DISTANCE COMPENSATION
DE10223738B4 (en) Method for connecting integrated circuits
DE102010045055A1 (en) Method for producing a semiconductor component with a via and semiconductor device with via
DE102006043133B4 (en) Terminal pad for contacting a device and method for its preparation
DE102005019574B4 (en) Contacting arrangement for a semiconductor device
DE10233641B4 (en) Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
DE102005006281B4 (en) High frequency power device with gold coatings and method of making the same
DE10139985B4 (en) Electronic component with a semiconductor chip and method for its production
WO1996009647A1 (en) Process for contacting an electronic component on a substrate
DE10116069A1 (en) Electronic component with a semiconductor chip and method for its production
DE10108081B4 (en) Arrangement of a semiconductor chip on a substrate
WO2021069459A1 (en) Contact assembly for an electronic component, and method for producing an electronic component
DE102015221979A1 (en) Contacting arrangement for a printed circuit board substrate and method for contacting a printed circuit board substrate
DE102005007643A1 (en) Method and device for contacting semiconductor chips on a metallic substrate
DE102017102035A1 (en) A semiconductor device, method of manufacturing a semiconductor device, and method of amplifying a die in a semiconductor device
DE102017211058B4 (en) Method for producing an electronic component and electronic component

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee