DE102005008392B4 - FeRAM memory cell, FeRAM memory circuit and method for storing a datum value in a FeRAM memory cell - Google Patents

Abstract

An FeRAM memory cell having a selection transistor and a ferroelectric memory element for storing data comprising:
A first and a second capacitor electrode (23; 11; 12);
A first ferroelectric region (14) of a first ferroelectric material which extends in a first section (A1) between the first and second capacitor electrodes (2, 3) and in the first section (A1) a first coercive voltage (V _c1 ) and causing a first remanent polarization charge (P _r1 );
A second ferroelectric region (5) of a second ferroelectric material extending in a second section (A2) between the first and second capacitor electrodes (2, 3; 11, 12) and in the second section (A2) a second coercive voltage (V _C2 ) and a second remanent polarization charge (P _r2 ) causes;
wherein the first and second ferroelectric regions (4) are configured so that the first and second coercive voltages (V _C1 , V _C2 ) and the first and second remanent polarization charges (P _r1 , P _r2 ) are different, respectively. ,

Description

The The invention relates to a FeRAM memory cell for storing data in the form of a remanent polarization of a ferroelectric region. The The invention further relates to a FeRAM memory circuit and method for storing a date value in a FeRAM memory cell.

ferroelectric Memory cells usually include a capacitor structure with capacitor electrodes, between which a ferroelectric material is arranged. According to a suitable Write voltage applied to the capacitor electrodes, can adjust the polarization of the ferroelectric material which causes a state in the ferroelectric memory cell can be stored. Reading out the state from the ferroelectric Memory cell is done by applying a certain reading voltage, being characterized by the occurrence or non-occurrence of a sudden charge change the capacitor structure is determined, whether the polarization the ferroelectric memory cell changes when the read voltage is applied or Not. Depending on whether it is determined that the polarization changes or not, becomes a certain state in the ferroelectric memory cell recognized.

The Polarization of the ferroelectric material causes a hysteresis behavior a polarization-voltage characteristic. The hysteresis behavior becomes caused by the remanent polarization, d. H. the polarization charge of the ferroelectric material when no electric field applied is. The polarization of the ferroelectric material changes a correspondingly applied electric field strength, the the polarization is directed against. The tension at which the Polarization changes, is called coercive stress.

in the Comparison to other types of non-volatile memory cells, such as For example, EEPROM memory cells or flash memory cells is integrated with one Building the needed area for one FeRAM memory cell more than twice as large, so that so far comparable Storage densities can not be achieved with FeRAM memory cells.

From the publication DE 197 24 449 A1 is a FeRAM memory cell with a selection transistor and a ferroelectric memory element for storing data known that a first and a second capacitor electrode, a first ferroelectric region of a first ferroelectric material extending in a first portion between the first and second capacitor electrode and in causing the first portion to have a first coercive voltage and a first remnant polarization, and a second ferroelectric region of a second ferroelectric material extending in a second portion between the first and second capacitor electrodes and in a second portion a second coercive voltage and a second remanent polarisate charge wherein the first and second ferroelectric regions are configured so that the first and second coercive voltages and the first and second remanent polarization charges are different, respectively, so that d The capacitor structure formed by the capacitor electrodes has a stepped hysteresis characteristic in a polarization charge-voltage characteristic, and wherein the first and second ferroelectric regions follow one another in a direction perpendicular to one another. extends to the distance direction of the two capacitor electrodes are arranged.

From the DE 19724499 A1 Further, an FeRAM memory cell having a selection transistor and a ferroelectric memory element for storing data is known, comprising first and second capacitor electrodes, a first ferroelectric region of a first ferroelectric material extending in a first portion between the first and second capacitor electrodes and causing a first coercive voltage and a first remnant polarization in the first portion and a second ferroelectric region of a second ferroelectric material extending in a second portion between the first and second capacitor electrodes and in a second portion a second coercive voltage and a second remanent Polarisatoinsladung causes, wherein the first and the second ferroelectric region are designed so that the first and second coercive voltage and the first and second remanent polarization charge are different, in each case in that the capacitor structure formed by the capacitor electrodes has a stepped hysteresis characteristic in a polarization charge-voltage characteristic, and wherein the first and second ferroelectric materials are different.

The publication DE 102 19 396 A1 shows a ferroelectric device having a plurality of dielectric regions between two capacitor electrodes.

From the publication US 5,495,438 A ferroelectric memory elements with a ferroelectric material with different remanent polarizations are disclosed. In order to bring about a graded hysteresis characteristic, the ferroelectric memory element has a capacitor structure with different regions, wherein capacitor electrodes have different spacings in the different regions.

From the publication EP 0 720 172 A2 For example, a ferroelectric memory element is known that has two capacitor structures each containing a ferroelectric material of different thickness.

Also the publication US 2001/0022292 A1 shows a ferroelectric memory element with a capacitor element having sections of different thickness.

From the publication US 6,091,621 A For example, a field effect transistor structure in which the gate electrode is separated from the channel region by a two-part region with ferroelectric materials is known, wherein the different regions have different ferroelectric properties.

In 3 is one of the DE 197 24 499 A1 known embodiment of a ferroelectric memory element shown. The ferroelectric memory element 10 has a first section A1 and a second section A2. The ferroelectric memory element of the known embodiment is formed as a capacitor structure, and has a first capacitor electrode 11 and a second capacitor electrode 12 on. The area between the capacitor electrodes 11 . 12 In contrast to the invention, it is filled with the same ferroelectric material (eg PZT). In a first section A1, the capacitor electrodes 11 . 12 spaced at a first smaller distance d1 from each other, while in a second area A2, the capacitor electrodes 11 . 12 spaced at a greater distance d2. This becomes a step structure of the capacitor electrodes 11 . 12 educated. Such a structure of a ferroelectric memory element 10 leads to different hysteresis characteristics of the polarization-voltage characteristic. Due to the used, identical, ferroelectric material in both sections A1, A2 of the ferroelectric memory element 10 and due to the substantially equal capacitor areas in the sections A1, A2, both sections of the ferroelectric memory element have an identical remanent polarization P _r . Only because of the different distances d1, d2 in the capacitor electrodes 11 . 12 For example, the coercive voltages V _{C of} the two sections A1, A2 are different since the electric field strength acting on the ferroelectric material arrives. In particular, to achieve a same field strength value in the second section A2, a higher voltage must be applied to the capacitor electrodes 11 . 12 be created because there the electrode distance d2 is greater than in the first section A1.

In order in the embodiment of the 3 It would also be possible to achieve different remanent polarizations P _r without using different ferroelectric materials, the surfaces of the capacitor electrodes 11 . 12 be selected differently in sections A1, A2. Ie. In general, the coercive voltage V _c of such a ferroelectric memory element with multiple sections can be determined by the choice of the ferroelectric material and / or by different distances between the capacitor electrodes 11 . 12 in sections A1, A2. A suitable remanent polarization P _r can be achieved in the two sections by the choice of different ferroelectric materials and / or by the provision of different areas of the capacitor electrodes 11 . 12 in sections A1, A2.

In the 4a and 4b With reference to the embodiment of the ferroelectric memory element according to FIG 3 the polarization-voltage characteristics for both the individual sections A1, A2 of the ferroelectric memory element as well as for the entire ferroelectric memory element shown. One recognizes in 4c in that the superimposition of the hysteresis characteristics leads to three different remanent polarizations of the overall arrangement of the ferroelectric memory element occurring. The fact that only three instead of four different polarization values occur is due to the fact that the remanent polarizations P _{r of} both sections of the embodiment of FIG 3 are identical. Thus, the total remanent polarizations coincide with a negative remanent polarization of the first portion and a positive polarization of the second portion and a positive remanent polarization of the first portion and a negative remanent polarization of the second portion and add up to a total remanent polarization from 0.

task In the invention, it is a FeRAM memory cell, a FeRAM memory circuit and a method of storing a date value in the Fe-RAM memory cell to increase the storage density of data and a reliable one Reading and reading guaranteed becomes.

These The object is achieved by the FeRAM memory cell according to claim 1, which FeRAM memory circuit according to claim 7 and by the method solved according to claim 13.

Further advantageous embodiments of the invention are specified in the dependent claims.

According to a first aspect of the present invention, a ferroelectric memory is ment for storing data. The ferroelectric memory element comprises a first and a second capacitor electrode, between which a first ferroelectric region and a second ferroelectric region are arranged. The first ferroelectric region extends in a first section between the first and second capacitor electrodes and effects a first coercive field strength and a first remanent polarization in the first section. The second ferroelectric region is located in a second portion between the first and second capacitor electrodes and effects a second coercive force and a second remanent polarization in the second portion. The first and second ferroelectric regions are made of different materials so that the first and second coercive forces and the first and second remanent polarizations are different, so that the capacitor structure formed by the capacitor electrodes has a stepped hysteresis characteristic in a polarization voltage Characteristic of the ferroelectric memory element.

The ferroelectric memory element according to the present invention, allows it's more than two states take, and thus more than one bit to save. this will through several ferroelectric areas that allows between the two Capacitor electrodes substantially side by side with respect to a Direction, which is perpendicular to the distance direction of the two capacitor electrodes, arranged are. About that In addition, the first and the second ferroelectric region with formed of different ferroelectric materials. The ferroelectric regions have different coercivities and various remanent polarizations, preferably at different Coercive voltages are taken. Thus it is possible the ferroelectric areas independently from each other with a rectified or opposite polarization to prove, so that in the best case four different states in the ferroelectric memory element can be taken.

It can be provided that in the first and second ferroelectric Area the distances different between the first and second capacitor electrodes are to adjust the amount of each coercive force, and / or the surfaces the capacitor electrodes, which are different in the first and second sections are to adjust the amount of each remanent polarization.

Preferably the first and second ferroelectric regions are designed that the amounts the first and the second coercive force by a factor of at least two different. Furthermore, the first and the second are ferroelectric Area preferably designed so that the amounts of the first and the second remanent polarization by a factor of at least two differ.

According to one Another aspect of the present invention is a FeRAM memory circuit for storing a date in such a ferroelectric Storage element provided. The ferroelectric memory element has a write circuit which is designed so that one after the other one of a date to be stored dependent first and second writing voltage is applied to the ferroelectric memory element to a first and a second polarization charge of the first and second ferroelectric, respectively Area dependent from the date to be stored. This way you can a two-phase write process are performed, in which first the polarization of the ferroelectric field with the larger coercive field and subsequently the polarization of the ferroelectric region with the lower one coercivity is determined.

Preferably For example, the magnitude of the first write voltage may be greater than the larger of the voltages. the coercivities cause, and the amount of the second write voltage to be greater as the smaller of the voltages that cause the coercivities, and smaller than the larger of the Tensions that cause the coercive force to be.

Especially For example, the writing circuit may be designed to have a first date is stored in the ferroelectric memory element by the first write voltage is applied as a positive voltage that a second datum is stored in the ferroelectric memory element is determined by the first write voltage as a positive voltage and the second write voltage is applied as a negative voltage, a third date in the ferroelectric memory element is stored by the first write voltage as a negative voltage is applied, and that a fourth date in the ferroelectric Memory element is stored by the first write voltage as negative voltage and the second writing voltage positive voltage be created.

Preferably, the ferroelectric memory element is arranged on a word line and a bit line and selectable by an associated selection transistor, wherein the write circuit generates a selection signal which can be applied to the word line. A write potential is provided on the bit line, wherein the selection transistor connects the ferroelectric memory element to the bit line depending on the selection signal apply first and second write voltage to the ferroelectric memory element. In particular, the ferroelectric memory element may be connected to a potential line, via which a further writing potential is provided, so that the first and the second writing voltage are formed as a difference voltage between the writing potential and the further writing potential.

Preferably may be provided a readout circuit which is designed that when reading a first reading voltage whose amount is greater as the smaller of the voltages that cause the coercivities, and smaller than the larger one Voltages that cause the coercive field strengths to the ferroelectric Memory element is applied and a measure of the first charge flow is detected at the ferroelectric memory element and that subsequently a second reading voltage whose magnitude is greater than the larger of the Voltages that cause the coercive field strengths at the ferroelectric Memory element is applied and a measure of a second charge flow is detected at the ferroelectric memory element. To this A two-phase read-out process is carried out at at first the polarization charge of the ferroelectric region with the lower the voltages that cause the coercive field strengths, and then the Polarization charge of the ferroelectric region with the higher coercive voltage is determined.

Preferably the readout circuit may be dependent from the measure of first charge flow and the extent of the second charge flow the date stored in the ferroelectric memory element determine.

Especially For example, the readout circuit may be coupled to the write circuit be to read the read-out date into the ferroelectric after reading out Memory element again according to a write operation save. This is useful if the read-out date continues is to be provided in the memory cell, as by the read-out process the previously stored information is lost.

According to one Another aspect of the present invention is a method for Storing a date in a ferroelectric memory element intended. According to the procedure are successively one dependent on a date to be stored first and / or second writing voltage to the ferroelectric memory element applied to the first and the second polarization charge of the first and the second ferroelectric region depending on the one to be stored Set date.

Especially a first date is stored in the ferroelectric memory element, in which the first writing voltage is applied as a positive voltage with a second datum in the ferroelectric memory element is stored by the first write voltage as a positive voltage and the second writing voltage is applied as a negative voltage, a third datum in the ferroelectric memory element is stored, in which the first write voltage as a negative voltage is applied, and wherein a fourth date in the ferroelectric Memory element is stored by the first write voltage as negative voltage and the second writing voltage as positive Voltage to be applied.

Preferably when reading a first reading voltage whose amount is greater as the smaller of the coercive voltages and smaller than the larger one of the Voltages that cause the coercive field strengths to the ferroelectric Memory element applied and a measure of the first charge flow detected at the ferroelectric memory element. Subsequently, will a second read voltage whose magnitude is greater than the greater of the voltages, the coercivities cause, applied to the ferroelectric memory element and a measure of one second charge flow to the ferroelectric memory element detected. Preferably, in the ferroelectric memory element stored date dependent from the measure of first charge flow and the extent of the second charge flow certainly.

preferred embodiments The present invention will now be described with reference to the accompanying drawings explained in more detail. It demonstrate:

1 a schematic representation of a cross section through a ferroelectric memory element according to an embodiment of the present invention;

2 both the individual polarization-voltage characteristics of the sections of the ferroelectric memory element of 1 and a resulting common polarization-voltage characteristic having a stepped hysteresis characteristic;

3 a schematic representation of a cross section of a known embodiment of a ferroelectric memory element;

4 a representation of the respective hysteresis characteristic of the individual sections of the ferroelectric Speicherele element after 3 , as well as a common polarization-voltage characteristic;

5 a block diagram of a FeRAM memory circuit according to a preferred embodiment of the invention;

6a to 6d shows various sequences of voltage pulses applied to the ferroelectric memory element to describe it with a particular date;

7 shows a polarization-voltage characteristic with a stepped hysteresis, in which the remanent polarization charges with respect to the circumscribed states of the 6a to 6d are shown;

8a shows the course of a read voltage to a ferroelectric memory element for reading the stored state in the ferroelectric memory element;

8b Quantitatively, a measure of the resulting charge flux at the ferroelectric memory element is dependent on the read pulses.

In 1 is a schematic representation of a cross section of a ferroelectric memory element according to a first embodiment of the invention shown. The ferroelectric memory element 1 is in the form of a capacitor structure with a first capacitor electrode 2 and a second capacitor electrode 3 educated. Between the capacitor electrodes 2 . 3 is located in a first section A1, a first ferroelectric region 4 formed with a first ferroelectric material. In a second section A2 is located between the first and second capacitor electrode 2 . 3 a second ferroelectric region 5 with a second ferroelectric material.

Ferroelectric materials are polarizable upon application of an electric field. If a ferroelectric material is located between capacitor electrodes of a capacitor, this material can amplify or attenuate an electric field existing between the capacitor plates, depending on the polarization charge. In this case, the ferroelectric material can essentially assume two extreme states of polarization, which are indicated by a remanent polarization value P _r . The remanent polarization value P _r corresponds to a field strength caused by the ferroelectric material when no voltage is applied to the capacitor electrodes. The amount of remanent polarization is substantially independent of the sign, so that depending on the state of the ferroelectric material between the capacitor electrodes a positive remanent polarization + P _r or a negative remanent polarization -P _r is present. The remanent polarization P _{r of} a ferroelectric material can be changed when a polarization-opposing electric field strength is applied between the capacitor electrodes, wherein the sign of the remanent polarization P _{r of} the ferroelectric material changes substantially at a certain coercive force.

The voltage value (or electric field strength) at which there is a sudden change in the polarization of the ferroelectric material is called coercive voltage V _c (coercive field strength). The amount of the coercive voltage V _c when changing from a negative to a positive polarization and a change from a positive to a negative polarization is substantially constant and has a different sign depending on the polarization change.

It can be seen that the polarization and the voltage applied to the capacitor electrodes form a hysteresis characteristic as shown in FIGS 2a and 2 B for the different sections A1 and A2 of the ferroelectric memory element.

The ferroelectric memory element shown is thus formed by a capacitor having two different ferroelectric materials. The two ferroelectric materials are juxtaposed between the capacitor electrodes with respect to a direction perpendicular to the pitch direction 2 . 3 arranged. The capacitor electrodes 2 . 3 are preferably formed as planar capacitor plates to achieve a uniform electric field strength upon application of a voltage in the respective first and second ferroelectric region. In the 2a and 2 B is the electrical behavior of the two sections A1, A2 of the ferroelectric memory element illustrated by a polarization-voltage characteristic.

When comparing the hysteresis characteristics of 2a and 2 B it can be seen that the second ferroelectric material has a low remanent polarization but a higher coercive force (coercive force) compared to the first ferroelectric material.

In an arrangement as used in the embodiment of the 1 is shown, there is a simple superposition of the hysteresis of the individual sections of the ferroelectric memory element. A resulting polarization-voltage characteristic is formed, which essentially has a stepped hysteresis characteristic. The stepped hysteresis characteristic is essentially caused by the different remanent polarizations P _r1 , P _r2 , which are obtained by addition or subtraction of the remanent polarizations P _r1 , P _{r2 of} the provide first and second ferroelectric region of the ferroelectric memory element. Thus, depending on the memory state (respective polarization of the first and second ferroelectric region) of the ferroelectric memory element, a first remanent polarization Pr1-Pr2, a second remanent polarization Pr1 + Pr2, a third remanent polarization -Pr1 + Pr2 and a fourth remanent polarization -Pr1 - Pr2 be accepted. By means of a suitable writing method, the remanent polarizations of the ferroelectric regions can be set individually. The thus set states of the FeRAM memory cell can be read out by a suitable reading method. Writing and reading methods are described below.

As low coercive field strength ferroelectric materials, SrBi ₂ Tr ₂ O ₉ (strontium bismuth tantalate, SBT), lead zirconate titanate (BZT) and the like come into consideration. Preferably, ferroelectric materials having a low coercive field strength are materials to be selected which have a coercive force of 10-50 kV / cm. As ferroelectric materials with high Koerzitvfeldstärke lithium niobate (LiNbO ₃ and lithium tantalate LiTaO ₃ ) are mentioned. These preferably have a coercive field strength between 150-300 kV / cm, preferably 200 kV / cm.

In 5 For example, a FeRAM memory circuit having such a ferroelectric memory element is shown as a block diagram. Illustrated is an example FeRAM memory cell with a selection transistor 20 and a ferroelectric memory element 21 educated. For the sake of clarity, only one FeRAM memory cell is shown in the illustrated FeRAM memory circuit, but it is located in a matrix of FeRAM memory cells which can be addressed via a plurality of word lines and bit lines WL, BL. The word lines WL are provided with a word line decoder 22 having an input through which the wordline decoder 22 with a write circuit 23 and a readout circuit 24 connected is. Furthermore, the wordline decoder is 22 provided with an address input to receive a word line address. The bit lines BL are switching means with a bit line 25 connected depending on a to be addressed FeRAM memory cell selects a bit line BL and one of the write circuit 23 or the readout circuit 24 provided bit line potential to the relevant bit line BL applies. The wordline decoder 22 activates the relevant word line WL, depending on the address of the FeRAM memory cell to be addressed, and switches the associated selection transistor 20 by.

The following is with reference to the 6a to 6d to a write in a FeRAM memory cell, as in the embodiment of the FeRAM memory circuit according to 5 used, received. The writing process is essentially done by the writing unit 23 controlled. The writing process is explained essentially on the basis of a FeRAM memory cell, wherein the ferroelectric memory element 21 according to the embodiment of the 1 is formed, wherein four different states than different remanent polarizations P _r in the ferroelectric memory element 21 can be stored. In describing the FeRAM memory cell, first, the corresponding word line WL is passed through the word line decoder 22 activated so that the selection transistor 20 is switched through. Subsequently, via the bit line BL, a first potential pulse to the ferroelectric memory element 21 applied, which causes over the ferroelectric memory element 21 a write voltage is applied whose magnitude is greater than the second coercive voltage V _{C2 of} that portion of the ferroelectric memory element having the higher coercive voltage, ie in the embodiment of 1 a voltage greater than the second coercive voltage V _{C2 of} the second portion A2. Depending on the state to be written, the first write voltage may be positive or negative and adjusts the polarization charge of the second portion of the ferroelectric memory element depending on the sign of the first write voltage. Since the coercive voltage V _{C1 of} the first section A1, that is, the Koerzi tivspannung of the portion with the lower coercive voltage is smaller than the amount of the memory element 21 adjacent the first write voltage and the remanent polarization of the first section A1 of the ferroelectric memory element is set accordingly. Subsequently, a second write voltage is applied to the memory element via the corresponding bit line BL 21 whose amount is smaller than the coercive voltage of the ferroelectric region having the larger coercive voltage and larger than the coercive voltage of the ferroelectric region having the smaller coercive voltage.

However, this is only necessary if the polarization charge of the first ferroelectric region to the polarization charge of the second ferroelectric region has an inverse sign. Should a state in the memory element 21 can be written, in which both ferroelectric regions are to have the same sign of the polarization charge, it may be sufficient, only a first write voltage to the ferroelectric memory element 21 to be applied, as it also sets the polarization charge of the first ferroelectric region.

In the 6a and 6d is this option shown in dashed lines. When writing the states "1" and "2", however, it is necessary, as in the 6b and 6d 2, it is shown how to describe the ferroelectric memory element in two steps by initially applying a first corresponding write potential and then a second write potential with opposite sign but with a lower voltage to the FeRAM memory cell.

To the respective write voltage on the memory element 21 is applied, a bit line potential is selected which corresponds to the corresponding potential difference to the potential on a potential line 26 having. The potential line 26 is connected to the ferroelectric memory element and is either maintained at a fixed potential, so that the bit line potential depending on the write potential, a positive or negative voltage difference to the specified potential on the potential line 26 has, or the potential line 26 depends on the memory element 21 to be applied write voltage with respect to the bit line potential on the bit line BL changed. This is in the present embodiment, the in 5 is achieved, achieved in that the potential line 26 with the bit line switching device 25 is connected, in addition to the bit lines BL and the potential lines 26 correspondingly connects with the corresponding further writing potential.

The successive application of the two write voltage pulses to the ferroelectric memory element 21 can be done by the write voltage pulses at previously switched through the selection transistor 20 to the bit line BL controlled by the write circuit 23 or by the bit line switching device 25 be created. The write voltage pulses can thereby also be applied to the memory element 21 be created, that first to the bit line BL, the first write potential is applied, and then for a predetermined period of time, the word line is activated to the selection transistor 20 turn on. Subsequently, the bit line BL is charged to the second write potential and the same word line WL is activated again for a predetermined period of time. The writing circuit 23 may decide whether a single-stage or two-stage writing process is necessary depending on the state to be written to the memory element, and in the case that only a simple write voltage pulse is applied to the memory element 21 must be created, the write circuit 23 continue writing a date to another memory cell. This saves time in writing to multiple memory cells. In 7 the writing process is clarified again. By means of dashed arrow lines is based on the step-shaped hysteresis of the ferroelectric memory element of 1 Describing the description of the various states. It can be seen that, when writing a state "0", first a voltage pulse is applied in a process IV so that both ferroelectric regions receive a positive remanent polarization. To write a state "1", first a write pulse, according to a process II , to the storage element 21 created. As a result, both ferroelectric regions receive negative remanent polarizations, the retentive polarization of the lower coercive voltage ferroelectric region being changed again by means of the second write pulse, in a process III. To assume the state "2", first a first write voltage in a process IV to the memory element 21 and then the remanent polarization of the ferroelectric region with the lower coercive voltage using a second write voltage pulse, according to the process I changed. For writing a state "3", a first write voltage pulse, in a process II to the memory element 21 The application of a second write voltage pulse may optionally be performed since the lower coercive voltage ferroelectric region already has the desired remanent polarization.

For reading a FeRAM memory cell, as in 5 is shown, the readout circuit 24 used. The read-out process is in the signal-time diagram of 8a and 8b shown. 8a shows the read voltage pulses and 8b the resulting charge fluxes on the bit line BL depending on the stored state.

The readout circuit 24 controls the wordline decoder 22 and the bit line switching device 25 such that first a first read voltage pulse to the memory element 21 whose amount exceeds the first coercive voltage V _C1 of the lower coercive voltage ferroelectric region, but is smaller than the second coercive voltage V _C2 of the higher coercive voltage ferroelectric region. Depending on whether a polarization change when applying the first read voltage pulse in the memory element 21 occurs, a charge pulse on the bit line BL may or may not be detected. If a change in the value of the remanent polarization occurs, then a corresponding charge pulse flows since the effective capacitance of the memory element 21 almost leaps and bounds. If there is no change in the remanent polarization of the ferroelectric memory element, there is no sudden change in the capacitance of the memory element 21 and no charge pulse can be detected.

Subsequently, a second read voltage pulse is applied to the memory element 21 whose magnitude of the voltage is greater than the second coercive voltage V _C2 of the higher coercive voltage ferroelectric range. In the same way as in the first read voltage pulse, it is now also possible to determine whether or not a polarization change has occurred in the ferroelectric region with the higher coercive voltage in the case of the second read voltage pulse. The application of the read voltage pulses essentially takes place, as already described above with reference to the write voltage pulses. Thus, the read voltage pulses can be generated by applying the corresponding voltage pulses to the bit line when the word line is activated or by briefly activating the word line in succession. When reading the FeRAM memory cell, the polarity of the applied read voltage is essentially arbitrary, but it should be the same for the first and the second read voltage pulse.

When a FeRAM memory cell is read out, the information contained therein is destroyed during read-out by applying a read voltage which is higher than the coercive voltages of the ferroelectric regions of the FeRAM memory cell. After reading, therefore, a writing back of the information read is necessary, preferably by the writing circuit 23 controlled by the readout circuit 24 is carried out. The writing back of the read-out information is performed substantially as before with respect to the function of the writing circuit 23 has been described.

1

ferroelectric storage element

2

first capacitor electrode

3

second capacitor electrode

4

first ferroelectric range

5

second ferroelectric range

A1

first section

A2

second section

10

ferroelectric storage element

11

first capacitor electrode

12

second capacitor electrode

A1

first section

A2

second section

d1

first distance

d2

second distance

20

selection transistor

21

ferroelectric module

22

Word line decoder

23

write circuit

24

readout circuit

25

Bitleitungsschalteinrichtung

26

potential line

Claims (18)

FeRAM memory cell having a selection transistor and a ferroelectric memory element for storing data, comprising: a first and a second capacitor electrode ( 23 ; 11 ; 12 ); A first ferroelectric region ( 14 ) of a first ferroelectric material, which is located in a first section (A1) between the first and second capacitor electrodes (A1). 2 . 3 ) and in the first section (A1) causes a first coercive voltage (V _c1 ) and a first remanent polarization charge (P _r1 ); A second ferroelectric region ( 5 ) of a second ferroelectric material located in a second section (A2) between the first and second capacitor electrodes (A2). 2 . 3 ; 11 . 12 ) and in the second section (A2) causes a second coercive voltage (V _C2 ) and a second remanent polarization charge (P _r2 ); wherein the first and the second ferroelectric region ( 4 ) are configured such that the first and second coercive voltages (V _C1 , V _C2 ) and the first and second remanent polarization charges (P _r1 , P _r2 ) are each different, so that the _voltages passing through the capacitor electrodes ( 2 . 3 ; 11 . 12 ) has a stepped hysteresis characteristic in a polarization charge-voltage characteristic, wherein the first and the second ferroelectric region ( 2 . 3 ; 11 . 12 ) successively with respect to a direction perpendicular to the pitch direction of the two capacitor electrodes ( 2 . 3 ; 11 . 12 ) are arranged, and wherein the first and the second ferroelectric material ( 4 . 5 ) are different. An FeRAM memory cell according to claim 1, wherein in said first and second ferroelectric regions (Fig. 4 . 5 ) the spacings of the first and second capacitor electrodes are different. FeRAM memory cell according to one of claims 1 and 2, wherein the first and the second ferroelectric region ( 4 . 5 ) are configured such that the first and second coercive voltages (VC1, VC2) differ by a factor of at least 2. An FeRAM memory cell according to any one of claims 1 to 3, wherein the first and second ferroelectric regions ( 4 . 5 ) are designed so that the first and the second remanent polarization charge (Pr1, Pr2) differ by a factor of at least 2. FeRAM memory circuit for storing a data value with memory cells according to one of Claims 1 to 4 and with a write circuit ( 23 ), which is designed to be dependent on one first or successively a first and second write voltage to the ferroelectric memory element are applied to a first and a second remanent polarization charge of the first and second ferroelectric region ( 4 . 5 ) depending on the data value to be stored. The FeRAM memory circuit of claim 5, wherein the Amount of the first write voltage is greater than the larger of the Coercive voltages and the magnitude of the second write voltage is greater as the smaller of the two coercive voltages and smaller as the larger of the Coercive. A FeRAM memory circuit according to claim 6, wherein said write circuit ( 23 ) is designed such that a first data value in the ferroelectric memory element ( 21 ) is stored by applying the first writing voltage as a positive voltage, that a second data is stored in the ferroelectric memory element by applying the first writing voltage as a positive voltage and the second writing voltage as a negative voltage, that a third data in the ferroelectric memory element is stored by applying the first writing voltage as a negative voltage, and that a fourth data is stored in the ferroelectric memory element by applying the first writing voltage as a negative voltage and the second writing voltage as a positive voltage. FeRAM memory circuit according to one of claims 5 to 7, wherein the ferroelectric memory element is arranged on a word line (WL) and a bit line (BL) and through the selection transistor ( 20 ), wherein the write circuit generates a selection signal which is applied to the word line (WL) and provides a write potential on the bit line (BL), wherein the selection transistor ( 20 ) connects the ferroelectric memory element to the bit line depending on the selection signal to apply the write voltage to the ferroelectric memory element. FeRAM memory circuit according to claim 8, wherein the ferroelectric memory element on a potential line ( 26 ) is connected to provide another writing potential. FeRAM memory circuit according to one of claims 5 to 9, wherein a read-out circuit ( 24 ) is provided which is designed so that when reading a first read voltage whose amount is greater than the smaller of the coercive voltages and smaller than the greater of the coercive voltages is applied to the ferroelectric memory element and a measure of a first charge flow to the ferroelectric memory element is detected, and then that a second read voltage whose magnitude is greater than the greater of the coercive voltages, is applied to the ferroelectric memory element and a measure of a second charge flux is detected at the ferroelectric memory element. FeRAM memory circuit according to claim 10, wherein the readout circuit ( 24 ) determines the data value stored in the ferroelectric memory element, depending on the degree of the first charge flow and the degree of the second charge flow. FeRAM memory circuit according to claim 10 or 11, wherein the readout circuit ( 24 ) with the write circuit ( 23 ) is coupled so that after reading the read data in the ferroelectric memory element is stored again. Method for storing a data value in a memory cell according to one of claims 1 to 4, wherein, depending on a data value to be stored, a first or a successive first and second write voltage are applied to the ferroelectric memory element to generate the first and second remanent polarization charges of the first and second ferroelectric region ( 4 . 5 ) depending on the data value to be stored. The method of claim 13, wherein the amount of first write voltage is greater than the larger of the Coercive voltages and the amount of the second write voltage is selected to be larger as the smaller of the coercive voltages and smaller than the larger of the Coercive. The method of claim 14, wherein a first data value is stored in the ferroelectric memory element by applying the first write voltage as a positive voltage to the ferroelectric memory element, wherein a second data value is stored in the ferroelectric memory element by writing the first write voltage as a positive voltage and the second write voltage is applied as a negative voltage, - wherein a third data value is stored in the ferroelectric memory element by applying the first write voltage as a negative voltage, and - a fourth data value is stored in the ferroelectric memory element by the first write voltage as a negative voltage and the second write voltage to be applied as a positive voltage. Method according to one of claims 13 to 15, being at Read out a first read voltage whose amount is greater as the smaller of the coercive voltages and smaller than that larger of the Coercive voltages applied to the ferroelectric memory element becomes and a measure of one first charge flux detected at the ferroelectric memory element will, and subsequently a second reading voltage whose magnitude is greater than the larger of the Coercive voltages applied to the ferroelectric memory element becomes and a measure of one second charge flow to ferroelectric memory element detected becomes. The method of claim 14, wherein depending on the measure of first charge flow and the extent of the second charge flow the data stored in the ferroelectric memory element is determined. A method according to claim 14 or 15, wherein after Reading out the read-out data into the ferroelectric memory element is saved again.