DE102004060697A1 - Semiconductor circuit arrangement and method for producing a semiconductor circuit arrangement - Google Patents

Abstract

A semiconductor circuit arrangement for a memory cell (160) with a transistor body (150) is described. The transistor body (150) includes first and second doping regions (10a, 10b) and a channel region (110) therebetween. The memory cell (160) further comprises a gate electrode (3a) disposed over the channel region (110) and separated therefrom by a dielectric layer (2a). First portions (661) of an oxide-nitride-oxide layer (66) are disposed over the first and second doping regions (10a, 10b) and are substantially parallel to an upper surface (111) of the transistor body (150). Second portions (662) of the oxide-nitride-oxide layer (66) adjoin the gate electrode (3a) and extend in a direction that is substantially non-parallel to the top surface (111) of the transistor body (150) ,

Description

The The present invention relates to a semiconductor circuit arrangement and a method of manufacturing a semiconductor circuit device

portable Equipment, such as mobile phones, digital cameras, and music players contain nonvolatile Storage units. These portable devices have been smaller in recent years become, likewise the respective storage units. You go away that miniaturization of portable devices continues becomes. The amount of data that can be stored in the nonvolatile storage units is enlarged to the performance of the device to improve. As a result, can More songs, photos or other data stored in smaller devices become.

embodiments nonvolatile Memory units are for example read only memory (ROM), Programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (electrical erasable programmable read only memory - EEPROM).

Of the Advantage of the ROM is the low price per storage unit. The ROM can not be programmed electrically. The programming is done while one of the manufacturing steps. Special masks, which the too storing data structure the semiconductor memory according to the data information. After completion of the manufacturing process, the contents of the ROM can not more changed become. amendments lead to the data programming to a costly and time-consuming re-design of the special Masks.

Of the PROM is created as an empty memory. The ones to program Data is stored only after the actual production. After the once performed Programming, the content can not be changed.

Of the EPROM can be reprogrammed after being ultraviolet Exposed to extinguishing light has been.

Above described non-volatile Storage units can not electrically deleted become. In contrast, the EEPROM can be programmed electrically and deleted become. He stops the stored data via a long time without power and can easily multiple Male programmed and deleted become.

Of the Contains EEPROM a plurality of memory cells for storing small parts of Information. There are memory cells for storing only one Bit. Multi-bit memory cells can however, save more than one bit. A means of storing a Bits has two states on. Which represents a state a logical zero. The other state represents a logical one.

A embodiment a one-bit memory cell comprises a transistor body with a cell tray. The cell well comprises two doping regions. A channel region is located between the doping regions. A gate electrode is over the channel region arranged through a dielectric layer is isolated. The dielectric layer is between the channel region and the gate electrode.

The Cell tray is formed by implanting ions into the substrate. The doping regions are formed by implanting ions in another Step trained. The type of dopant ions used to form the doping ranges used is different from the Type of dopant ions used to form the cell sump.

one the doping regions serve as source and the other serves as Drain. A read voltage is applied to drain with source grounded. If the reading voltage exceeds a certain threshold voltage, flows a stream. In accordance with the respective state, which is either a logical one or represent a logical zero should, the threshold voltage is changed. It is either higher or higher lower than the reading voltage. An alternative memory cell, based on this structure is described below.

A nonvolatile Memory cell comprises a transistor body as described above with a gate electrode over a dielectric is arranged. The dielectric comprises a first oxide layer, a nitride layer and a second oxide layer. The nitride layer serves as a charge trapping layer for electrons. When a positive gate voltage is applied, electrons can escape from the substrate through the thin one Tunnel oxide layer in the nitride layer, where they then remain. The trapped negative charge increases the threshold voltage of the Transistor. In similar Way, the threshold voltage may be due to a negative voltage at the gate be reduced, causing the electrons from the nitride layer be removed.

When the read voltage is applied, either a current flows or not, depending on the threshold voltage. The two states of the memory cell correspond to a switch which is either low mad or not conductive.

A similar Memory cell, however, which also has a charge trapping layer of silicon nitride between the channel region and the gate electrode is to this effect designed to store two bits. Such a memory cell is used as a programmable NROM memory cell (nitride read only memory - NROM) designated.

The programmable NROM memory cell is disclosed in U.S. Patent No. 6,011,725 and Boaz Eitan and others: "NROM: A Novel Localized Trapping, 2-bit Nonvolatile Memory Cell ", IEEE Electron Device Letters, Vol. 21, No. 11, November 2000.

The Oxide-nitride-oxide layer of the NROM memory cell comprises a nitride layer, as a charge trapping layer embedded between insulating oxide layers, creating a Diffusion of embedded electrons in the vertical direction avoided becomes. two single bits are in physically different areas the nitride layer stored. A first bit area is located near of the first doping region and a second bit region close by of the second doping region. S.T.Kang and others: "A Study of SONOS Nonvolatile Memory Cell Controlled Structurally by Localizing Charge Trapping Layer ", Proceedings of IEEE Nonvolatile Memory Workshop, Monterey, 2003 describes an alternative embodiment of an NROM memory cell with two spatially separated ONO layers.

One Memory cell array includes a plurality of memory cells, the are arranged as a matrix with rows and columns. The rows of the memory cell array are parallel to a first direction arranged. The columns of the memory cell array are parallel to a second direction orthogonal to the first direction runs. The first and second doping regions of the memory cell in one Columns are arranged in one direction parallel to the second Direction runs.

The Gate electrodes arranged parallel to the first direction are connected to wordlines. A bit line connects the doping regions arranged parallel to the second direction are. The bit line includes source and drain of the memory cells, extending to both sides of the Bit line are located.

The Bits are programmed by so-called "hot electrons." The Electrons become out of the channel according to the applied voltages into the cargo catcher area injected. The programming of a first bit is done by applying a programming voltage to the first doping region and the Gate performed, wherein the second doping region is grounded. The electrons become injected and in the first bit area adjacent to the first doping region adjoins, stored. In similar Way, the programming of a second bit is performed by the application of a programming voltage to the second doping region and the gate, wherein the first doping region is grounded. The Electrons are injected and stored in the second bit area.

To the Clear of a bit so-called "hot holes" or a Fowler Nordheim tunneling used become. The deleting the first bit is performed by erasing voltages applied to the gate or to the first doping region and the gate which leads to a lateral field. This conditional holes flow through the lower oxide layer and compensate for the charge of the electrons.

A Bit information is read by an opposite voltage between the first and second doping regions in comparison to Programming voltage is applied to the programming of the bit is used. Relatively small stored charges in the Near the grounded doping region prevent or reduce the current flow. For example, reading the first bit by applying a Read voltage to the second doping region and to the gate. Of the first doping region is grounded. The current flows when no charges are stored in the first bit area. If in the first bit area charges are stored, the current flow reduced or the current flows Not.

The first and second bits of each memory cell can be programmed, read and deleted are created by respectively applying a program, read and erase voltage to the bitlines and the wordline associated with the respective ones Memory cell are connected.

A conventional NROM memory cell as described above comprises a Oxide-nitride-oxide layer under the gate with two different areas for storing the charges containing the first and second bit information represent. Consequently, the injection of electrons or holes to change a Bit information affect the other bit. The influence of the residual charges in one Area of the nitride layer adjacent to the bit line, can be negligible be. An unintentional injection into the nitride layer over the Channel area conventional NROM memory cells can not be avoided.

The local Propagation of electrons in the charge trapping region is greater than in holes, there is mobility of electrons and holes in nitride differs. holes are much more mobile. The same number of holes is over a larger area distributed as the corresponding number of electrons. Not next to Each electron is adjoined by a hole, with which the charge of the electron is directly compensated. Holes that are over one wider area than the electrons extend, serve to to cover the charge of the electrons. To a bit information to change, which is represented by embedded electrons, become more holes injected as electrons to cover the charge of the electrons. While another programming step will become more electrons again into the cargo catcher area injected, creating more holes required to charge during the following erase cycle to compensate. This aging process leads to an increase of erase voltages and the programming and erasing processes need more time.

The increased mobility the holes, which represent one bit information, affects the charges that represent the other bit, and lead to a charge loss, possibly associated with a loss of information.

It It is an object of the invention to provide an NROM memory cell, in the aging process due to the different degrees of mobility of electrons and holes do not occur.

The Task is by a semiconductor circuit arrangement for training a memory cell according to the sibling Claim 1 solved. The Semiconductor circuit arrangement comprises a transistor body with an upper surface and a first doping region and a second doping region and a channel region between the first doping region and the second doping region. Furthermore includes the semiconductor circuitry has a gate dielectric extending above the upper surface of the transistor body located, as well as a gate electrode, which is located above the channel area is. The gate electrode is arranged on the gate dielectric in such a way that that the gate dielectric between the gate electrode and the upper surface of the transistor body located. The arrangement further comprises an oxide-nitride-oxide layer with first Sections each having a bottom surface and second sections, each a lower surface exhibit. The first portions of the oxide-nitride-oxide layer are over the first and second doping regions arranged. The lower surfaces The first portions of the oxide-nitride-oxide layer are substantially parallel to the upper surface of the transistor body. The lower surfaces the second portions of the oxide-nitride-oxide layer are the gate electrode adjacent and extending in a direction that is substantially not parallel to the upper surface of the transistor body.

Of Another is a method for producing the semiconductor circuit arrangement according to the invention indicated for forming a memory cell.

advantageously, touch the lower surfaces the first sections of the oxide-nitride-oxide layer the surface of the The transistor body, and the bottom surfaces the second portions of the oxide-nitride-oxide layer touch the sidewalls of the Gate electrode, so that they are perpendicular to the first sections of the Oxide-nitride-oxide layer are arranged. This creates two separate areas for the storage of one bit each.

by virtue of The shape of the oxide-nitride-oxide layer are corner portions of the intervening ones Nitride layer present at the first or second doping region and the gate electrode are adjacent. On both sides of the gate electrode There is a corner area serving as a charge trapping area.

The Inventive memory cell allows a very good two-bit separation, since there is no direct nitride connection between the areas for storing a bit there. by virtue of the L-shaped Oxide-nitride-oxide layer is for an advantageous orientation of charge carriers ensured. The charge carriers are intercepted in the border area. The spatial Extension of the area within the channel area or under the Gate electrode, in which the charge carriers, especially holes, is stored, is reduced.

The Gate electrode comprises polysilicon whereas the gate dielectric comprises silicon dioxide or silica. Thereby, the gate conductive electrode becomes through the gate dielectric isolated. For doping the channel region is either boron or Indium related, for doping the first and second doping regions Arsenic is used, so that an n-channel is formed, which in the Compared to a p-channel to a faster programming and deletability the memory cell leads.

Advantageously, the memory cells are arranged in a field having rows and columns. The memory cells are all in the same Way aligned. This arrangement facilitates the control of the individual memory cells.

to Isolation of the individual memory cells is their gate electrode by a Nitride distance range isolated. The penetration between the memory cells is avoided by a so-called anti-penetration doping, which is arranged between the memory cells.

Between the columns of the matrix-shaped arranged gate electrodes In the field are bitlines extending below the upper surface of the Substrate are buried. By means of these bit lines are the memory cells programmable. The bit lines are through an overlying Oxid lead isolated. Orthogonal to the bit line extend wordlines, the the gate electrodes connect in a row so that by an appropriate choice of Bit lines and a word line a single memory cell programmable is. The word lines are usually made of polysilicon, metal or metal silicide, preferably tungsten silicide.

The inventive method for manufacturing such a semiconductor circuit arrangement providing a semiconductor substrate having a top surface Applying an oxide layer to the substrate, an introduction of Doping substances for the formation of a tub and an application a conductive layer on the oxide layer. Furthermore includes the substrate the partial etching the conductive layer and the oxide layer for forming gate islands, causing the upper surface of the semiconductor substrate is exposed. On the exposed upper surface of the semiconductor substrate and the upper surface and side walls of the Gate islands, an oxide-nitride-oxide layer is applied. The oxide-nitride-oxide layer has a typical L-shape according to the invention.

alternative can the dopants even after the application of the oxide layer in the substrate are introduced.

Around avoid penetration between adjacent gate electrodes can suitable dopants are introduced therebetween.

A Development of the method comprises the application of a nitride layer on the oxide-nitride-oxide layer for forming horizontal and vertical sections of the nitride layer. The horizontal sections are etched, so that around the gate electrodes a vertical nitride spacer remains for isolation serves.

The distances the gate electrodes are chosen that after the step just mentioned, there are trenches between the columns whereas this is not the case with the rows. In these trenches will be Dopants introduced to the first and second doping regions form in the form of bit lines. These are in usually arsenic dopants, to form an n-channel.

advantageously, The process serves to create multiple gate islands along rows and columns are arranged for to form a memory cell array.

On the bit lines are applied an oxide line for their isolation. Orthogonal to the oxide lines run wordlines, with which the gate islands, which are arranged in a row, electrically are connected. For the word lines become polysilicon, metal or metal silicide, In particular, tungsten silicide used to have good electrical properties to reach.

following the invention with reference to the drawing based on embodiments explained.

It demonstrate:

1 shows a cross-section of an intermediate product of a preferred manufacturing method after introduction of dopant ions and the application of an oxide layer on a semiconductor substrate;

2 shows a cross section of the intermediate according to 1 with a polysilicon layer on the surface of the oxide layer;

3 shows a cross section of the intermediate according to 2 after etching gate islands;

4 shows an intermediate product of the preferred method in plan view;

5 shows a cross section of the intermediate according to 3 which is coated by an oxide-nitride-oxide layer;

6 shows a cross section of the intermediate according to 5 along an in 4 shown line AA 'after the application of a nitride layer;

7 shows a cross section of an intermediate according to 6 along an in 4 shown line BB ';

8th shows a cross section of the intermediate according to 6 after severe overetching to remove horizontal portions of the nitride layer and the underlying oxide-nitride-oxide layer;

9 shows a cross section of the intermediate according to 7 after severe overetching to remove horizontal portions of the nitride layer and the underlying oxide-nitride-oxide layer;

10 shows a cross section of the intermediate according to 8th after introducing doping ions to form a bit line;

11 shows a cross section of the intermediate according to 10 after applying an oxide line over the bit line;

12 shows a cross section of the intermediate according to 11 after etching a residual oxide layer from an upper side of the gate island;

13 shows a cross section of the intermediate according to 12 after applying a wordline;

14 shows the structure of the memory cell array in the plan view and

15 shows a cross section of the memory cell structure according to the invention.

in the The following are preferred embodiments explained in detail. The explained specific embodiments are only illustrative of special ways The invention is intended to be implemented and used, and limits the scope of the invention not a.

A manufacturing process for semiconductor circuitry includes a plurality of steps of forming patterned layers on or in a substrate, which is generally monocrystalline silicon. A manufacturing process of an embodiment of a memory cell according to the invention will be described below with reference to FIGS 1 to 14 described. These figures show cross-sections and plan views of a small range of semiconductor device interconnect devices.

1 shows a cross section of a portion of an intermediate product of the semiconductor circuit arrangement. A semiconductor substrate 1 (eg silicon) is provided. An upper surface 111 of the semiconductor substrate 1 is through an oxide layer 2 covered. The thickness of the oxide layer 2 is preferably in the range of about 5 nm to 30 nm. In particular, the step of applying the oxide layer comprises 2 generally a thermal oxidation to form the oxide layer 2 (eg silica) on the substrate 1 ,

The following step involves forming a cell tray 100 by introducing doping ions, resulting in a homogeneous doping of an upper region of the semiconductor substrate 1 leads. The dopant ions pass through the oxide layer 2 implanted. In a preferred embodiment of the invention, p-type impurities such as boron or indium ions are used as doping ions.

It is also possible to use the dopant ions in the semiconductor substrate 1 before the step of applying the oxide layer 2 to implant. When using this sequence of process steps, the oxidation process can alter the doping. As a result, the concentration of dopant ions in the cell sump can 100 become inhomogeneous.

2 shows a cross section according to 1 after a further process step. A polysilicon layer 3 gets onto the oxide layer 2 applied. The polysilicon layer 3 and the cell tray 100 are from the polysilicon layer 3 through the oxide layer 2 isolated.

3 shows the area according to 2 after a further process step.

In general, a memory unit comprises a plurality of memory cells arranged in a field, each memory cell comprising a gate electrode 3a having. As a result, a plurality of gate islands 4 formed according to the arrangement of the memory cells during an etching process.

Parts of the polysilicon layer 3 and the oxide layer 2 which lies below are etched to the gate island 4 train. The gate island 4 includes a gate electrode 3a and an insulating gate dielectric 2a , The upper surface 112 of the semiconductor substrate 1 is exposed by the etching process. For example, a typical etching process includes the steps of forming a mask on the top surface of the polysilicon layer 3 form, the etching relative to the mask and the removal of the mask.

4 shows a plan view of the gate islands 4 , The gate islands 4 are arranged as a field that has rows and columns. The rows of the gate islands 4 lie parallel to a first direction 301 , The columns of the gate islands 4 lie parallel to a second direction 302 leading to the first direction 301 orthogonal runs.

The distance between adjacent rows of gate islands 4 is smaller than the distance from adjacent columns of gate islands 4 because, in a further step, which will be described below, bit lines are formed between them. As a result, further process steps result in different structures along the first and second directions 301 . 302 , The respective structures are shown in the following figures. The 6 . 8th and 10 to 13 show cross-sections of memory cells arranged along a line between A and A 'which are parallel to the first direction 301 runs. The 7 and 9 show cross-sections of memory cells arranged along a line between B and B 'parallel to the second direction 302 runs.

5 shows the area according to 3 after a further process step. An oxide-nitride-oxide (ONO) layer 66 is on the exposed surface 112 of the semiconductor substrate 1 as well as the upper surface and sidewalls of the gate islands 5 applied. The ONO layer 66 includes a nitride layer 6 (eg, silicon nitride) sandwiched between an upper oxide layer 7 (eg, silica) and a lower oxide layer 5 (eg silica) is embedded. Instead of a nitride layer, any non-conductive charge trapping material may be used. This process step leads to the shape of the ONO layer 66 according to the invention, the horizontal sections 661 on top of the gate islands 4 and in between, as well as vertical sections 662 which is on the side walls 33 the gate islands 4 are arranged.

An optional step includes the insertion of dopant ions to form a dopant, in particular an implant 80 with anti-punch through features that act as a diffusion barrier and to insulate the gate electrodes 3a serves. The implantation 80 is introduced into the substrate through the ONO layer. The dopant ions are not capable of the gate islands 4 to penetrate, resulting in a lack of anti-penetration implantation 80 below the gate islands 4 leads. Preferably, indium ions are used. Indium ions are larger and less mobile than boron ions. As a result, the diffusion of the implanted ions is reduced during further steps, particularly those associated with an elevated temperature used to activate implantation. Although the anti-penetration implantation 80 between the rows and the columns of the gate islands 4 In particular, it is used to form contiguous rows of gate electrodes 3a to isolate, because the distance between those smaller than the distance between adjacent columns of gate electrodes 3a is.

6 shows an area according to 5 and along the line AA ', which is parallel to the first direction 301 runs, after a further process step. A nitride layer 88 will be on the ONO layer 66 applied, with horizontal sections 88a and vertical sections 88b be formed. The vertical sections 88b the nitride layer 88 form side walls of trenches 40 out, located between neighboring gate islands 4 are located. The horizontal sections 88a the nitride layer 88 between the gate islands 4 lying, forming the lower walls of the trenches 40 ,

7 shows an area along the line BB 'parallel to the second direction 302 aligned, after the same process step. The distance of the gate islands 4 which are arranged along the line BB 'is smaller than along the line AA'.

The nitride layer 88 will be on the ONO layer 66 applied. The thickness of the nitride layer 88 is precisely adapted to the entire space between the neighboring gate islands 4 to fill. The cross section of the nitride layer 88 looks comb-shaped with horizontal sections 88a over the upper surface of the gate islands 4 and intermediate vertical sections 88b , Between adjacent gate islands 4 located along the line BB ', no trenches are present. Due to the difference between the pitch of columns and the spacing of rows of gate islands 4 lie trenches 40 only parallel to the second direction 302 in front.

The vertical sections 88b the nitride layer 88 serve as a means to the gate islands 4 to insulate the respective memory cells and to stop the diffusion of the implanted ions. The distance between the gate islands 4 must be adjusted carefully. On the one hand, the distance between the gate islands 4 be small. On the other hand, the thickness of the nitride layer 88 covering the entire space between adjacent rows of gate islands 4 fills, be able to considerably reduce the diffusion of dopant ions and the gate electrodes 3a to isolate.

8th shows one to the first direction 301 parallel area according to 6 after a further process step, which includes a strong over-etching, around the horizontal sections 88b the nitride layer 88 and the underlying ONO layer 66 to remove. The upper surface of the gate island 4 will be exposed. The horizontal nitride layer 88b and the ONO layer 66 that under the surface of the lower wall of the trench 40 lies, be removed, resulting in a gap 9 leads. The gap 9 separates the horizontal sections 661 the ONO layer 66 between two adjacent gate islands 3a , The vertical sections 88b the nitride layer 88 stay, um a nitride distance range 8th train.

9 shows an area along the second direction 302 according to 7 after the same process step. The completely filled space between the adjacent gate islands 4 remains at a nitride distance range 8th formed as a means for isolating adjacent gate electrodes 3a serves. The etching process only removes layers on top of the gate islands 4 ,

10 shows an area according to 8th after a further process step. Doping ions are going through the gap 9 introduced to a bit line 10 train. The bit line 10 is under the gap 9 and adjacent sections of the ONO layer 66 arranged. The bit line 10 runs parallel to the first direction 301 and between adjacent columns of the gate islands 4 ,

It is not possible to have doping ions between adjacent rows of the gate islands 4 in the substrate 1 because of the nitride distance range 8th fill in the entire space in between, as in 9 shown. The dopant ions are from the nitride spacer regions 8th stopped.

A channel area 110 is located under the gate electrode 3a and between two bit lines 10 , The channel area 110 has the same doping as the cell well 100 , Horizontal sections 661 the L-shaped ONO layer 66 are above the bit line 10 , The corner 507 the L-shaped ONO layer 66 , especially the corner 606 the nitride layer 6 , is preferably located above a transition zone 120 that is between the bit line 10 and the channel area 110 lies.

The preferred embodiment of the invention comprises arsenic ions for doping. The combination of boron or indium ions for a cell sump 100 and arsenic or another element of column IV in the Periodic Table of Elements (eg, phosphorus) results in an n-channel. An n-channel is preferred to a p-channel because the electrons move faster than the holes, resulting in a faster memory cell programming and erasing process.

To In the implantation, the semiconductor circuit arrangement is placed on a Temperature of about 1050 ° C heated to activate the implantation.

11 shows an area according to 10 after a further process step. An oxide line gets in the gap 9 over the bit line 10 applied. The oxide line 11 separates the ONO layer 66 and isolates the bit line 10 , Due to the oxidation process becomes a thin residual oxide layer 12 on the upper surface of the gate islands 4 applied.

12 shows the area according to 11 after a further process step. The residual oxide layer 12 on the upper surface of the gate islands 4 is etched. Due to the etching process, an upper portion of the oxide line becomes 11 Etched and adjacent areas of the nitride spacer are also etched laterally. The insulation is not affected by the etching process due to the thickness of the oxide line 11 and the nitride distance range 8th ,

13 shows the area according to 12 after a further process step. A wordline 13 is formed by applying polysilicon with tungsten silicide. Alternatively, other metals or metal silicides are used. The word line 13 comes with the gate electrodes 3a connected. Polysilicon with tungsten silicide conducts better than pure polysilicon. Other silicides such as titanium silicide, cobalt silicide or nickel silicide may alternatively be used. Nevertheless, the gate electrodes contain 3a Polysilicon, compared to the etching process of the gate islands 4 is more robust. The semiconductor region is covered by a capping nitride layer 14 covered for protection.

14 shows a plan view of the memory cell according to 4 after further process steps which have been described above. Vertical sections of the ONO layer 66 are located on the side walls of the gate islands 4 , The nitride distance range 8th is located on the vertical sections 662 the ONO layer 66 , which sidewalls of the trenches 40 train parallel to the second direction 302 are arranged. The oxide lines 11 over the bitlines 10 lie between adjacent columns of the gate islands 4 ,

The Write, delete or reading each memory cell is performed by the corresponding ones Driving voltages applied to the bit lines and the word line which are connected to the respective memory cell.

The Describe preferred production steps described above also a preferred embodiment the memory cell according to the invention.

Another step, not shown here, involves inserting a metal contact into the buried bit line 10 without going to the gate electrode 3a to make a connection. A step of adjusting the position of the metal contact is facilitated by the thickness of the nitride insulating spacer region 8th that is around the gate electrode 3a located.

15 shows a cross section of a memory cell array 160 with rows and columns. The cross section of memory cells 160 , which are arranged in the series, takes place according to the line AA '(see 14 ), which are parallel to the first direction 301 is aligned. A memory cell 160 and parts of memory cells adjacent to both sides 160 are shown.

The memory cell 160 includes a transistor body 150 with an upper surface 111 , Under the upper surface 111 there is a cell tray 100 containing a first doping region 10a and a second doping region 10b with an intermediate channel area 110 includes. A gate electrode 3a is over the channel area 110 arranged and by a gate dielectric 2a separated. The gate dielectric 2a includes, for example, silicon dioxide. A bit line 10 connects the first doping regions 10a or the second doping regions 10b which are arranged in a column parallel to the second direction 302 runs. Only the first and second doping regions become 10a . 10b represented as the bit lines 10 are aligned normal to the cross section. The above-described optional anti-punch-through implantation 80 is also in 15 shown. It is located below the upper surface 111 between the gate islands 4 , below and around the first and second doping regions 10a . 10b ,

An oxide-nitride-oxide (ONO) layer 66 is above the upper surface 111 of the transistor body 150 and the side walls 33 the gate electrode 3a arranged. The ONO layer 66 includes a nitride layer 6 that is between an upper oxide layer 7 and a lower oxide layer 5 is embedded. The nitride layer 6 includes, for example, silicon nitride. Instead of silicon nitride, any non-conductive charge trapping material can be used.

The ONO layer 66 includes first sections 661 and second sections 662 , The first sections 661 the ONO layer 66 are substantially parallel to the upper surface 111 of the transistor body 150 , The lower surfaces 51 the first sections 661 the ONO layer 66 are located on the upper surface 111 of the transistor body 150 in contact. The second sections 662 the ONO layer 66 borders to the gate island 4 and extend in a direction that is substantially non-parallel to the top surface 111 of the transistor body 150 is. In particular, the second sections 662 the ONO layer 66 essentially vertical to the upper surface 111 of the transistor body 150 , The lower surfaces 52 the second sections 662 the ONO layer 66 are with side walls 33 the gate island 4 in contact.

The L-shaped ONO layer 66 includes a corner region of the nitride layer 6 which is preferably above a transition zone 120 located between one of the first and second doping regions 10a . 10b and the channel area 110 located. The corner area serves as a charge trapping region of the memory cell 160 , There are charge trapping regions C1, C2 on both sides of the gate island 4 , There is no direct nitride connection between the charge collector regions C1, C2 of a memory cell 160 available.

The first sections 661 the ONO layer 66 are located above the first and second doping regions 10a . 10b , They are going through the oxide line 11 disconnected over the bit line 10 located.

The L-shaped ONO layer 66 has an upper surface 77 which is covered by a nitride layer having a vertical nitride pitch region 8th which acts as a means of isolating adjacent gate electrodes 3a serves.

A wordline 13 connects the gate electrodes 3a arranged in a row. The semiconductor region is through a capping nitride layer 14 covered for protection.

For programming, reading or erasing a memory cell 160 need the appropriate drive voltages to the bitlines 10 and the wordline 13 be created with the respective memory cell 160 are connected. The method of programming a first bit and a second bit and clearing and reading the respective bits has already been described in the prior art section. Special features of the memory cell according to the invention 160 in terms of programming, reading and deleting are described below.

One of the first and second doping regions 10a . 10b serves as a drain, and the other serves as a source. To program a first bit, programming voltages are applied to the bit line 10 created, which is the first doping region 10a and the wordline 13 connects to the gate electrode 3a the respec gene memory cell 160 connected is. The bit line 10 connected to the second doping region 10b connected is grounded. As a result, electrons are injected into the first charge trapping region C1, which is the first doping region 10a is adjacent.

Similarly, application of corresponding programming voltages results in the second doping region 10b and the gate electrode 3a in that electrons are introduced into the second charge catcher region C2, which is the second th doping range 10b is adjacent.

The Read and delete of the first and second bits includes the steps included in the section have been described to the prior art.

Due to the separation of the first and second charge trapping regions C1, C2, the interactions that occur during reading, programming or erasing are alleviated. Due to the missing nitride layer under the gate electrode 3a Charges, especially holes, can not enter the channel area 110 move, which is under the gate electrode 3a located. Therefore, a spontaneous injection into the ONO layer 66 unlikely. Residual charges in the nitride layer 6 , especially holes, move up, which means that they hardly affect the memory cell.

The Inventive memory cell and the corresponding memory cell array provide for an advantageous Alignment of the charge carriers in the oxide-nitride-oxide layer, eliminating the problem of different mobility Grade of electrons and holes is mitigated in nitride.

1

substratum

100

cell tray

111

upper surface

112

exposed upper surface

2

oxide

3

Polysilicon layer

2a

Gate dielectric

3a

Gate electrode

4

Gate Island

33

Sidewalls of the Gate Island

5

lower oxide

6

nitride

7

upper oxide

66

Oxide-nitride-oxide layer

661

horizontal Sections of the oxide-nitride-oxide layer

662

vertical Sections of the oxide-nitride-oxide layer

51

lower surface the horizontal sections of the oxide

Nitride-oxide layer

52

lower surface the vertical sections of the oxide

Nitride-oxide layer

77

upper surface the oxide-nitride-oxide layer

507

corner the oxide-nitride-oxide layer

606

corner the nitride layer

8th

Nitride spacer region

88

nitride

88a

horizontal Section of the nitride layer

88b

vertical Section of the nitride layer

9

gap

10

bit

10a

first doping region

10b

second doping region

110

channel area

120

Transition zone

11

Oxidleitung

12

Residual oxide layer

13

wordline

14

Capping nitride layer

40

dig

80

Anti-penetration implantation

150

transistor body

160

memory cell

301

first direction

302

second direction

C1

first Charge trapping area

C2

second Charge trapping area

Claims (32)

Semiconductor circuit arrangement for forming a memory cell, comprising: a transistor body ( 150 ) with an upper surface ( 111 ), and a first doping region ( 10a ) and a second doping region ( 10b ) as well as a channel area ( 110 ) between the first doping region ( 10a ) and the second doping region ( 10b ) is arranged; A gate dielectric ( 2a ) located above the upper surface ( 111 ) of the transistor body ( 150 ) is located; A gate electrode ( 3a ) above the channel area ( 110 ) and on the gate dielectric ( 2a ) is arranged such that the gate dielectric ( 2a ) between the gate electrode ( 3a ) and the upper surface ( 111 ) of the transistor body ( 150 ) is located; and an oxide-nitride-oxide layer ( 66 ) with first sections ( 661 ), each having a lower surface ( 51 ), and second sections ( 662 ), each having a lower surface ( 52 ) exhibit; the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ) over the first and second doping regions ( 10a . 10b ), and the lower surfaces ( 51 ) of the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ) substantially parallel to the upper surface ( 111 ) of the transistor body ( 150 ) and the lower surfaces ( 51 ) of the second sections ( 662 ) of the oxide-nitride-oxide layer ( 66 ) to the gate electrode ( 3a ) are adjacent and extend in a direction substantially non-parallel to the upper surface (FIG. 111 ) of the transistor body ( 150 ) runs. Semiconductor circuit arrangement according to claim 1, characterized in that the second Sections ( 662 ) of the oxide-nitride-oxide layer ( 66 ) are substantially orthogonal to the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ). Semiconductor circuit arrangement according to Claim 1, characterized in that the lower surfaces ( 51 ) of the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ) the upper surface ( 111 ) of the transistor body ( 150 ), and that the lower surfaces ( 52 ) of the second sections ( 662 ) of the oxide-nitride-oxide layer ( 66 ) Side walls ( 33 ) of the gate electrode ( 3a ) touch. Semiconductor circuit arrangement according to Claim 1, characterized in that the gate electrode ( 3a ) is formed with polysilicon. Semiconductor circuit arrangement according to Claim 1, characterized in that the gate dielectric ( 2a ) is formed with silicon dioxide or silicon oxide. Semiconductor circuit arrangement according to Claim 1, characterized in that the channel region ( 110 ) is doped with a dopant containing either boron and / or indium, and wherein the first and second doping regions ( 10a . 10b ) are doped with arsenic. Semiconductor circuit arrangement according to one of the preceding claims, comprising a multiplicity of memory cells ( 160 ) arranged in a matrix with columns and rows, the rows being in a first direction (FIG. 301 ) and the columns in a second direction ( 302 ), which in turn are directed to the first direction ( 301 ) is orthogonal. Semiconductor circuit arrangement according to Claim 7, characterized in that the first and second doping regions ( 10a . 10b ) of the memory cells ( 160 ) arranged in a row along a direction to the first ( 301 ) are aligned parallel line. Semiconductor circuit arrangement according to Claim 7, characterized in that a bit line ( 10 ) which is parallel to the second direction ( 302 ) and the at least two adjoining doping regions ( 10a . 10b ) electrically connected in parallel to the second direction ( 302 ) are arranged. A semiconductor circuit arrangement according to any one of claims 1 to 6, comprising: - a substrate ( 1 ) with an upper surface ( 111 ); A plurality of gate electrodes ( 3a ), which are on the upper surface ( 111 ) of the substrate ( 1 ), wherein the gate electrodes ( 3a ) are arranged in a field, with rows parallel to a first direction ( 301 ) and columns parallel to a second direction ( 302 ) leading to the first direction ( 301 ) is orthogonal; A plurality of gate dielectrics ( 2a ), wherein one of the plurality of gate dielectrics ( 2a ) between one of the plurality of gate electrodes ( 3a ) and the upper surface ( 111 ) of the substrate ( 1 ) is arranged; At least two bit lines ( 10 ) running along the second direction ( 302 ) on both sides of a column of gate electrodes ( 3a ), wherein the bit lines ( 10 ) under the upper surface ( 111 ) of the substrate ( 1 ) are buried; A channel area ( 110 ) contained in the substrate ( 1 ) between the bit lines ( 10 ) and under one of the gate electrodes ( 3a ), and wherein the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ) over the bitlines ( 10 ) and the lower surfaces ( 52 ) of the second sections ( 662 ) of the oxide-nitride-oxide layer ( 66 ) to the gate electrode ( 3a ). Semiconductor circuit arrangement according to one of Claims 7 to 10, characterized in that a nitride spacing region ( 8th ) vertical to the upper surface ( 111 ) of the transistor body ( 150 ) or vertically to the upper surface ( 111 ) of the substrate ( 1 ) on the side walls ( 33 ) of the gate electrode ( 3a ) is arranged. Semiconductor circuit arrangement according to one of Claims 7 to 11, characterized in that dopants ( 80 ) with anti-punch through features between adjacent rows of gate electrodes ( 3a ) are arranged and parallel to the first direction ( 30 ), the dopants ( 80 ) below the upper surface ( 111 ) of the transistor body ( 150 ) or below the upper surface ( 111 ) of the substrate ( 1 ) are located. Semiconductor circuit arrangement according to one of Claims 7 to 12, characterized in that an oxide line ( 11 ) on the bit line ( 10 ) and the oxide line ( 11 ) between the first sections ( 661 ) of the oxide-nitride-oxide layer ( 66 ) is arranged. Semiconductor circuit arrangement according to one of Claims 7 to 12, characterized in that a word line ( 13 ) electrically with at least two of the gate electrodes ( 3a ), which in turn are arranged in the same row. Semiconductor circuit arrangement according to Claim 14, characterized in that the word line ( 13 ) is formed with one or more materials from the group polysilicon, metal and metal silicide. Semiconductor circuit arrangement according to Claim 15, characterized in that the word line ( 13 ) is formed with tungsten silicide. A method for producing a semiconductor circuit arrangement comprising the steps of: providing a semiconductor substrate ( 1 ) with an upper surface ( 111 ); - Application of an oxide layer ( 2 ) on the semiconductor substrate ( 1 ); Introducing dopants into the substrate such that a well ( 100 ) is formed; - applying a conductive layer ( 3 ) on the oxide layer ( 2 ); Partial etching of the conductive layer ( 3 ) and the oxide layer ( 2 ) for forming a gate island ( 4 ), whereby the upper surface ( 112 ) of the semiconductor substrate ( 1 ) and - application of an oxide-nitride-oxide layer ( 66 ) on the exposed upper surface ( 112 ) of the semiconductor substrate ( 1 ) and the upper surface and side walls ( 33 ) of the gate island ( 4 ). A method according to claim 17, characterized in that the application of a conductive layer ( 3 ) comprises applying a polysilicon layer. A method according to claim 17, characterized in that the step of introducing the dopants before the step of applying the oxide layer ( 2 ) is carried out. The method of claim 17, further comprising introducing dopants into the substrate ( 1 ) to a doped area ( 80 ) formed between the gate island ( 4 ) and an adjacent second gate island ( 4 ), the gate island ( 4 ) and the second gate island ( 4 ) along a second direction ( 302 ) are arranged. Method according to claim 20, characterized in that the dopant has anti-punch through features. The method of claim 17, further comprising - applying a nitride layer to the oxide-nitride-oxide layer ( 88 ) for forming horizontal and vertical sections ( 88a . 88b ) of the nitride layer ( 88 ) and - etching the horizontal sections ( 88a ) of the nitride layer ( 88 ) and the oxide-nitride-oxide layer ( 661 ), which are below the horizontal sections ( 88a ) of the nitride layer ( 88 ) to form a nitride spacer region ( 8th ) train. The method of claim 22, further comprising introducing dopants on both sides of the gate island ( 4 ) to a first doping region and a second doping region ( 10a . 10b ) train. A method according to claim 23, characterized in that the introduction of dopants for forming the trough ( 100 ) comprises introducing one of boron and / or indium dopants, and in that the introduction of dopants for forming the first doping region ( 10a ) and the second doping region ( 10b ) comprises introducing arsenic dopants. Method according to claim 22, characterized in that several gate islands ( 4 ) are arranged along a row, and several gate islands ( 4 ) are arranged along a column, wherein the rows are parallel to a first direction ( 301 ) are arranged, and the columns parallel to a second direction ( 302 ), to the first direction ( 301 ) are arranged orthogonally. Method according to claim 25, characterized in that the step of etching horizontal sections ( 88a ) of the nitride layer ( 88 ) a gap ( 9 ) which is parallel to the second direction ( 302 ) between adjacent columns of gate islands ( 4 ) lies. A method according to claim 26, comprising a step of introducing dopants through the gap ( 9 ) in the tub ( 100 ) to a bit line ( 10 ) train. The method of claim 27, further comprising forming an oxide line ( 11 ) in the gap ( 9 ) and above the bit line ( 10 ). The method of claim 28, further comprising forming a wordline ( 13 ) electrically connected to at least two of the gate islands ( 4 ), which are arranged in the same row. Method according to claim 29, characterized that the word line with one or more materials from the Group polysilicon, metal and metal silicide is formed. Method according to claim 30, characterized in that the formation of a word line ( 3 ) comprises applying polysilicon and forming a silicide over the polysilicon. Method according to claim 31, characterized in that the word line ( 13 ) is formed with tungsten silicide.