DE10135775A1 - Fuse programming testing method determines resistance between fuse cover and anode or cathode of programmable fuse bridge - Google Patents

Abstract

The testing method determines the resistance between the conductive cover (14) for the programmable fuse bridge (12) and the anode (A) and/or cathode (K) of the fuse bridge. A read-out current can be applied to the anode and 2 different potentials applied to the cover in succession, with measurement of the voltage between the anode and the cathode. Also included are Independent claims for the following: (a) a test circuit for a programmable fuse; (b) a method for read-out of the programming of a programmable fuse; (c) a read-out circuit for a programmable fuse; (d) a fuse cellwith a programmable fuse; (e) a fuse cell matrix

Description

The invention relates to a method for checking the Programming a cavity fuse according to the generic term of Claim 1, a test circuit according to the preamble of Claim 5, a method for reading out the programming a cavity fuse according to the preamble of claim 10, a Reading circuit for a cavity fuse according to the generic term of Claim 15, a fuse cell according to the preamble of claim 18 and a fuse matrix according to claim 20.

For one-time programming of an integrated Circuit or an IC (Integrated Circuit) are in Cases that require high reliability, such as in particular in the automotive field of application, often so-called Cavity fuses used. Such cavity fuses are also referred to as fusible links.

Generally, under a fuse in the Semiconductor technology and circuit technology one Fuse understood that permanent on a binary Value can be programmed. With a cavity fuse for example a polysilicon bridge through a strong one Programming impulse melted. The height The reliability of this programming method stems from the fact that the melting of the bridge on the occasion of programming is irreversible.

In contrast to EPROMs (Electrical Programmable Read Only Memories) or EEPROMs (Electrical Erasable and Programmable Read Only Memories), their programming charge yourself u. U volatilize during the life of the device permanent programming is achieved.

Fig. 1 shows a known prior art Hohlraumfuse 10 with a connected read-out circuit. The cavity fuse 10 consists of a (polysilicon) bridge 12 which is arranged between an anode A and a cathode K. The cathode K is at a reference potential. A current is impressed into the anode A via a current mirror. The current mirror consists of the current source IL1 and two p-MOS transistors Q1 and Q2. The source of the p-MOS transistor Q2 is connected to a supply potential VDD; Drain is connected to anode A. Bridge 12 , anode A and cathode K are covered with a cover 14 , which is indicated as an approximately rectangular area with dashed lines. The bridge 12 of the cavity fuse 10 shown has melted, ie the fuse is programmed.

The surface or cover 14 of the cavity, under which the bridge 12 , anode A and cathode K is located, is wholly or partly either non-conductive or conductive; in the latter case, however, at least electrically floating. I.e. this conductive structure is electrically isolated from the rest of the circuit so that charges cannot flow to or from it.

If the fuse is programmed correctly and there is no parasitic conductive path between anode A and cathode K the cavity fuse has formed, the potential is U1 at Anode A identical to the supply potential VDD, since the Transistor Q2 goes into saturation (it cannot read current into the extremely high-resistance fuse).

Aluminum fuses are also state of the art known. These work similarly to the cavity fuses. By a strong programming pulse instead of one Polysilicon bridge a thin aluminum line for melting brought. There is one in comparison to melting Polysilicon bridge extremely high currents in the Range of about 0.5 A is required. This is because the aluminum sheet only through a thin dielectric from Substrate is separated and thus in a very intimate thermal contact to the good heat-conducting silicon. Around nevertheless the necessary temperatures in the foot section too generate a high current must flow.

In addition to programming through cavity fuses is common also uses the so-called zener zapping. Doing so high during programming to a zener diode Voltage is applied so that the diode is short-circuited and then remains low-resistance. This widespread process has the disadvantage that compared to cavity fuses large currents in the range of approximately 200 mA are also necessary are. In circuits in which for protection reasons There is series resistance in the supply line therefore not possible to implement an already implemented, i.e. H. to program built-in integrated circuit (so-called In-circuit programming).

For programming an IC at the slice level, still before mounting in a housing is also used Polysilicon bridges, which are however bombarded with a Lasers can be programmed. Such fuses are therefore considered Denoted laser fuses. However, after installing the ICs can no longer be programmed. So no one can the assembly of the IC caused inaccuracies be calibrated out. It is particularly so with analog ICs but often essential that you have offsets and Temperature responses caused by mechanical tension in the IC or chips in the housing are strongly influenced, after which Trimmed housing assembly.

The cavity fuses differ from the Zener zapping through a much lower one Programming current off: you need a current of only approx. 50 mA, i.e. approx. 25% of the Zener programming current. This low programming current is achieved in that the Polysilicon bridge is not in an immediate thermal Contact with the chip is: It is not like all the others Components in the IC, more precisely its substrate diffused or grown on the surface of the IC, but it is in a cavity. This is that Point that melts when programming, only from relative poorly heat-conducting air and the thermal Little contact with the rest of the IC. This is achieved by the polysilicon fuse on a sacrificial layer (the so-called Sacrificial Layer) is grown. One comes over it another sacrificial layer, which with a kind of cover or Cover is covered. This lid contains holes through it which an acid can dissolve the sacrificial layers. As soon as the Sacrificial layers are completely dissolved, the poly- Fuse like a bridge in the air.

The lid or cover is essentially from an electrically insulating oxide layer and one electrically conductive polysilicon layer. Will the actual fuse link from a first polysilicon layer Made of Poly1, there is the conductive part of the cover from a second polysilicon layer Poly2.

During operation, the logical state becomes a Cavity fuse ("programmed" or "not programmed") determined by a reading current the size of some Micro-ampere is stamped into the fuse. In the programmed Condition is usually the bridge melted, i. H. the conductive path between anode A and cathode K. interrupted.

If the fuse is programmed, then its resistance is very large. In the theoretical ideal case, it is infinitely large, in practice at least larger than a few megohms. In this In this case, the voltage drop across the fuse is practically the same the supply voltage. The power source then goes in Saturation because of its available voltage swing is not sufficient to the reading current through the high-resistance fuse to drive. This can be called logic "HIGH" by a logic be recognized.

If the fuse is not programmed, it is Resistance only about 100 ohms. Then arises from the reading current only a very low voltage of approx. 100 mV at the Fuse what as conventional logic in CMOS technology as "LOW" is recognized.

So for a reliable programming memory the reading current should be chosen so that the voltage at a non-programmed fuse is small enough to be logical "LOW" to be recognized. On the other hand, the reading current must be like this be chosen so that the tension on the fuse according to the Reading current still logically corresponds to "HIGH" if the programmed fuse has "only" a few megohms of resistance.

Under certain conditions it can occur with cavity fuses However, the following reliability problem arises: Will the cavity fuse is programmed, so it melts and evaporates Polysilicon bridge due to the strong energy input in usually within a few microseconds. Because the cavity is almost hermetically sealed, the residual gases can be bad therefore escape and settle on the walls of the cavity low.

In the course of the lifespan of the module, it can especially at high temperatures and high voltages The cavity fuse will come between the two Connections of the cavity fuse forms a conductive path. As a result, the resistance of this path can be relatively low be (for example 100 kOhm), so that when reading the cavity fuse using the method of Reading current may be such a small voltage across the Fuse sets a "LOW" instead of a "HIGH" becomes. This case must be avoided because the Building block thus its programming during the lifetime can lose (i.e. a "HIGH" can become "LOW", not but vice versa).

So far, this has been possible through further process steps be eliminated, but this affects the manufacturing process expensive and the process run lengthened because additional Mask levels or at least additional work steps in the processing became necessary.

The object of the invention is therefore, method and Devices for checking and reading out the programming to specify a cavity fuse that mentioned Reliability problem during the operation of the device recognize and if necessary generate an error signal, in particular, making the manufacturing process more expensive due to additional mask levels or at least additional processing steps avoided shall be.

This task is accomplished through a procedure for checking the Programming a cavity fuse with the features according to Claim 1, a test circuit for a cavity fuse with the Features according to claim 5, a method for reading the Programming a cavity fuse with the features according to Claim 10, a read circuit for a cavity fuse with the Features according to claim 15, a fuse cell with the features according to claim 18 and a fuse matrix with the features according to Claim 20 solved. Further advantageous embodiments, Refinements and aspects of the present invention result from the dependent claims, the Description and the accompanying drawings.

An essential on the basis of the invention The idea is that to check and read the Programming a cavity fuse that is a programmable Bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive material arranged to cover the bridge is, the resistance between the cover and anode and / or cathode is determined. As already mentioned mentioned, can undesirably become parasitic conductive Form paths in the cavity fuse. By the invention can now such parasitic paths between anode and Cavity fuse cathode reliably determined and their Effects are corrected if necessary.

To identify a parasitic path, the following is Circumstance helpful: It turns out that such Parasitic path usually always over the cover is closed. So if one is already programmed Cavity fuse with low resistance over the course of its lifetime there is usually also a low-impedance one Contact between cover and anode and / or cathode. Of It is particularly important here that the contact resistance between cover and cathode or anode less than that Resistance between anode and cathode of the cavity fuse is. Theoretically, this can be explained by the fact that there are residues of vaporized polysilicon between the anode and Cover as well as two between cover and cathode Form conductive paths. The series connection of both As a result, paths have a higher resistance than anyone of the two individual paths. This can also be an option existing cover oxide that will damage the Cover insulated from anode and cathode.

The invention is relatively simple detect whether a cavity fuse tipped from "HIGH" to "LOW" is. Only with a perfectly functioning cavity fuse the cover has a high resistance to the anode and cathode. is the cavity fuse partially damaged, so there is one Contact between cover and only one of the two Electrodes (anode or cathode): works in this case but the cavity fuse, d. H. when reading you get another "HIGH" because there is still no path from the anode Cover after cathode has formed. Is the fuse complete? damaged, so there is contact from cover to both Electrodes and the reading result in a "LOW" instead of the originally programmed "HIGH".

According to a first aspect, the invention relates to a Procedure for checking the programming of a cavity fuse, which is a programmable bridge made from a first conductive Material with an anode and a cathode and a cover made of a second conductive material which for Covering the bridge is arranged. The procedure is now the resistance between the cover on the one hand and the anode and / or cathode, on the other hand, to detect a defect in the Cavity fuse can be seen.

In a preferred embodiment of the method a reading current is stamped into the anode, a first and then a second potential different from the first Cover applied and the voltage between the anode and Measured cathode. The measured voltage changes with the Potential change on the cover, so there is a conductive Path between one or both electrodes - anode and / or cathode and cover. This requires, that the cavity fuse is programming, d. H. the bridge is interrupted. Otherwise, i.e. if the measured If the voltage does not change, the cavity fuse is OK, i. H. there is no conductive path between the electrodes and the cover. With this phase one can programmed cavity fuse a contact at least one of the Electrodes and the cover can be safely detected.

In a further phase, a cathode can be applied Reference potential before the reading current is impressed into the anode be placed. Now there is a conductive (parasitic) path between anode and cover, so the measured voltage a change. In this case there is with a correctly programmed cavity fuse between the anode and cover a conductive path, d. H. is the cavity fuse malfunction. This phase can be used for a programmed Cavity fuse ensures contact between anode and cover can be detected.

To establish contact or parasitic paths between Cover and cathode in a programmed cavity fuse To detect a reference potential to the cathode placed, a reading current stamped into the cover, the anode isolated and the voltage between cover and cathode can be measured. Is the potential at the Cavity fuse cover much smaller than that Operating voltage of the agent that reads the current into the Impresses cover, so there is contact between cover and cathode in front.

Another aspect of the invention relates to a Test circuit for a cavity fuse, which is a programmable Bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive material arranged to cover the bridge is. The test circuit is characterized by that they have to perform the above the inventive method is formed.

It preferably has means for impressing one Reading currents, means for applying potentials and Voltage measuring device.

The means for impressing a reading current and the means transistors, in particular, can be used to apply potentials be of the MOS type.

In a particularly preferred embodiment, include the means for impressing a reading current with a current mirror, making a more precise and, above all, constant, essentially load-independent reading current is obtained.

The test circuit can furthermore have control means which especially to carry out the above are designed according to the inventive method. In this Embodiment, the control means take control of the Steps to check the programming of the Cavity fuse are required. Will the test circuit for example in a complex electronic circuit, used in particular on an integrated circuit, can thereby carry out other circuit modules be relieved of the procedure. You can also take an exam independent of additional external circuit parts or -modules performed by the integrated circuit itself become.

The invention further comprises a method for reading out programming a cavity fuse, the one programmable bridge made of a first conductive material with an anode and a cathode and a cover a second conductive material used to cover the Bridge is arranged. According to the procedure first read current in the anode and a second read current in the cover is embossed and the potentials at the anode and Cover for determining the in the cavity fuse programmed value logically to an output signal connected.

In a specific embodiment, the logical one Linking the inversion of the potential on the cover and an OR operation with the potential at the anode. With this, by a few logical circuit elements feasible logic function can be read out simultaneously a test of the cavity fuse performed and within certain Limits a verification of the programming made become.

According to a further aspect, the invention relates to a Reading circuit for a cavity fuse, which is a programmable Bridge made of a first conductive material with an anode and a cathode and a cover from a second conductive material arranged to cover the bridge is. To get a programmed value safely from the Being able to read out cavity fuses is a means of imprinting a first read current into the anode and a second Read currents in the cover and means for evaluating the Potentials on anode and cover and for logical Linking the evaluated potentials are provided to a value programmed in the cavity fuse as Get output signal.

Means for impressing a first are preferred Read current in the anode and a second read current in the Covering transistors, especially of the MOS type.

The means for evaluating the potentials at the anode and Coverage and for logical linking of the evaluated Potentials are particularly preferred Embodiment logic gate.

In a particularly preferred embodiment, the second reading stream pulsed, so to speak: here it is in predetermined first periods in which the cavity fuse is selected, chosen so small that the potential at the cover in the event of a fault is smaller than the potential at the Is anode.

Finally, the second reading current can be predetermined second periods when the cavity fuse is not is selected, be chosen so large that it is a Electromigration causes the growth of oneself forming parasitic current path between cover and Cathode is inhibited.

To testability of the whole, through cavity fuse and the electronic means provided for reading Increasing circuitry is preferred before reading out the cavity fuse by means of a transistor, in particular MOS Transistor, a potential applied to the cover and that Output signal measured a first time; after that it will Potential switched off by means of the transistor and that Output signal measured a second time; the two measured output signal values can then be evaluated become.

Here are, for example, measured Output signal values from logic "HIGH" and then logic "LOW" means both the means intended for reading and the cavity fuse is fine. In contrast, they are for reading provided funds are functionally in order if not a logical one twice as output signal value "LOW" results because, for example, the contact resistance to Coverage is too large; in this case, however Cavity fuse okay. Will be one twice in a row Measured logically "HIGH", the cavity fuse is faulty. The measurement result is logically "LOW" and then logically "HIGH" in principle not possible.

A fuse cell according to the invention comprises a cavity fuse, which is a programmable bridge made from a first conductive Material with an anode and a cathode and a cover made of a second conductive material that is used to cover the Bridge is arranged, has that explained above Read circuit, and a programming circuit for Programming the cavity fuse. The anode is included with a supply line to the fuse cell and the cathode connected to a transistor. This will make a very space-saving variant of a fusel cell created that one Power transistor for switching the on and off Programming current (this is the one with the cathode Cavity fuse connected transistor).

Preferably, the programming means and the Means for reading out essentially MOS transistors.

The fuse cells are preferably in a fuse matrix arranged or used. Such a fuse matrix can for example in a CAD system as a library element be in place so that when designing an integrated Circuit can be built into this.

The invention is explained below with reference to figures of the Drawing shown in more detail. Show it:

Fig. 1 is a Hohlraumfuse with read circuit according to the prior art,

Fig. 2 shows a first embodiment of the read circuit according to the invention for a Hohlraumfuse in a first operating state,

Fig. 3 shows the embodiment of the read circuit according to the invention for a Hohlraumfuse in a second operational state illustrated in FIG. 1,

Fig. 4, the embodiment shown in Fig. 1 of the read circuit according to the invention for a Hohlraumfuse in a third operating state,

Fig. 5 shows a second embodiment of the read circuit according to the invention for a Hohlraumfuse in a first operating state,

Fig. 6 shows a programming circuit for a Hohlraumfuse according to the prior art, and

Fig. 7 shows an embodiment of a programming circuit according to the invention.

The following can be the same or at least functional the same elements with the same reference numerals.

In Fig. 1, the normal read circuit for a Hohlraumfuse is shown in which the read current in the anode A stamped and the voltage at the anode A (with respect to earth = cathode potential) is digitally evaluated. The cover is floating. For a more detailed description of FIG. 1, reference is made to the introduction to the description.

In FIG. 2, an extension of the conventional read circuit through the pMOS transistor Q3 and the NMOS transistor Q4 is shown, but which is still switched inactive. Fig. 3 shows how one shown in dashed lines with the aid of this extension circuit contact between anode A and the, approximately rectangular cover 14 detected: Such contact occurs when the anode voltage of "HIGH" to "LOW" toggles once the cover 14 is grounded.

FIG. 4 shows how a contact between cathode K and cover 14 is detected with this expansion circuit: Here the reading current is no longer impressed into the anode A, but into the cover 14 (the anode is floating). At the same time, the potential of the cover 14 is digitally evaluated: if it is "LOW", there is a low-resistance contact between the cover and the cathode.

In a productive module, it is advisable to carry out the functions of the circuit from FIGS. 2, 3 and 4 in multiplex operation in successive clock cycles (for example by switching the relevant transistors on and off alternately), the three voltages or logic variables Store U1, U2, U3 in flip-flops and then carry out the following evaluation with the knowledge gathered:
(U1 = "HIGH") and (U2 = "LOW") means: contact between cover and anode A;
(U3 = "LOW") means: contact between cover and cathode K;
(U1 = "LOW") and (U3 = "LOW") means: contact between the cover and both electrodes, i.e. anode A and cathode K.

In the latter case in particular, it is assumed that it only for programmed cavity fuses Contact between the cover and one of the two electrodes can come. This may have to be done after processing and before programming the module (i.e. during the wafer test or possibly also be verified at the beginning of the module test).

The procedure just described requires one certain effort for the multiplexer circuit and delivers then more information than the module in practice for flawless function required.

FIG. 5 shows a very simple modification of the conventional read-out circuit which not only recognizes the critical error "fuse is programmed, but is read as" LOW "read out" according to contacts for covering, but even corrects it. For this purpose, in addition to the reading current IL1, which is impressed into the anode A of the cavity fuse 10 , a further reading current IL2 is impressed into the cover 14 . Both anode and coverage potential are assessed digitally. If the anode potential is "HIGH", there is no further doubt about it. However, if the anode potential is "LOW", the fuse is "not programmed" only if there is no contact with the cover, ie if the cover potential is "HIGH". However, if the cover potential is "LOW", there is at least one contact 16 , 18 from cover 14 to cathode K. However, this contact 16 , 18 can only have come about in such a way that the cavity fuse 10 has been programmed and then a parasitic conductive path has formed. So the fuse should be "HIGH"; the circuit in FIG. 5 makes the correction and supplies "HIGH" at its output.

The additional circuitry for this Measures are limited: there will only be one OR gate OR and an inverter INV and a pMOS transistor Q3 (as Power source) required. The additional power loss is in static operation and as long as there is no parasitic path from Cover against cathode has formed about zero.

If the cavity fuses are correct and there is no contact with the cover, no read current IL2 flows - so it does not contribute to the power consumption of the device. However, if the cavity fuse has a parasitic path between cover 14 and cathode K, efforts are made to detect it with a high degree of certainty. Therefore, IL2 should not be too large, so that potential S2 will surely become "LOW" before potential S1 becomes "LOW".

However, it is possible to only determine the potential S2 Read out times. At other times it recommends to choose the current IL2 as large as possible: according to Electromigration can then take the parasitic path below Dismantle circumstances. There is an upper limit due to the maximum permitted current consumption of the module.

A special aspect of the reliability of this circuit is its testability: it could be the case, for example, that processing errors (e.g. dust on the chip surface during exposure) cause the contact from the node with the potential S2 to the cover 14 of the cavity fuse 10 in FIG. 5 is not properly executed. He can then U. have a contact resistance of many mega-ohms. In this case, it can happen that during the revitalization of the fuse 10, although there is a low-resistance contact from the anode A to the cover 14 and from the cover 14 to the cathode K, the potential S2 nevertheless remains "HIGH" because the voltage drop across the contact resistor is so big. Then the circuit does not recognize the cover contact and delivers a "LOW" at the output OUT.

This extremely unlikely case of a double fault (1st fault: fuse revitalizes in the course of the service life load, 2nd fault: faulty contact between node or line with potential S2 and cover 14 ) can be eliminated if the contact resistance is tested in the wafer or block test , The nMOS transistor Q5 in FIG. 5 is used for this purpose . Its drain is contacted directly on the cover 14 of the fuse 10 with its own contact. When testing the device, the gate of Q5 is set to "HIGH" so that its channel becomes low-resistance. If the contact resistances from the node or from the line, the potential S2 to the cover 14 and from the cover 14 to the drain of Q5 are properly low-resistance, then S2 "LOW", S3 "HIGH" and the output signal OFF "HIGH". If Q5 is then switched off, OFF becomes "LOW" (because the fuses have not yet been programmed at this point).

• 1. die Abdeckungskontaktierung samt Inverter und ODER- Gatter voll funktionsfähig ist und
• 2. die Fuse im Originalzustand niederohmig (also unprogrammiert) ist.

From this sequence it can be concluded that

• 1. the cover contact including inverter and OR gate is fully functional and
• 2. The fuse is in the original state with low resistance (ie unprogrammed).

If the cover contact would be too high would have been processed, then you would get in the test low impedance fuse the sequence "LOW", "LOW" and at high-resistance fuse the sequence "HIGH", "HIGH". Both times the processing error discovered; the block can to be retired.

It has not yet been shown how the cavity fuse is programmed. Fig. 6 shows this, first the prior art. An essential feature is that the switching transistors that conduct the high programming current through the fuse are on the anode side of the fuse and the cathode of the fuse is at ground.

In contrast to this, FIG. 7 shows a space-saving variant according to the invention, in which the cathode K of the cavity fuse 10 is placed on the drain of a power nMOS Q6. This nMOS Q6 is switched on for programming the relevant fuse and pulls the programming current towards ground. The read current is drawn from the cathode K and from the cover 14 and the resulting potentials are combined with an inverter and a Nand gate (similar to FIG. 6) to form an output signal OUT.

This variant has the advantage of being particularly space-saving to be, since they only have the minimum necessary for each fuse Number of power transistors - namely one - used. In addition, this is an nMOS transistor, which due to its lower channel resistance when switched on is even smaller than a pMOS transistor. The advantage of nMOS transistor is also its powerless control: You can use a strong gate in normal operation Connect the inverter to ground so that the transistor also in the case remains safely switched off from ESD and EMC events. This powerful inverter does not pull in static operation Current (other than a negligible leakage current) and carries therefore not noteworthy for the power loss of the device at.

The circuits shown in FIGS. 2-7 are explained in detail below, in particular with regard to their mode of operation.

Fig. 2 is an extension of the present invention shows the conventional reading circuit of Figure 1 through the transistors Q3, Q4. If the fuse is programmed properly 10 and there is no parasitic conductive path between the anode A and cathode K of the Hohlraumfuse has formed 10, so is the potential U1 identical to VDD since transistor Q2 saturates (it cannot impress the read current in the extremely high-resistance fuse). Transistors Q3 and Q4 represent the extension of the conventional reading circuit. They both contact the conductive cover 14 of the cavity fuse 10 , but are both switched off in this phase of the reading process (ie, charges 14 cannot flow in or out of the cover 14 ).

Fig. 3 in the 2nd phase of the read operation is impressed to be the read current to the anode A of the Hohlraumfuse fourteenth However, the gate of Q4 is connected to VDD, so that the cover potential is pulled to ground. If - as indicated in FIG. 3 - a contact 16 has occurred between cover 14 and anode A of the cavity fuse 10 , Q4 pulls the potential U2 to ground via this contact 16 . Such a contact 16 is thus detected when in phase 1 U1 = "HIGH" (see FIG. 2) and in phase 2 U2 = "LOW". This damage to the cavity fuse 10 is of minor importance, however, because it does not change the programmed logic state of the fuse 10 (this is still "HIGH").

Fig. 4 in the third phase of the read operation, the read current to the anode A of the Hohlraumfuse 10 is turned off so that the anode A is floating (ie, it can no charges from the anode A derived or supplied). Q4 is turned off by grounding its gate. Q3 is turned on so that this transistor tries to inject current into the cover 14 of the cavity fuse 10 . In the normal case - if the cover 14 has no conductive connection to the cathode K, the potential U3 = VDD. If, however, as shown in FIG. 4, a conductive path has formed between cover 14 and cathode K of fuse 10 (contact 18 ), U3 is drawn to ground via this contact 18 .

FIG. 5 shows a readout circuit which impresses a first read current into the anode A and a second read current into the cover 14 of the cavity fuse 10 . If the fuse 10 is correctly programmed (ie no parasitic path from A to K via the cover 14 ), the output signal becomes OFF = "HIGH". If a parasitic path from A to K has formed, so that the signal S1 = "LOW", then S2 = "LOW". It is assumed here that the contact resistance between cover 14 and K can never be greater than that between A and K via cover 14 . If S2 is "LOW", S3 becomes "HIGH" and the output signal OFF = "HIGH". As an output signal OUT therefore the value that corresponds to a programmed Hohlraumfuse 10 shows: the circuit has detected at low AK resistance of the fuse 10, according cover contact error and corrected.

• 1. Wenn sich ein Kontakt zwischen Anode A und Kathode K unter Umgehung der Abdeckung 14 bildet, so wird dieser immer als "LOW" ( = nicht programmiert) bewertet. Dieser Fehlermechanismus tritt jedoch in der Praxis nicht auf.
• 2. Wenn sich ein Kontakt zwischen Abdeckung 14 und Kathode K bildet, obwohl die Fuse nicht programmiert wurde, so wird ein "HIGH" erkannt. Es gibt keine bekannte Ursache, die zu diesem Fehlerbild im Laufe der Lebensdauer führen könnte. Lediglich ein Prozessierungsfehler und/oder Montagefehler könnte unter Umständen zu einem Kontakt zwischen Abdeckung 14 und Kathode K führen. Daher müssen die Bausteine nach Beendigung der Prozessierung und Montage, aber noch vor der Programmierung diesbezüglich getestet werden.

The circuit only fails in the following two cases:

• 1. If a contact is formed between anode A and cathode K bypassing cover 14 , this is always rated as "LOW" (= not programmed). However, this error mechanism does not occur in practice.
• 2. If a contact forms between cover 14 and cathode K, although the fuse has not been programmed, a "HIGH" is recognized. There is no known cause that could lead to this fault pattern over the course of its service life. Under certain circumstances, only a processing error and / or assembly error could lead to contact between cover 14 and cathode K. For this reason, the blocks must be tested after processing and assembly, but before programming.

To ensure that the cover 14 has been properly contacted and the NOR gate is functioning, the nMOS transistor Q5 is used: this transistor is switched on in the test (before programming). If a "HIGH" then appears as the output signal OFF, the cover contact is OK. Q5 is then always switched off during further operation.

Fig. 6 shows a programming circuit for fuses according to the prior art: Each fuse is extended by a programming circuit to a Fusezelle which merely serves to ignite the fuse. All fuse cells are interconnected for their power supply on a common supply line. The lines drawn in bold carry the programming current when the fuse F shown is fired. In order to switch the large currents at mostly high voltages, npn bipolar transistors are used. The transistor T1 can be actuated in different ways. An extension to a Darlington transistor (transistor T1 with transistor T2) with a control via a pnp transistor T3 is shown.

An essential feature of this circuit (in contrast to FIG. 7) is that the fuse is grounded on one side and the switching transistor T1 on the anode of the fuse. Furthermore, the line Lp is only connected to a sufficiently high voltage for programming. In normal operation (when the fuses are read out) the line Lp is connected to OV.

Due to the numerous bipolar transistors, the Space requirement of this fusel cell is considerable, as each one Fuse must be equipped with this circuit. On Another disadvantage is that voltage pulses on the line Lp (due to ESD and EMC events) lead to Tl briefly (for a few nanoseconds up to microseconds) becomes a leader because, according to its base, the large base Collector capacity is "pulled up" for a short time. Tl can not be switched off perfectly (at least with transient interference pulses).

Fig. 7 shows a space-saving variant of an Fusematrix according to the invention. All fuses hang with their anode A on a common "Supply Line" SL. When fuses, ie when programming fuses, this "supply line" SL is set to a high potential and the fuse 10 to be programmed is selected by means of the transistor Q6. When reading out, the "Supply Line" SL is connected to the supply voltage of the logic gates, which are integrated on an integrated circuit together with the fuse matrix. The read current IL is fed into the cathode K via a transistor Q2 and into the cover 14 via a transistor Q3. The resulting potentials S4 and S5 are logically combined with an inverter and a Nand gate, and deliver a "HIGH" as the output signal AUS if the fuse link AK is high-resistance or if the cover 14 shows a low-resistance contact to the anode A, for example via the Contact 16 . Transistor Q5 has a similar function to transistor Q5 shown in FIG. 5.

An advantage of this circuit is that transistor Q6 can be switched off very efficiently, so that no current flows through fuse 10 even at voltage pulses at anode A and an unprogrammed fuse is loaded with current as little as possible. Furthermore, this unit cell is very small compared to that shown in FIG. 6, because it requires exactly one power transistor that switches the fuse current on / off. Legend: 10 Hohlraumfuse
12 bridge
14 cover
16 Contact between anode and cover
18 Contact between cathode and cover
Q1 pMOS transistor
Q2 pMOS transistor
Q3 pMOS transistor
Q4 nMOS transistor
Q5 nMOS transistor
IL1 power source
U1 measuring voltage
U2 measuring voltage
U3 measurement voltage
INV inverter
OR OR gate
S1 circuit node
S2 circuit node
S3 circuit node
OFF readout signal

Claims (20)

1. A method for checking the programming of a cavity fuse ( 10 ), which has a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material arranged to cover the bridge ( 12 ), characterized in that the resistance between cover ( 14 ) on the one hand and anode (A) and / or cathode (K) on the other hand is determined. 2. The method according to claim 1, characterized in that a reading current is impressed into the anode (A), a first and then a second potential different from the first is applied to the cover ( 14 ) and the voltage (U2) between the anode (A) and cathode (K) is measured. 3. The method according to claim 2, characterized in that a reference potential to the cathode (K) before the stamping of the reading current is placed in the anode (A). 4. The method according to any one of the preceding claims, in particular according to claim 1, characterized in that a reference potential is applied to the cathode (K), a reading current is impressed in the cover ( 14 ), the anode (A) is isolated and the voltage ( U3) between cover ( 14 ) and cathode (K) is measured. 5. Test circuit for a cavity fuse, which has a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material, which is used to cover the bridge ( 12 ) is arranged, characterized in that the test circuit (Q3, Q4) is designed to carry out the method according to one of the preceding claims. 6. test circuit according to claim 5, characterized in that it means (IL1, Q1, Q2; Q2, Q3) for impressing a Reading currents, means (Q3, Q4) for applying potentials and voltage measuring means (OR, INV). 7. test circuit according to claim 6, characterized in that the means (IL1, Q1, Q2; Q2, Q3) for impressing one Reading currents and the means (Q3, Q4) for applying Potentials are transistors, especially of the MOS type. 8. test circuit according to claim 7, characterized in that the means (IL1, Q1, Q2; Q2, Q3) for impressing one Read current comprise a current mirror. 9. Test circuit according to one of claims 5-8, characterized in that it has control means, in particular for Carrying out a method according to one of claims 1-4 are trained. 10. A method for reading out the programming of a cavity fuse ( 10 ) which has a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material arranged to cover the bridge ( 12 ), characterized in that a first read current is impressed in the anode (A) and a second read current in the cover ( 14 ) and the potentials (S1, S2) on the anode (A) and Cover ( 14 ) for determining the value programmed in the cavity fuse ( 10 ) logically linked to an output signal (AUS) (INV, OR). 11. The method according to claim 10, characterized in that the logical combination of the inversion (INV) of the potential (S2) on the cover ( 14 ) and an OR combination (OR) with the potential (S1) on the anode (A) includes. 12. The method according to claim 10 or 11, characterized in that the second reading current in predetermined first periods in which the cavity fuse ( 10 ) is read out is chosen so small that the potential ( 52 ) on the cover ( 14 ) is less than is the potential ( 51 ) at the anode (A). 13. The method according to any one of claims 10-12, characterized in that the second reading current in predetermined second periods in which the cavity fuse ( 10 ) is not read out is chosen to be so large that it causes electromigration, through which the growth of a parasitic current path between the cover ( 14 ) and the cathode (K) is inhibited. 14. The method according to any one of claims 10-13, characterized in that before reading out the cavity fuse ( 10 ) by means of a transistor, in particular MOS transistor (Q5), a potential is applied to the cover ( 14 ) and the output signal (OFF) is measured a first time, then the potential is switched off by means of the transistor and the output signal (OFF) is measured a second time and the two measured output signal values are evaluated. 15. Reading circuit for a cavity fuse, comprising a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material, which is used to cover the bridge ( 12 ) is arranged, characterized in that means for impressing a first read current into the anode (A) and a second read current into the cover ( 14 ) and means for evaluating the potentials (S1) on the anode (A) and cover (S2 , 14) and for logically combining the evaluated potentials in order to obtain a value programmed in the cavity fuse ( 10 ) as an output signal (OFF). 16. Reading circuit according to claim 15, characterized in that means for impressing a first reading current in the anode (A) and a second reading current in the cover ( 14 ) are transistors (Q2, Q3), in particular of the MOS type. 17. reading circuit according to claim 15 or 16, characterized in that Means for evaluating the potentials (S1) at anode (A) and Cover (S2, 14) and for logically linking the evaluated potentials are logic gates (INV, OR). 18. Fuse cell with
a cavity fuse ( 10 ) comprising a programmable bridge ( 12 ) made of a first conductive material with an anode (A) and a cathode (K) and a cover ( 14 ) made of a second conductive material used to cover the bridge ( 12 ) is arranged,
a read circuit (Q5, Q3, Q2, NAND) according to any one of claims 15-17, and
a programming circuit (Q6) for programming the cavity fuse ( 10 )
characterized in that
the anode (A) is connected to a supply line (SL) of the fuse cell and the cathode (K) is connected to a transistor (Q6). 19. Fuse cell according to claim 18, characterized in that the means for programming (Q6) and the means for Reading (Q5, Q3, Q2, NAND) essentially MOS Have transistors (Q2, Q3, Q5, Q6). 20. fuse matrix, characterized in that it has fuse cells according to claim 18 or 19.