DE10120255C2 - Integrated semiconductor memory with self-test and test arrangement with test system and integrated semiconductor memory - Google Patents

Description

The present invention relates to an integrated half circuit memory with self-test and a test arrangement with a test system and the integrated semiconductor memory.

Conventional memory chips, for example DRAMs (Dynamic Random Access Memory), to increase the yield at Manufacturing usually redundant memory cells with which replaced defective memory cells of the memory chip can be. For example, 256 megabit memory chips several 1000 redundant elements.

In order to be able to replace defective memory cells in a memory chip, it is first necessary to test the memory chip in a test system. For this purpose, expensive and complex test systems are available, which have a defined number of test channels, which are connected to data outputs, the so-called DQ pads, of the memory modules. For example, 16 such I / O channels are required simultaneously for 256 megabit memory chips.

Because the redundant to be provided on the memory chip Memory cells require additional space on the chip and cause higher costs, it is wonderful worth it, the redundancy available if possible optimal use and to achieve a high yield. For this purpose, in the test systems, which are highly parallel, external computer systems are executed, computing-intensive and elaborate algorithms implemented. The used Redundancy algorithms are very complex.

The complexity of the task increases because with one redundant element, for example a redundant word line,  multiple memory cell errors along the word line are repairable, which alternatively talk to a variety then bit lines could be repaired. Another Increasing the complexity of the task often results from so-called interblock redundancy concepts used, which (Other) redundant elements from in the same spoke chip can provide ordered foreign memory blocks NEN.

The reprogramming and thereby replacing the de faulty memory cells due to redundant elements usually by means of laser exposure and so-called laser fuses in manufacturing.

Problematic with the increasing storage density and the too increasing size of memory chips is that a variety of data output drivers, for example 16 channels testing memory chip, the so-called DUT (Device Under Test) are provided, which have an equal number of parallel Da channels on the test system for testing a single memory make chips necessary. In addition, these test channels of the Test system for transferring the test data from the memory chip to the test system for redundancy calculation with high frequencies can work, for example at 100 MHz at 100 MHz SD (Synchronous Dynamic) RAMs.

In the document US 6,065,141 A is a semiconductor memory a diagnostic circuit and a redundant circuit specified. This includes a group of memory circuits for storing position data of defective memory cells. An output circuit is for converting the position data designed in serial data.

The object of the present invention is an integrated Specify semiconductor memory that enables replacement defective memory cells with redundant memory cells  less effort and significantly lower test costs respectively.

According to the invention the object is achieved by an inte free semiconductor memory with self-test the features of the present patent claim 1.

Only those that are defective are recognized in the buffer memory stored memory cells and then via the Paral Transfer the lel / serial converter to an external tester. As a result, the data to be transmitted to the tester are signifi reduced edge.

The parallel / serial converter enables a reduction of the Data output driver (DQ) pads on a memory chip from übli currently 16 on only 1 connection pad, via wel all necessary and complete redundancy information ions can be transferred from the DUT to the tester. Consequently the parallelism during testing can be significantly increased because a multiple of memory chips simultaneously on one multi-channel tester can be tested.

As a result, the test and thus the manufacturing costs, of which the test costs already make up over 10% can, significantly reduced.

With a number of M, the buffer memory is redundant Word lines and N redundant bit lines in one memory cher cell field of the integrated semiconductor memory is preferred designed as M / N + 1 or as M + 1 / N memory.

In a preferred embodiment of the present invention the bit width of the output of the parallel / serial Converter less than 4.  

The bit width of the output of the parallel / serial converter is in the given context synonymous with the number of to test an integrated semiconductor memory Chen channels on the test system and synonymous with the number the data output driver on the integrated semiconductor memory. In the present subject matter, this is preferably 1 or 2.

In a further advantageous embodiment of the present The invention is the parallel / serial converter as a shoot trained register. The shift register preferably has parallel data inputs for the transfer of preferred columns information, line information and DQ address of the respective, defective and replaceable memory cell. The DQ address can be used to clearly assign the defective memory cell le to a specific memory cell array in the integrated Semiconductor memory may be required. In addition, white more memory locations in the shift register for storing over run information of rows or columns can be provided. The shift register has a serial output that comes before only 1 bit wide.

In a further preferred embodiment of the present the invention are means for compressing the transmitted Test data or redundancy data of the memories to be replaced cells provided in the semiconductor memory. A first Kompri mation of the data is already achieved by using lying object only the so-called fail data are transmitted, that is, only those addresses those memory cells that are recognized as defective. Another reduction or compression of the transfer The test data enables a further increase in the speed redundancy calculation. The compression is there based on the principle that always a multiple to test the cells compared to the cells to be repaired lies. The internal storage of errors in the buffer memory of the  Redundancy data can be indicated using a compression method be reduced.

In a further preferred embodiment of the present According to the invention, the semiconductor memory has a comparator to provide an error signal at its output in Dependency on actual and target input Test data on, an N row counter and M column counter, which is coupled to the comparator for incrementing N row counter or M column counter if there is one Memory cell defect and a memory overflow decoder for transferring row and column addresses into the buffer memory in case of an overflow of N-line counter or M- Column counter.

With the row and column counters and the overflow decoder and the comparator, which recognizes defective memory cells, is a simple but very effective compression of the test data achieved by the absolutely necessary repair bit lines and / or word lines can be recognized. Because if, for example, five defective ones on one word line Memory cells are recognized, but only four redundant ones Bit lines are present, so is the word order in question must be replaced or reprogrammed. The detection of these so-called "must-repairs" avoids the Use of very deep and complex to implement Asso ziativ memory for storing the faulty cells and thus represents a significant reduction in the number of transmissions Test data is a very inexpensive implementation option for redundancy compression. The memory overflow decoder To detect an overflow, the In formation, how many redundant bitlei and how many redundant word lines are available. If no memory overflow is detected, the content of the Buffer memory completely via the parallel / serial Transfer converter to the external test system.  

In the present Invention is a frequency multiplying circuit vorese hen, the input side with a frequency generator with the maximum operating frequency of an externally connectable Te sters can be coupled and the one at its output, the one with the Te direction is coupled, a multiple of this frequency provides.

This is due to the provision of the frequency multiplication circuit Principle, the internal test speed of the DUT from to decouple the external test system speed. at for example, a test system specified at 30 MHz can Control the DUT at 30 MHz, the DUT itself can use its internal BIST (Built In Self Test) using the frequency ver Carry out multiplication switching internally with 120 MHz and the Redundancy data compressed at 30 MHz at the data output provide drivers. Accordingly, can be more advantageous wise test systems with lower system requirements speed can be used and thereby further test cost savings.

In a further preferred embodiment of the present the invention is a test arrangement formed with a Test system and as a DUT an integrated semiconductor memory as described above, being at the entry / exit point the semiconductor memory a workstation, a personal computer ter or the like for redundancy calculation outside the Test system is connected.

This enables the redundancy calculation to be independent from the test system used, so that when a new one is introduced Memory generation not immediately new test systems, which ko are intensive, are required, but are initially single Lich the required computing power by adjusting the Re performance of the workstation can be increased. You can also the required redundancy algorithms from the test user in can be easily adapted without changing the test system  from the test system manufacturer. This enables overall a higher flexibility when testing Storage modules and thus a higher yield.

Further details of the invention are the subject of Un subclaims.

The invention is described below using an exemplary embodiment explained in more detail with reference to the drawings. Show it:

Fig. 1 shows a first embodiment of the present invention using a simplified block diagram and

FIG. 2 shows an arrangement with a test system which is connected to a DQ output of a semiconductor memory according to FIG. 1.

Fig. 1 shows an integrated semiconductor memory having self-test, a plurality of memory cell arrays 1 comprises. Each memory cell array 1 has row decoders 2 and column decoders 3 for selecting memory cells and for write and / or read accesses. The row decoders 2 are designed to select word lines 4 , while the column decoders 3 are designed to select bit lines 5 .

The memory cell array 1 has a plurality of memory cells arranged in a matrix, some of which are defective. The defective memory cells are identified by reference number 6 .

Is as due to the customary for the preparation of memory chips manufacturing steps is a high probability for a plurality of defective memory cells 6 along of a common word or bit line 4, 5 occurring are arranged in ge recorded as five defective memory cells 6 along ei ner word line. 4

With the memory cell array 1 is a test device 7 for providing a BIST, built-in self-test, coupled, which is formed for performing functional testing of the memory cells 1 of. For this purpose, test data 8 are written into the memory cell 1 . The data are then read out from the memory cell array and compared with the stored test data 8 in a comparator 9 . Using the test data 8 , the comparator 9 determines whether the memory cells in the memory cell array 1 are defective or not.

On the input side to the test device 7 , a frequency multiplier 10 is connected, which multiplies a frequency provided externally by a tester, for example an integer, and thus the integrated semiconductor memory, in particular its self-test device 7 , with a higher clock frequency than the maximum clock frequency of the tester be operates.

A buffer memory 11 is further coupled to the test device 7 and the comparator 9 , in which the row and column addresses are written in the presence of a defective memory cell, and the associated DQ address is used to assign the defective memory cell 6 to one of the memory cell fields 1 enables. Furthermore, a column and row counter 12 , 13 is coupled to the output of the comparator 9 . The row and column counters 12 , 13 are each connected to a memory overflow decoder 14 which marks the corresponding address of the memory cell 6 in the buffer memory 11 when there is a memory overflow in the row counter 12 or the column counter 13 , while when there is no overflow , the entire content of the buffer memory 11 is written into the tester.

Finally, a parallel / serial converter 15 is coupled to the buffer memory 11 and the memory overflow decoder 14 and is connected to the memory fields for row, column and DQ address information of the buffer memory 11 and one serial output for parallel reading in of data has only a single pin or pad of the DUT, that is to say of the integrated semiconductor memory, for clocking out the redundancy data in series. The parallel / serial converter 15 is designed as a shift register. In addition to the described address information stored in the buffer memory 11 , the shift register 15 has one or more further memory cells W, B for storing memory overflow information from the counters 12 , 13 and is connected to the decoder 14 for this purpose.

The mode of operation of the arrangement in FIG. 1 is explained below: The memory cell array 1 has N available redundant bit lines and M available redundant word lines. The test device 7 , which comprises a BIST processor, provides the word line and bit line addresses required for a memory cell field test as well as the data to be written and read. In the event of a faulty read access, that is to say if a defective memory cell is present, the memory address just created is stored in the buffer memory 11 , at the same time the column or line counter 12 , 13 is increased, depending on whether the test algorithm along a word line, that is to say incrementation of the word line counter, or along a bit line, that is, incrementation of the bit line counter tests. In the event of incorrect access subsequently occurring, that is to say the memory cell subsequently recognized as defective, the defective address is in turn stored in the buffer memory 11 , the previously stored address being shifted into the next shift register. Again, the corresponding counter 12 , 13 is increased. This process is repeated until either one of the counters 12 , 13 overflows or the test device 7 addresses the next memory segment. In this case, the counters 12 , 13 are reset with a reset device (reset). If one of the counters 12 , 13 overflows, only the last or the first incorrect address including word line or bit line bits W, B and the corresponding data segment DQ is clocked out in series via the parallel / serial converter 15 to the external test system.

In the event that none of the counters 12 , 13 overflow and the test algorithm jumps into a further memory segment, for example another memory cell array 1 , no compression can take place and the complete address data including data segment must be clocked serially to the external test system. However, since with n available redundant elements, the word lines / bit lines to be tested are usually at least 100 × n, the data rate can be reduced by a multiple even with uncompressed data (maximum n) and thus the external and internal test frequency via the frequency multiplier 10 be decoupled from each other.

In the example shown in FIG. 1, N + 1 faulty cells have occurred along a word line. However, since only N redundant bit lines are available in the same memory segment, the repair must be carried out using the available redundant word lines. This is called "must repair". It is therefore not necessary to transmit the error addresses of the N + 1 cells to the external test system, but only the address of the faulty word line 4 , the affected segment DQ and another indicator, a so-called flag, to indicate that compression the data chain in the word line direction W has taken place. With this information, an external redundancy calculation system can recover the original error information. The procedure is the same for a test along the bit lines with a maximum of M redundant word line elements.

Necessary to implement the concept described circuitry measures are simply through feasible.

In addition to the described decoupling and tester operation frequency and internal test frequency on the DUT principle, a higher degree of parallelism when testing, because the DUT only occupies one channel of a tester instead of Usually 16 channels, so functional tests can cost be carried out more cheaply. The high internal compression of the data contributes to a significant reduction in the test time contributes to further cost savings. The in terne address space can be greatly reduced.

With the principle described, so-called wafer Level burn-in test concepts can be implemented. It is still going on the actual fuse process, i.e. before a re-program defective memory cells, a so-called wafer burn In-test carried out by artificial aging of the memory chip and subsequent testing a higher one Reliability and reliability are guaranteed can. With the usual high parallelism and number of da output drivers for transferring redundancy information Such a wafer level burn-in test is not possible Lich, since the errors that have occurred are not saved can. However, this would be necessary to detect errors ren, which only occur in such a stress test and no longer detect in a subsequent test step are cash.

So-called known-good-die concepts, which use the up to previous test arrangements are not possible with the described test can be carried out because a test with in tern frequency multiplication is possible.

While with the existing BIST concepts both the pass and fail information from the DUT to the test system  transmitted, that is, both the information about intact as well as information about defective storage cells len, and with the present concept only the information is transferred via the defective memory cells enables a significant reduction in the data to be transmitted.

FIG. 2 shows the semiconductor memory 17 from FIG. 1, which is connected to a channel of the tester 18 via only one DQ output for the purpose of transmitting redundancy data from the shift register 15 . Compared to the previously usual and necessary occupancy of 16 channels on the tester 18 by only one memory chip 17 , up to 16 times the number of memory chips can now be tested simultaneously. On the one hand, this leads to considerable time savings due to highly parallel testing and, on the other hand, to a significant reduction in the test costs and thus the overall manufacturing costs.

LIST OF REFERENCE NUMBERS

1

Memory cell array

2

row decoder

3

column decoder

4

wordline

5

bit

6

defective memory cell

7

test equipment

8th

test data

9

comparator

10

frequency

11

buffer memory

12

line counter

13

column counter

14

Memory overflow decoder

15

Parallel / serial converter

16

Input / output interface

17

Semiconductor memory

18

Test System

Claims (6)

1. Integrated semiconductor memory ( 17 ) with self-test, on
at least one memory cell array ( 1 ) with row and column decoders ( 2 , 3 ) for selecting memory cells of the memory cell array ( 1 ) and for read / write access,
a test device ( 7 ) which is coupled to the memory cell array ( 1 ) for carrying out functional tests of the memory cells,
a buffer memory ( 11 ) for storing row and column address information identified as defective memory cells,
a parallel / serial converter ( 15 ) which is coupled on the input side to the buffer memory ( 11 ) and on the output side to an input / output interface ( 16 ) of the semiconductor memory ( 17 ) for transferring test data, and
a frequency multiplication circuit ( 10 ) which can be coupled on the input side to a frequency generator of an externally connectable tester ( 18 ) and which at its output, which is coupled to the test device ( 7 ), provides a multiple of the frequency generated by the frequency generator. 2. Semiconductor memory according to claim 1, characterized in that means for compressing ( 9 , 12 , 13 , 14 ) of the test data to be transmitted are provided in the semiconductor memory. 3. Semiconductor memory according to claim 2, characterized in that the semiconductor memory
a comparator ( 9 ) for providing an error signal at its output as a function of actual and target test data that can be applied on the input side,
a row counter ( 12 ) and / or a column counter ( 13 ), which is coupled to the comparator ( 9 ) for incrementing the row counter ( 12 ) or column counter ( 13 ) if there is a memory cell defect and
a memory overflow decoder ( 14 ) for transmitting row and column addresses in the buffer memory ( 11 ) when there is an overflow of row counter ( 12 ) or column counter ( 13 ). 4. Semiconductor memory according to one of claims 1 to 3, characterized in that the bit width of the output of the parallel / serial converter ( 15 ) is less than 4. 5. Semiconductor memory according to one of claims 1 to 4, characterized in that the parallel / serial converter ( 15 ) is out as a shift register. 6. Test arrangement with a test system ( 18 ) and with a semiconductor memory ( 17 ) according to one of claims 1 to 5, characterized in that the input / output interface ( 16 ) of the semiconductor memory ( 17 ) with a workstation for redundancy calculation is coupled.