DE10065754B4 - Method for controlling a computer system, computer system with an execution environment and computer program product - Google Patents

Abstract

Method for controlling a multiprocessor system (1) in the
- A source code (7) with source code commands (8) is arranged, which are arranged in a command sequence (9);
- The source code (7) comprises a data declaration (10) and the data declaration (10) assigns a first attribute (12) to a first data store (11) and assigns a second attribute (14) to a second data store (13); and
- The source code (7) is translated into machine instructions (15) and the machine instructions (15) are rearranged so that the machine instructions (15) have a machine instruction sequence (16) that differs from the command sequence (9); and
- The machine instructions (15) are stored in a command memory (4) and loaded by a computing unit (2) from the command memory (4) and executed differently from the machine instruction sequence (16) by the computing unit (2);
- wherein the first attribute (12) of the first data store (11) and the second attribute (14) of the second data store (13) have the effect that the re-sorting of the machine instructions (15) during translation is restricted in a first predetermined manner; and
- wherein the first attribute (12) of the first data memory (11) has the effect that the re-sorting of the machine instructions (15) is restricted in a second predetermined manner when executed in the computing unit (2); and
- The second attribute (14) of the second data memory (13),
a) that a re-sorting of the machine instructions (15) is not restricted when executed in the computing unit (2); and
b) that the second attribute (14) is generated during the translation together with a second source code command (20) which accesses the second data memory (13), a second machine instruction (21) which defines a second limit (22) forms so that all source code commands that are arranged before the second source code command (20) are translated into machine instructions that are arranged in the machine instruction order (16) before the second machine instruction (21).

Description

The present patent application relates a method for controlling a computer system, a computer system with an execution unit and a corresponding computer program product, which is on a computer-suitable Medium is stored.

Computer systems with conventional ones Processors are characterized in that the processor (computing unit) Loads instructions from an instruction memory and these in the order processes how they are stored in the command memory. Thereby it is always ensured that a Memory write command, that in order in the instruction memory prior to a memory read instruction is also arranged before the store read command is executed So that the Data are already stored in the data memory and the memory read command is the actual one Receives data from memory.

For example, modern processors several parallel arithmetic units, so that commands in their processing order can be swapped within a processor to be in a parallel Computing unit executed to be, reducing the overall processing power of the processor increases. A further increase in processing speed One computer system is, for example, the arrangement of several Processors possible. Here, the present command sequence is used on several processors distributed, which accelerates the processing of the underlying Problem is achieved.

The problem here is that commands in their order, causing data inconsistencies can arise.

For example, if a result is calculated in a first processor and the correct calculation of the result subsequently from a second Processor must be used. A possible one How to do this stipulates that the correct calculation of the result from the first processor in one Signal field is displayed. A second processor is only now taking effect then towards the result calculated by the first processor if the signal field indicates that the Result correct and complete was calculated. Now the order of execution in the swapped the first processor, so the signal field can be a supposed valid Show calculated result even though the first processor gets this result has not yet calculated. As a result, the second processor becomes incorrect Data processed.

The problem described does not occur only for several Processors, but is already in one processor with several Tasks, processes or threads available. For example, this problem thereby solved be that at parallel processing or modern processors the visible reversal of the order of processing in general repressed becomes. Would continue solving the problem that only a processor of the computer system processes an existing program and the rest Processors of the computer system make no contribution to the processing of the program. However, both approaches lead to one reduced computing power of the computer system.

A program code often includes a usage date and a signal date, the usage date from the first Processor of a multiprocessor system should be saved before the first processor stores the signal date, which is a correct storage of the useful date. Likewise, the second processor should be first Read and evaluate the signal date from the memory so that it can be ensured can that in a subsequent step, only valid user data from the second Processor can be read from memory. This can be done with an attribute be achieved that both the exchange of instructions during translation, as well as the exchange while the execution. On such an attribute is, for example, that from the programming language "C" known attribute "volatile".

Becomes a usable date and a signal date or a data structure and one on the data structure pointing pointer (pointer) used only by one processor, so should however also be ensured in the event of an interrupt be that Signal date is only set when the user data has already been written or the pointer to a data structure only then is used when the data structure already has valid data filled (initialized).

It is the object of the invention to provide a method of controlling a computer that leads to a leads to a more efficient functioning of the computer system, a corresponding computer system with an execution environment and to specify a corresponding computer program product.

According to the invention the object is achieved by a method for controlling a computer system with the in claim 1 listed Features.

With regard to the interrupt that occurs, the problem can be solved with the help of the second attribute, which restricts the swapping of instructions during translation and enables them during runtime. Since the swapping is carried out by the processor during runtime, the resultant can Data inconsistencies are corrected by the processor.

An advantage of the method according to the invention is that a first attribute and a second attribute for the declaration of data may be used, the first attribute being another restriction on the Interchangeability of instructions includes as the second attribute. The first attribute has an interchangeability effect of machine instructions that relate both to the translation process of the source code in machine instructions as well as on the execution order of the machine instructions in affect the computing unit. The second attribute includes one Effect regarding the interchangeability of machine instructions that relate only to the source code translation process in machine instructions.

The first attribute can be the data integrity of a Ensure multi-processor system, because the interchangeability of machine instructions both when translating, as well as the program execution is preventable. First of all, this is a limitation which slows down the processing speed of the computer program. To enable an accelerated processing of the computer program, can for example an instruction order that only one processor concerns, are generated using the second attribute. The second Attribute contains only a limitation of the exchange of Machine instructions for the translation, so that a individual processor can change the processing order internally, to accelerate the processing of the computer program. Modern processors have means that ensure data consistency guarantee.

An embodiment of the method according to the invention stipulates that the translation the source code in machine instructions using an interpreter or a compiler or a just-in-time compiler. An interpreter is for translation of the source code, whereby the translation at runtime of the Program at the time a command is processed. A compiler translates the source code in advance so that an efficient Program execution can take place. A just-in-time compiler translates the source code at program runtime, whereas in contrast to the interpreter the machine instructions generated from the source code are saved be so that they translated only once Need to become.

Another embodiment of the method according to the invention stipulates that the first attribute of the first data store together with a first Source code command that accesses the first data store, the Generation of a first machine instruction during translation causes a first boundary.

Another embodiment of the method according to the invention stipulates that it the first or second limit is a fence machine instruction acts or is a machine instruction that affects the effect a fence machine instruction. Fence-machine instructions or machine instructions, which show the effect of a fence machine instruction include are for known modern processors.

Another embodiment of the method according to the invention stipulates that it the first source code command or the second source code command is a memory read access that is one in the first or reads information stored in the second data memory or a memory write access acts, which writes information into the first or the second data memory.

For example, the source code command to access a signal field, the signal field can for example be used to ensure that everyone in the program before Access to the machine instructions arranged with the signal field Security are processed before the signal field has a signal value receives.

Another embodiment of the method according to the invention stipulates that during the translation and during the execution in a processing unit it is ensured that all source code commands are arranged before the first source code command, translated into machine instructions be in the machine instruction order before the first Machine instructions are arranged and it is ensured that all before the first machine instruction arranged machine instructions accomplished be placed before one after the first machine instruction Machine instruction executed becomes.

Another advantageous embodiment of the method according to the invention stipulates that during the translation and during the execution in a computing unit ensures that the first limit no visible reversal in the machine instruction order he follows.

Another advantageous embodiment of the method according to the invention stipulates that during the translation it is ensured that over the second No visible confusion in the machine instruction sequence across borders he follows.

This ensures that a visible Exchange of instructions about the border is excluded so that program parts are strictly separated can be. A visible swap involves swapping the processing order of machine instructions or the exchange of the Completion of the processing of a machine instruction for others Processors or processes becomes visible.

With regard to the computer system, the task is solved by a multi-processor system an execution environment with the features according to claim 9.

The multi-processor system according to the invention enables Exchange and parallel processing of instructions in an instruction memory are stored. This leads to an accelerated Processing of the instructions stored in a command memory, being by additional means it is ensured that the Resorting machine instructions is restricted in a predetermined manner. This enables that a Data inconsistency during processing of the instructions is avoided. Furthermore is provided that the Means only in translation restrict the reordering of machine instructions.

Furthermore, the task related to the multiprocessor system program product solved by a multi-processor system program product according to claim 10, which on a Multi-processor system-appropriate medium is stored and computer-readable Program funds include with which the steps according to one of claims 1 to 8 executed if the program product runs on a multiprocessor system.

Advantageous embodiments of the Invention are the subject of the respective subclaims.

The invention is explained below of embodiments and figures closer explained.

The figures show:

1 a source code with source code commands and machine instructions generated from the source code;

2 a computer system with a first computing unit, a first command memory and a data memory and a second computing unit with a second command memory;

In 1 is a source code 7 shown the source code commands 8th contains. The source code commands 8th are in an order of command 9 arranged. The source code 7 includes a data declaration 10 having a first data store 11 a first attribute 12 and a second data store 13 a second attribute 14 assigns. Additionally is in the source code 7 a first source code command 17 and a second source code command 20 arranged. Furthermore, in 1 a first instruction memory 4 shown in the machine instructions 15 in a machine instruction order 16 are arranged, with the machine instructions 15 from the source code commands 8th have been translated. Translation of machine instructions 15 from the source code commands 8th can be carried out on the one hand while the program is running. It is also possible for a compiler to execute the machine instructions before the program runs 15 generated, whereby an efficient processing of the computer program is possible. It is also possible for a just-in-time compiler to execute the source code commands 8th in the machine instructions 15 translated, whereby a translation can be carried out for the specific hardware of the computer system at program runtime.

In 2 is a computer system 1 shown. The computer system 1 comprises a first computing unit 2 and a second computing unit 3 , The first arithmetic unit 2 is with the first instruction memory 4 and the second arithmetic unit 3 is with a second instruction memory 5 connected. The first arithmetic unit 2 and the second arithmetic unit 3 are with a data store 6 connected. In the first instruction memory 4 are the machine instructions 15 in the machine instruction order 16 arranged.

In the data store 6 are a first data store 11 , a second data storage 13 and a third data store 25 arranged.

The machine instructions 15 include interchangeable machine instructions 23 as well as a first data access 24 that on the third data store 25 accesses. Below include the machine instructions 15 a first machine instruction 18 that have data access to the first data store 11 includes. The first machine instruction 18 includes a first boundary 19 since the first machine instruction 18 to the one with the first attribute 12 marked first data area 11 accesses. For example, include the interchangeable machine instructions 23 the calculation of a result, which is achieved by means of the first data access 24 in the third data store 25 is saved, it is necessary that by means of the first machine instruction 18 a signal value in the first data memory 11 is only registered when the first data access 24 the writing process in the third data memory 25 has ended.

This enables the second processor 3 those in the second instruction memory 5 arranged query machine instruction 26 to ensure that the data reading machine instruction executed in the following 27 Data read from the third data memory are valid. The order of the first data access 24 and the first machine instruction 18 is to be observed across all processors, so that when translating the source code 7 in the machine instructions 15 as well as when executing the first machine instructions 15 in the first processor 2 the interchangeability of the sequence is restricted. The first source code command 17 is, for example, in the first machine instruction 18 translated, taking into account that a in the first source code command 17 included access to the first data store 11 and the attribution of the first data store 11 with the first attribute 12 is taken into account.

It is also provided that the second Source Command 20 in a second machine instruction 21 is translated, which is also in the first command memory 4 is arranged. The second source code command 20 sees a memory access to the second data memory 13 before that with the second attribute 14 is marked. This ensures that during the translation of the source code commands 8th in the machine instructions 15 a second limit 22 next to the second machine instruction 21 is formed. The second frontier 22 stipulates that the exchange of machine instructions during the translation process is restricted in such a way that data consistency is guaranteed. This is the case, for example, when the first processor 2 exclusively on the second data storage 13 accesses. In this case, the first processor 2 an exchange during the runtime - also via the second machine instruction 21 formed border 22 addition - perform, provided the first processor 2 ensures that data consistency is maintained.

The second attribute 14 This is useful, for example, when an interrupt occurs between two instructions that are to be executed in a fixed sequence to one another. An error can occur here if the commands are swapped in their processing order, since the interrupt handler called by the interrupt can read out the data areas processed by the swapped commands for evaluation. A swap during the runtime within the processor can be recognized by modern processors, so that the premature storage of a signal date before the storage of a useful date can be recognized and corrected by the processor. However, if this exchange takes place during the translation, the order changed during the translation cannot be corrected by the processor. The possibility of swapping during the execution of the program increases the execution speed of the program code, since commands can be processed prematurely, for example, in a parallel execution unit of the processor.

1

computer system

2

first computer unit

3

second computer unit

4

first instruction memory

5

second instruction memory

6

data storage

7

Source code

8th

Source commands

9

Command Order

10

data declaration

11

first data storage

12

first attribute

13

second data storage

14

second attribute

15

machine instructions

16

Machine instruction sequence

17

first Source Command

18

first Computer instruction

19

first border

20

second Source Command

21

second Computer instruction

22

second border

23

interchangeable machine instructions

24

first data access

25

third data storage

26

Query machine instruction

27

Data read-machine instruction

Claims (9)

Method for controlling a multiprocessor system ( 1 ) where - a source code ( 7 ) with source code commands ( 8th ) that is created in a command order ( 9 ) are arranged; - where the source code ( 7 ) a data declaration ( 10 ) and the data declaration ( 10 ) a first data storage ( 11 ) a first attribute ( 12 ) and a second data storage ( 13 ) a second attribute ( 14 ) assigns; and - the source code ( 7 ) in machine instructions ( 15 ) is translated and the machine instructions ( 15 ) are rearranged so that the machine instructions ( 15 ) a machine instruction sequence ( 16 ) which depend on the order of commands ( 9 ) deviates; and - the machine instructions ( 15 ) in a command memory ( 4 ) are saved and processed by a computing unit ( 2 ) from the command memory ( 4 ) and different from the machine instruction order ( 16 ) from the computing unit ( 2 ) are executed; - where the first attribute ( 12 ) of the first data store ( 11 ) and the second attribute ( 14 ) of the second data storage ( 13 ) cause the reordering of the machine instructions ( 15 ) is restricted in translation in a first predetermined manner; and - where the first attribute ( 12 ) of the first data store ( 11 ) causes the reordering of the machine instructions ( 15 ) when executed in the computing unit ( 2 ) restricted in a second predetermined manner; and - where the second attribute ( 14 ) of the second data storage ( 13 ) causes a) that when executed in the computing unit ( 2 ) a reordering of the machine instructions ( 15 ) is not restricted; and b) that the second attribute ( 14 ) together with a second source code command ( 20 ) on the second data storage ( 13 ) accesses a second machine instruction ( 21 ) which creates a second limit ( 22 ) so that all source code commands that precede the second source code command ( 20 ) are arranged, are translated into machine instructions that are in the machine instruction order ( 16 ) before the second machine instruction ( 21 ) are arranged. Method according to claim 1, characterized in that the translation of the source code ( 7 ) in machine instructions ( 15 ) is carried out using an interpreter or a compiler or a just-in-time compiler. Method according to one of claims 1 or 2, characterized in that the first attribute ( 12 ) of the first data store ( 11 ) together with a first source code command ( 17 ) on the first data store ( 11 ) accesses, the generation of a first machine instruction ( 18 ) in translation that creates a first limit ( 19 ) forms. Method according to one of Claims 1 to 3, characterized in that the first limit ( 19 ) or the second limit ( 22 ) is a fence machine instruction or is a machine instruction that contains the effect of a fence machine instruction. Method according to one of Claims 1 to 4, characterized in that the first source code command ( 17 ) or the second source code command ( 20 ) is a memory read access, which is one in the first or the second data memory ( 11 . 13 ) reads out stored information or is a memory write access that stores information in the first or the second data memory ( 11 . 13 ) registers. Method according to one of claims 1 to 5, characterized in that during the translation and during execution in a computing unit ( 2 ) it is ensured that over the first border ( 19 ) no visible reversal in the machine instruction sequence ( 16 ) he follows. Method according to one of claims 1 to 6, characterized in that it is ensured during the translation that over the second limit ( 22 ) no visible reversal in the machine instruction sequence ( 16 ) he follows. Multi-processor system with an execution environment for executing the steps according to one of claims 1 to 7, - for which a source code ( 7 ) with source code commands ( 8th ) that is created in a command order ( 9 ) are arranged; - where the source code ( 7 ) a data declaration ( 10 ) and the data declaration ( 10 ) a first data storage ( 11 ) a first attribute ( 12 ) and a second data storage ( 13 ) a second attribute ( 14 ) assigns; and - the multiprocessor system ( 1 ) Has means to the source code ( 7 ) for execution by the multiprocessor system from the multiprocessor system in machine instructions ( 15 ) to translate, with the machine instructions ( 15 ) are rearranged so that the machine instructions ( 15 ) a machine instruction sequence ( 16 ) which depend on the order of commands ( 9 ) deviates; and - the machine instructions ( 15 ) in a command memory ( 4 ) for processing by a computing unit ( 2 ) are stored and the computing unit ( 2 ) Has means for exchanging the machine instruction sequence ( 16 ) are suitable; - the multiprocessor system ( 1 ) Has means which cause the first attribute ( 12 ) of the first data store ( 11 ) and the second attribute ( 14 ) of the second data storage ( 13 ) the reordering of the machine instructions ( 15 ) restrict translation in a first predetermined manner; and - the multiprocessor system ( 1 ) Has means which cause the first attribute ( 12 ) of the first data store ( 11 ) the reordering of the machine instructions ( 15 ) when executed in the computing unit ( 2 ) constrained in a second predetermined way while the second attribute ( 14 ) of the second data storage ( 13 ) the reordering of the machine instructions ( 15 ) when executed in the computing unit ( 2 ) allows. Computer program product that is on a computer-compatible medium is stored and includes computer-readable program means with which the steps according to one of claims 1 to 8 executed when the program product runs on a computer.