DE10060436A1 - Test device for high frequency testing of fast integrated circuits has low and high frequency communications connections, arrangement for producing and receiving high frequency test signals - Google Patents

Abstract

The device has connections for low frequency or LF signal communications with test equipment, especially for acquiring LF test signals such as data, control, address and clock signals, an arrangement for producing high frequency or HF test signals based on incoming LF test signals and second connections for HF signal communications with a circuit under test, especially for outputting HF test signals and receiving response signals from the circuit. The device has first connections (32a,32b) for low frequency signal communications with a test equipment (40), especially for acquiring low frequency test signals such as data, control, address and clock signals, an arrangement (38) for producing high frequency test signals based on incoming low frequency test signals and second connections (34a-34d) for high frequency signal communications with a circuit under test (52), especially for outputting high frequency test signals and receiving response signals from the circuit.

Description

The present invention relates to a test device for High frequency test of fast integrated circuits.

Today's DRAM (Dynamic Random Access Memory) chips are used costly memory test systems. On this Te Test programs for checking the functions become a star Suitable for the memory chips. In doing so Defi signals with precisely defined voltage levels nated times at the semiconductor circuit to be tested created. While checking the reading function of the It is also possible for DUT to send Si coming from the DUT signals into the test device at precisely defined times read and compare with expected signal values.

Because of the high frequencies at which today's storage construction working stones, e.g. B. 200 to 300 MHz with DDR (Double Data Rate) DRAMs and 400 to 800 MHz are required for Rambus DRAMs the specification of these chips high accuracy of the signals. For example, for DDR memories there are signal specifications 500 ps are already common today. The The production or storage test systems used must be there The highest technical requirements meet what ent leading to high production and test costs. Gegenwär tig cost DRAM test devices that meet the above conditions fulfill several million dollars each. All of this leads to the fact that the test costs for high frequency memory modules already account for up to 30% of the manufacturing costs.  

Function test of the memory modules can be found on both Wafer level, as well as after the separation at the block level instead of. Today, rela is usually used at the wafer level tiv low frequency ranges from about 10 to 100 MHz basic function of the memory chips checked. The higher Frequent tests are then carried out in housed after assembly Condition on special module testers instead.

In principle, it would be desirable to be at the wafer level High-speed test on the memory chips lead, because then the function test leads to an added value From a technical point of view, there is a great time There is potential for cost savings.

However, high frequency tests at the wafer level are now only borders possible, mainly on the large geometric Dimensions of the test arrangement lies. From pin electronics the tester over the test head, the needle card arrangement to dimensions for the building block to be tested are of the order of magnitude bridge 10 cm to 1 m. This is at frequencies from 200 MHz to 1 GHz with sufficient accuracy and high Parallelism practically impossible.

This is where the invention comes in. The invention, as in the Is characterized, the task is based a test facility for testing fast integrated switching circles to provide the radio frequency tests also on Wa ferebene in a simple and inexpensive manner. This object is achieved by the test facility gene according to claim 1 or 6 and the use according to claim 7 or 8 solved.  

According to the invention, a test device for high-frequency testing of fast integrated circuits, in particular semiconductor memory modules, has a semiconductor circuit which is arranged on a supporting element and which comprises

• - First connections designed for low-frequency signal communication communication with a test device, especially for recording low-frequency test signals such as data, control, address and Clock signals
• - Means for generating high-frequency test signals based incoming low-frequency test signals from the test device, and
• - Second connections designed for high-frequency signal communication nication with a circuit to be tested, in particular for Delivery of the high-frequency test signals and for recording the response signals generated by the circuit under test.

The invention is therefore based on the idea between the Test system and the circuit to be tested another Insert semiconductor circuit that from the relatively long active, low-frequency test signals from the test device Frequent test signals for high-speed tests of the test block generated. This other semiconductor Circuit is called a BOST (Built Outside Self Test) block referred to and can advantageously out as an ASIC circuit leads.

During a variety of circuits to be tested on one Wafers can each be assigned a BOST module several BOST blocks from the same standard Tester channel can be controlled, reducing the parallelism can be massively increased during testing. The Redu continues adornment of the test steps by merging the previous steps  Functionality check at wafer level with the high speeds to test the building blocks at the production level cost savings.

With this concept, the BOST module is used according to the invention equipped two different interfaces, namely on the one hand with connections that are suitable for the low-frequency Si communication with the test system are designed, esp especially for recording low-frequency test signals such as for example data, control, address and clock signals. Dar in addition, the BOST module has second connections, on high-frequency signal communication with the te constant circuit are designed, in particular for delivery the high-frequency test signals and to record the from test circuit generated response signals.

This has the further advantage that the flexibility used conventional, low-frequency test systems and at the same time high frequency on the circuit under test can be accessed.

In a preferred embodiment, this is the BOST building block load-bearing element directly formed by a printed circuit board. al ternative is the load-bearing element through a carrier plate, preferably a ceramic support plate formed with a circuit board is connected. This enables, in particular when using a variety of BOST modules et wa in a needle card, the orientation of the BOST building blocks precisely set relative to a wafer surface.

In the latter embodiment, the BOST Component on a circuit facing away from the circuit to be tested  Surface of the support plate arranged. The carrier plate has connections to the high-frequency signal communication tion are designed with the circuit to be tested, and the connected to the second connections of the BOST module are. This arrangement makes the test device robust and not only for wafer level testing but also good for Suitable for high-speed tests at the block level.

The second connections of the test device can be contacted Have needles for high-frequency signal transmission. This transmit the time critical signals between the BOST Module and the circuit to be tested in the shortest possible way and are still mechanically stable and re-contactable.

According to the invention, a test device has a parallel High frequency test of a plurality of faster integrated Circuits, especially semiconductor memory devices, a Most of the test facilities described. By pa Parallel measurement can be carried out, especially when testing Wa level of time for the high-frequency tests clearly lower and make it acceptable for production environments.

It is advantageous to use a test stone as described Direction in a test system for high-frequency testing faster integrated circuits, in particular semiconductor memories building blocks, at the wafer level. As mentioned, the reduction leads the test steps by merging the previous functions Quality check at wafer level at high speed Tests at block level in production at considerable cost steneinsparungen.  

A test device described can also be advantageous Integrate faster in a test system for high-frequency testing ter circuits, in particular semiconductor memory modules, can be used at the block level. Such tests are already possible today with high-frequency test equipment, however, the invention allows through the frequency transform tion of the BOST module is slower and therefore cheaper Test devices can also be used for testing at block level.

Further advantageous configurations, features and details the invention emerge from the dependent claims, the Description of the embodiments and the drawings.

The invention is described below with reference to an embodiment game explained in connection with the drawings become. It is only for understanding the Er essential elements shown. It shows

Fig. 1 is a schematic representation of an embodiment of the invention;

Fig. 2 is a schematic representation of another embodiment of the invention;

Fig. 3 is a schematic representation of a further embodiment of the invention;

Fig. 4 is a schematic representation of yet another embodiment of the invention;

Fig. 5 is a perspective schematic view of another embodiment of the invention;

Fig. 1 shows a schematic representation of a test system 10 having mounted on a printed circuit board 20 has been executed as an ASIC BOST (Build Outside Self Test) module 30th

Test signals of a test system 40 which is relatively slow at 10 to 100 MHz reach signal connections 42 to connections 22 a, 22 b of printed circuit board 20 . From there, they are led, for example, via conventional bond wires to connections 32 a, 32 b of the BOST module. To protect the bond wires, these could be cast with an epoxy, for example. In the guide plate 20 , the signal lines are unbundled and shielded against one another.

The high-frequency terminals 34 a- 34 d of the BOST block are mechanically partially flexible contacting needles 36 a- 36 d provided which establish a radio-frequency, mechanically stable and wiederkontaktierbare electrical connection to the test circuit 52nd

In the embodiment of FIG. 1, the circuit 52 to be tested is one of a multiplicity of memory modules to be tested located on a wafer 50 . The wafer 50 itself is located on an adjustable chuck, not shown.

In test mode, the BOST module 30 is arranged with the contacting needles 36 a- 36 d directly above the memory device 52 to be tested and a releasable electrical contact is made with the corresponding connection pads of the memory module 52 . The low-frequency test signals of the test system 40 , in particular data, control, address and clock signals, go over the connections 32 a, 32 b to the BOST module 30 .

This has, inter alia, a signal generator 38 which generates the test system based on the slow test signals 40 internal fast signals, which are then a- via the high-frequency terminals 34 are submitted 34 d to the stone to be tested Speicherbau 52nd

After the test of the memory module 52 , the detachable electrical connection is disconnected and the BOST module 30 is available for testing a further memory module.

The number of connections was limited in the schematic representation of FIG. 1 only for the sake of clarity to two low-frequency connections 32 a, 32 b and four high-frequency connections 34 a- 34 d. In practice, the number of connections is significantly larger and generally determined by the number of connections of the circuit to be tested.

Another embodiment is shown in FIG. 2. The BOST module 30 is not attached directly to a printed circuit board, but rather is mounted on a ceramic carrier plate 60 , for example ceramic, which in turn is connected via screw connections 80 at an adjustable distance to a printed circuit board 70 . On the one hand, this improves the dissipation of the heat loss generated in the BOST module 30 and, on the other hand, allows the orientation of the BOST module to be set precisely.

The BOST module 30 can, as shown in FIG. 2, be mounted on the surface 64 of the carrier plate 60 facing away from the module to be tested. This is a robust design that is well suited for both testing circuits 52 at the wafer level and testing circuits 54 at the device level. The carrier plate has in this case down to the circuit 52 , 54 to be tested, connections 62 a- 62 d for high-frequency signal communication with the circuit 52 , 54 to be tested, which with the connections 34 a- 34 d of the BOST module the carrier plate 60 are connected through. The low-frequency signal lines are in Fig. 2 on the carrier plate (Be reference 68 ) to the circuit board 70 to 72 connections .

The BOST module 30 can also indicate with its upper side to the carrier plate 60 . The electrical contact can then be achieved by high-frequency contact balls 90 (fine grid ball array) ( FIG. 3).

Alternatively, the BOST module 30 , as shown in FIG. 4, is mounted on the surface 66 of the carrier plate 60 facing the module to be tested.

The test device 100 shown schematically in FIG. 5 has a 3 × 3 array of BOST components 30 on a ceramic carrier plate 60 in an arrangement corresponding to FIG. 3. The connection of the carrier plate 60 to the printed circuit board, on which the shielding and unbundling of the signal lines is carried out, and the individual connections of the BOST modules are not shown. With the test device 100 , it is possible to test nine memory modules 152 , for example the nine memory modules defined by the border 154 , on a wafer 150 at the same time. After the test has been carried out, the test device and the wafer are separated again, and the wafer is shifted in its position until the next nine memory modules are located under the corresponding BOST modules 30 . It is immediately apparent that a time saving on the order of a factor 9 is achieved by the parallel testing.

Of course, the arrangement according to the invention is not limited to an array of 3 × 3 BOST blocks, but any other n × m array arrangements are also included n, m ≧ 1 in the context of the present invention. With increasing The number of * * BOST blocks increases the parallelization and thus the time saved compared to a sequential Testing the building blocks.

If instead of a circuit 52 on a wafer an already isolated module 54 is contacted, the module to be tested occurs instead of the wafer to be tested on an adjustable chuck, which can be mechanically positioned and held by a handler system. A BOST module can then be integrated in a single test socket. Here too, however, the parallel measurement of many modules is inexpensively possible by providing a corresponding number of BOST modules, for example in a so-called Hifix board.

Claims (8)

1. Test device for high-frequency test of fast integrated circuits, in particular semiconductor memory modules, with a semiconductor circuit ( 30 ) arranged on a supporting element ( 20 ; 60 ), which comprises
first connections ( 32 a, 32 b) designed for low-frequency signal communication with a test device ( 40 ), in particular for receiving low-frequency test signals such as data, control, address and clock signals,
Means ( 38 ) for generating high-frequency test signals based on incoming low-frequency test signals from the test device, and
second connections ( 34 a- 34 d) designed for high-frequency signal communication with a circuit to be tested ( 52 ; 54 ), in particular for delivering the high-frequency test signals and for receiving the response signals generated by the circuit to be tested ( 52 ; 54 ). 2. Test device according to claim 1, wherein the supporting element is formed by a printed circuit board ( 20 ). 3. Test device according to claim 1, wherein the supporting element is formed by a carrier plate ( 60 ), preferably as a ceramic carrier plate which is connected to a printed circuit board ( 70 ). 4. Test device according to claim 3, wherein the semiconductor circuit ( 30 ) is arranged on a surface facing away from the circuit to be tested ( 62 ) of the carrier plate ( 60 ), and the carrier plate ( 60 ) connections ( 62 a- 62 d) designed for High-frequency signal communication with the circuit to be tested ( 52 ; 54 ), which are connected to the second connections ( 34 a- 34 d) of the semiconductor circuit ( 30 ). 5. Test device according to one of claims 1 to 4, wherein the second connections ( 34 a- 34 d) contacting needles ( 36 a- 36 d) for high-frequency signal transmission. 6. Test device for parallel high-frequency test of a plurality of fast integrated circuits, in particular semiconductor memory modules, with a plurality of test devices ( 10 ) according to one of claims 1 to 5. 7. Use of a test device according to one of the claims 1 to 6 faster in a high-frequency test system integrated circuits, in particular semiconductor memories building blocks at the wafer level. 8. Use of a test device according to one of the claims 1 to 6 faster in a high-frequency test system integrated circuits, in particular semiconductor memories building blocks at building block level.