DE10056295A1 - Production of a ferroelectric capacitor used in the production of highly integrated non-volatile storage capacitors, especially FeRAMs, comprises inserting a dielectric between precious metal electrodes - Google Patents

Abstract

Production of a ferroelectric capacitor comprises inserting a ferroelectric or para-electric material as dielectric (6) between precious metal electrodes (3, 4) of the capacitor (1); and depositing a TaSixNy layer as hydrogen diffusion barrier (7) over the capacitor to protect the ferroelectric or para-electric material from hydrogen used in the integration process. An Independent claim is also included for a highly integrated non-volatile storage capacitor. Preferred Features: The TaSixNy layer is structured so that it lies between an electrode plate of the capacitor and a Ti/TiN barrier layer in a neighboring through-hole filled with tungsten.

Description

The invention relates to a method for producing a ferroelectric capacitor especially in highly integrated ten non-volatile semiconductor memories, a ferroelek trical or paraelectric material as dielectric between electrodes made of precious metal of the capacitor is used and with a water above the condenser fabric diffusion barrier to protect the ferro- or paraelek tricum before hydrogen used in the integration process is deposited.

In the manufacture of ferroelectric capacitors for applications in non-volatile semiconductor memories with high integration density, a ferroelectric material, e.g. B. SrBi ₂ (Ta, Nb) ₂ O ₉ (SBT or SBTN), Pb (Zr, Ti) O ₃ (PZT) or Bi ₄ Ti ₃ O ₁₂ (BTO) are used as dielectric between the plates of a capacitor. Paraelectric materials, such as. B. (Ba, Sr) TiO ₃ (BST) can be used. The plate material is a precious metal that can withstand high temperatures in O ₂ . As plate materials such. B. Pt, Pd, Ir, Rh, Ru, Os in question. In general, either the stack principle or the offset cell principle is pursued in the construction of the capacitor, which is not technologically so demanding, but still requires more space.

Both methods are used to integrate the capacitors Process steps necessary in a hydrogen-containing environment exercise take place. These lead to reduction reactions degradation of the ferroelectric layer. So z. B. for conditioning the metallization and the transistors of a ferroelectric memory chip Forming gas necessary (95% N2, 5% H2), which is proven to deterioration in electrical properties increased leakage current, short circuits, lower polarization and  for the deterioration of the structural properties (Pee ling) of the storage capacitors. Further z. B. the Deposition of intermediate oxides, silicon nitride passivation, Tungsten plugs due to their high hydrogen content Deposition as well as damage in the layer itself of the ferroelectric or paraelectric.

To protect the ferroelectric or paraelectric from hydrogen zen, is therefore usually above the capacitor module Hydrogen diffusion barrier (English encapsulation barrier layer, abbreviated EBL). Here come mainly materials that contain hydrogen themselves ten (SiOxNy: H, SiNy: H,...) or at least during the Ab damage caused by hydrogen in the process gas cause (silane, ammonia,...).

All currently commercially available products with ferroelectric layers and a storage density of just a few kb have a pure Al metallization. Such an Al metallization is unsuitable for higher storage densities, which necessitate metallization with tungsten in the contact holes or vias. Furthermore, an AlOx layer or a TiOx or TiON layer or a layer of ZrOx is known as the H ₂ barrier above the capacitor. However, all of these materials have the disadvantage that they are difficult to etch.

It is therefore an object of the invention, a generic Process for producing a ferroelectric condenser tors especially in highly integrated non-volatile half ladder storage to indicate which damage to the Fer can prevent roelektrikums by hydrogen and the same good etchability of the hydrogen diffusion used barrier achieved. Another task is a ferroe Specify dielectric semiconductor memory device that with the The method according to the invention can be produced.  

This task is solved according to the requirements.

According to an essential aspect of the invention, a TaSi _x N _y layer is deposited either directly on the capacitor module or first a buffer layer or a buffer layer system and then the TaSi _x N _y layer thereon. Since TaSi _x N _{y has} barrier properties against hydrogen diffusion, it is very well suited to prevent damage to the ferroelectric or paraelectric during or after the deposition. Such TaSi _x N _y barrier layer is good to be etched.

TaSi _x N _y is usually reactively sputtered from a TaSi target into N2. So there is no hydrogen pollution during or after the deposition through the barrier layer.

Many known hydrogen barriers must e.g. B. are annealed in oxygen to fully develop their barrier properties. This increases the thermal budget. B. may cause undesirable effects in the previously manufactured transistors of a ferroelectric semiconductor memory. In addition, oxygen tempering can lead to an additional load for a possibly used oxygen barrier under the capacitor module. If, as proposed in the present invention, only TaSi _x N _y as a barrier, this tempering is completely eliminated.

Since TaSi _x N _{y has} a thermal expansion coefficient similar to that of silicon, only a bearable stress is generated when exposed to temperature. This means the mechanical stress, which is temperature-dependent.

Since the TaSi _x N _{y is} conductive, it must e.g. B. around vias and Kon contact holes and where it was deposited on the substrate, recessed or removed. Otherwise the TaSi _x N _y barrier would be a possibly unwanted electrical connection e.g. B. between vias and contact holes or between rule's top electrode and bottom electrode.

In a first method, the TaSi _x N _y barrier layer can be structured by introducing an additional lithography layer. Alternatively, the TaSi _x N _y barrier layer can also be structured simultaneously with the ferroelectric or paraelectric and the top electrode of the capacitor.

Another alternative possibility is the structuring of TaSi _x N _y barrier layer with a planar etch, such as CMP.

A further advantage of the material used for the hydrogen barrier layer TaSi _x N _y is its barrier property to Ti-diffusion. The vias to the top and bottom electrodes are usually filled with tungsten. Since the adjacent SiO _{2 is} heavily attacked by WF ₆ during the deposition of the W plugs, a Ti / TiN barrier layer (liner) is usually applied before the deposition of tungsten. Parts of the Ti / TiN barrier layer serving as a liner can diffuse into the top or bottom electrode, where the barrier properties deteriorate and efflorescence can result from the reaction of WF ₆ with SiO ₂ z. B. come through a leaky liner on such a via.

If the TaSi _x N _y , which primarily serves as a hydrogen barrier, is also separated between the electrode and liner, the Ti diffusion into the electrode is prevented and the barrier properties of the Ti / TiN liner and efflorescence are prevented. However, it should be mentioned that this advantage can be achieved not only by a TaSi _x N _y layer but also by other layers or layer systems which are conductive and have barrier properties with respect to Ti.

The invention will now be described with reference to the lying drawing figures embodiments explained in more detail.

Fig. 1A schematically shows an embodiment of a three-dimensional structure in the process he realized inventive ferroelectric capacitor 1 and

FIG. 1B shows details within the area B framed by a circle in FIG. 1a .

Referring to Fig. 1A consists of ferroelek tric capacitor 1 of the invention from a top electrode 3, z. B. from tin and a bottom electrode 4 and an intermediate ferroelectric or paraelectric 6 (z. B. from SBT). The bottom electrode 4 can be buffered with a buffer layer 5 or a buffer layer system made of Ti / TiN with respect to an underlying layer.

According to the invention for the protection of ferrous or Paraelektri Kums 7 from TaSi _x N _y is 6 abge before used in the integration process hydrogen across the capacitor 1, a hydrogen diffusion barrier (EBL engl. Encapsulation barrier layer,) secreted. As a result, there is no hydrogen load on the ferroelectric capacitor during or after the deposition through the barrier layer. In addition, the temperature is completely eliminated if only TaSi _x N _{y is used} as the barrier material. The fact that TaSi _x N _{y has} a thermal expansion coefficient similar to that of silicon creates only a tolerable stress.

TaSi _x N _y is conductive. The TaSi _x N _y layer 7 is therefore structured after its deposition in such a way that it either remains recessed around vias 8 or contact holes and around exposed regions of the substrate 10 or is removed. Fig. 1A clearly shows that the TaSi _x N _y layer 7 is pulled down so far that it also covers the side edges of the top electrode 3 and the ferroelectric or paraelectric 6 .

The vias 8 ( FIG. 1A shows a via 8 to the top electrode 3 and a via to a transistor electrode in a lower-lying metallization) are usually filled up with tungsten W. Since the adjacent SiO _{2 is} strongly attacked by WF ₆ during the deposition of the tungsten plugs, a Ti / TiN barrier layer (Liner L) is applied before the tungsten deposition. Fig. 1B shows the details in the bottom area of the via 8, ie in the vicinity of the top electrode. 3 In usual Lich construction parts of the liner 9 could diffuse into the top electrode 3 . This would deteriorate the barrier properties of the liner 9 , which can lead to efflorescence. However, this is avoided by the hydrogen diffusion barrier layer 7 consisting of TaSi _x N _y . Since this TaSi _x N _y barrier layer 7 is deposited between the top electrode 3 and the liner 9 , the Ti diffusion into the electrode is prevented. Furthermore, since the TaSi _x N _y layer 7 is conductive, good electrical contact between the wolf ramplug 8 and the top electrode 3 is achieved. Fig. 1B clearly shows that the thickness of the deposited liner 9 a on the Bo of the vias is relatively thin. However, this is not harmful since the conductive TaSi _x N _y layer 7 with Ti barrier property is already deposited on the bottom of the via 8 . Therefore, the Ti / TiN liner layer 9 is not required at all. Against the dilution of the liner 9 to the side walls of the vias 8, TaSi _x N _y layer 7 does not help unfortunately.

In the manufacture of such a ferroelectric Kon densators the inventively provided TaSi _x N _y can - barrier layer 7 are patterned with an additional lithography step. Alternatively, the structuring of the TaSi _x N _y barrier layer 7 can also be carried out simultaneously with the structuring of the ferro- or paraelectric 6 and the top electrode 3 of the ferroelectric capacitor 1 .

LIST OF REFERENCE NUMBERS

1

Ferroelectric capacitor

3

.

4

electrode plates

5

protective layer

6

Ferro or paraelectric

7

TaSi _x

_Ny

-Layer

8th

tungsten plug

9

Ti, TiN liner

10

substratum
L liner
W tungsten

Claims (10)

1. A method for producing a ferroelectric condenser, in particular in highly integrated, non-volatile semiconductor memories, wherein a ferroelectric or para-electrical material is used as a dielectric ( 6 ) between electrodes made of noble metal ( 3 , 4 ) of the capacitor ( 1 ) and wherein the capacitor ( 1 ) a hydrogen diffusion barrier ( 7 ) for protecting the ferro- or pa raelectric ( 6 ) is deposited from hydrogen used in the integration process, characterized in that as a hydrogen diffusion barrier (EBL) a TaSi _x N _y layer ( 7 ) over the capacitor is deposited. 2. The method according to claim 1, characterized in that a structuring step structures the TaSi _x N _y layer ( 7 ) in such a way that it is spared or removed around vias and contact holes and on exposed substrate regions. 3. The method according to claim 1 or 2, characterized in that a structuring step structures the TaSi _x N _y layer ( 7 ) such that it also between an electrode plate ( 3 ) of the capacitor ( 1 ) and a Ti / TiN barrier layer ( 9 ) is located in an adjacent via filled with tungsten. 4. The method according to any one of claims 1 to 3, characterized in that the TaSi _x N _y layer ( 7 ) is reactively sputtered from a TaSi target in an N ₂ atmosphere. 5. The method according to any one of claims 1 to 4, characterized in that the structuring step for structuring the TaSi _x N _y layer ( 7 ) is an additional lithography step. 6. The method according to any one of claims 1 to 4, characterized in that the structuring step structures the TaSi _x N _y layer ( 7 ) simultaneously with the ferroelectric or paraelectric and the top electrode of the ferroelectric capacitor. 7. The method according to any one of claims 1 to 4, characterized in that the structuring step structures the TaSi _x N _y layer ( 7 ) by a planar etching process, such as CMP. 8. Use of the method according to one of claims 1 to 7 for the production of a non-volatile semiconductor memory chers, especially FeRAMs. 9. Integrated ferroelectric semiconductor memory arrangement, in which a ferroelectric or paraelectric material is used as a dielectric ( 6 ) between electrodes ( 3 , 4 ) of a capacitor ( 1 ) of each storage cell consisting of noble metal and via the capacitor ( 1 ) a hydrogen diffusion barrier ( 7 ) to protect the ferro- or para-electric ( 6 ) from hydrogen, characterized in that the hydrogen diffusion barrier (EBL) is a TaSi _x N _y layer ( 7 ). 10. Integrated ferroelectric semiconductor memory arrangement according to claim 9, characterized in that the TaSi _x N _y - layer ( 7 ) also between an electrode plate ( 3 ) of the capacitor ( 1 ) and a Ti / TiN barrier layer ( 9 ) in an adjacent via lies.