DE10051173C2 - Arrangement and method for reducing the voltage drop along a word line / bit line of an MRAM memory - Google Patents

Abstract

The invention relates to an arrangement and a method for reducing the voltage drop along a word line / bit line of an MRAM memory, in which a selected word line / bit line is connected to the same potential at both ends.

Description

The present invention relates to an arrangement and a Method for reducing the voltage drop along an egg ner word line / bit line when reading one in a memory memory cell array of an MRAM memory le, the at the crossing point of a selected word line with is located on a selected bit line, according to the Oberbe handle of claim 1 or 2.

As is known, information is stored in an MRAM cell (MRAM = magnetoresistive read / write memory) by changing the volume resistance R _{Z of} the cell. An MRAM cell consists of a hard magnetic layer, a tunnel barrier layer and a soft magnetic layer. With parallel magnetization direction of the soft magnetic layer and the hard magnetic layer, the volume resistance R _{Z of} the cell is smaller than with its anti-parallel magnetization direction. The direction of magnetization in the soft magnetic layer can be set parallel or anti-parallel to the direction of magnetization in the hard magnetic layer by sending currents in the corresponding direction through the associated word and bit lines.

A high volume resistance, i.e. an anti-parallel one Magnetization of the two magnetic layers, so For example, a logical "1" can be assigned while a low volume resistance, i.e. an anti-parallel one Magnetization of the two magnetic layers, then one logical "0" means. The assignment of the information content "0" or "1" can of course also be reversed.  

Fig. 6 shows schematically an MRAM cell Z at the intersection of a word line WL with a bit line BL, here this cell Z, which actually consists of a soft magnetic layer, a tunnel barrier layer and a hard magnetic layer, which lies between the word line WL and the bit line BL are stacked at their crossing point, is schematically illustrated by a resistor R _Z. If the word line WL is supplied with a voltage V _WL and the bit line BL with a voltage V _BL , then a certain voltage V _Z is present at the MRAM cell, which is given by V _Z = V _WL - V _BL . A certain current I _Z = V _Z / R _{Z then flows} through the MRAM cell. This current I _Z can be measured in order to determine the storage state of the cell, that is to say a high or low volume resistance R _Z.

In practice, the chip required for this measurement The drop in voltage across the cell is achieved by the word line WL of this cell brought to a certain potential is, while the bit line BL belonging to the cell on ei leave another, e.g. lower potential becomes.

It should now be considered that a memory cell array of an MRAM, which is also referred to as an MRAM array, forms a resistance network in which parasitic currents flow through each cell to which a voltage is applied. In addition, a voltage drop arises along each word line and each bit line due to their respective line resistance, which ultimately results in different cell currents I _Z through the individual memory cells and can cause read errors.

WO 99/14760 describes a memory cell arrangement and de Use as magnetic RAM and as associative Known memory. In this memory cell arrangement all word lines and bit lines including the selected ones  Bit line, but with the exception of the selected word line, or include all word lines and bit lines Lich the selected word line, but with the exception of the se selected bit line, at one end to a predetermined one first potential. The selected word line or Bit line is used in this known memory cell arrangement placed on a second potential, compared to the first Potential is higher. For example, the second pot tial have a voltage of 1 V, while the first Po has potential 0 V.

Fig. 7 shows a memory cell array of word lines WL0, WL1,. , , WL4 and bit lines BL0, BL1,. , ., BL4, at the intersection of which cells Z00, Z01, Z02,. , ., Z44 are the. It is now assumed that the cell Z22 is to be read out at the intersection of the word line WL2 with the bit line BL2. A voltage V2 is then applied to the word line WL thus selected, while a voltage V1 (V2 <V1) is applied to all other word lines WL0, WL1, WL3 and WL4. Similarly, the voltage V1 is applied to the selected bit line BL2, while all the other bit lines BL0, BL1, BL3 and BL4 are at the voltage V2.

In this arrangement, the word lines WL0, WL1, WL3 and WL4 and the bit line BL2 are at the potential of the voltage V1, while the voltage V2 is present on the bit lines BL0, BL1, BL3 and BL4 and on the word line WL2. This means that a voltage drop V _Z22 = V2 - V1 only occurs at cell Z22 on the two selected lines WL2 and BL2, while the other cells Z02, Z12, Z32, Z42 and Z20 connected to these selected lines WL2 and BL2, Z21, Z23 and Z24 experience a voltage drop "0", so that V _Z02 = 0, V _Z12 = 0, V _Z32 = 0, V _Z42 = 0, V _Z20 = 0, V _Z21 = 0, V _Z23 = 0 and V _Z24 = 0 apply.

In other words, for the selected word and bit lines all parasitic currents are eliminated here since al ln the desired cell Z22 a voltage between the Word line WL2 and the bit line BL2 arises, which the Reading current caused.

A disadvantage of the arrangement of FIG. 7, however, is that during the entire reading process, a voltage V1-V2 is present on all cells that are not on the selective word line WL2 or on the selected bit line BL2, each of which has a parasitic current Ipar, which flows through cells Z00, Z01, Z03, Z04, Z10, Z11, Z13, Z14, Z30, Z31, Z33, Z34, Z40, Z41, Z43 and Z44 and is indicated schematically by an arrow in front of the resistance symbol. The sum of these parasitic currents causes the power loss in the memory cell array shown to increase considerably, so that an arrangement with a reduced voltage drop along the word lines / bit lines when reading a memory cell array is desired.

It is therefore an object of the present invention to provide an arrangement voltage and a method for reducing the voltage drop along a word line / bit line when reading one in one Memory cell array of an MRAM memory arranged Spei to specify the cell.

The present invention provides a solution to this problem ne arrangement with the features of claim 1 or a method with the features of claim 2 before.

In the arrangement according to the invention or in the Invention According to the method, different lines of the MRAM Memory cell array placed at different voltages to the parasitic currents both in the memory cell array as a whole as well as directly on the selected word or bit lines to minimize. In addition, a selected word line / bit line  powered from both sides where minimized by the voltage drop across this line that can.

The invention will be described in more detail below with reference to the drawings explained. Show it:

Fig. 1 a memory cell array for explaining an underlying the inventive concept

Fig. 2 is a word line WL2 of Fig. 1 in detail,

Fig. 3 shows the profile of the voltage drop along the word line WL2 of Fig. 2,

Fig. 4, the word line WL2 of Fig. 1 with the power supply according to the invention from both sides and

Fig. 5 shows the course of the voltage drop along the word line of Fig. 4.

Corresponding components are shown in the figures provided with the same reference numerals.

FIG. 1 shows an arrangement of an MRAM memory cell array with which the high power losses of the memory cell array from FIG. 7 can be avoided. It is again assumed here that cell Z22 should be read out at the intersection of word line WL2 with bit line BL2.

In the concept on which the arrangement of FIG. 1 is based, only the word line WL2 is connected to the voltage V2, while all other word lines WL0, WL1, WL3 and WL4 and all bit lines BL0 to BL4 are connected to the voltage V1. First of all, this has the advantage that a voltage drop "0" occurs at all cells except the cells connected to the word line WL2, so that V _Z = 0 applies to these cells.

It should be noted that by activating the bitlei BL0 to BL4 Sense Amplifiers (sense amplifiers)  every desired memory cell with corresponding itself who is on the voltage V2 word line driven that can.

The problem now arises in the arrangement shown in FIG. 1 that parasitic currents flow through each cell Z20, Z21, Z22, Z23 and Z24 along the selective word line WL2. With n cells on a word line WL, the total current I _WL that flows into a selective word line, for example into the word line WL2, is therefore n times as high as in the memory cell array of FIG. 7. There is therefore a relationship I. _WL = n × I _Z before. In other words, a parasitic current I _par = I _Z also flows through the cells Z20, Z21, Z23 and Z24, this current I _{Z being} the current flowing through the selective cell Z22.

The line resistance of the word line and the high word line current I _WL result in a voltage drop .DELTA.V _WL across the word line WL2, as is illustrated in FIG. 2. Here R _{L means} the resistance value of each section of the word line WL between individual bit lines BL0, BL1,. , ., BL4. So that over each cell Z20, Z21,. , ., Z24 along the word line WL2 receive a different voltage V _Z and thus a different cell current, as illustrated in FIG. 3, in which the voltage on the word line WL is plotted over its length. For example, if cell Z20 is to be read out, a much higher current is obtained than when cell Z24 is read out. This difference in the reading current can cause reading errors.

In order to keep the voltage drop on the word line WL2 as low as possible, as is illustrated in FIGS . 4 and 5, both ends of this word line are brought to the high voltage V2. The voltage curve illustrated in FIG. 5 is thus obtained over the length of the word line WL2. As a comparison with FIG. 3 shows, the maximum voltage drop along the word line WL2 is reduced to about 1/4 in comparison to the word line WL2 from FIG. 3. In other words, by clamping the word line at both ends to a predetermined potential, the voltage drop across the word line is reduced, which reduces parasitic currents and prevents reading errors due to cell currents that differ greatly from one another.

Clamping the voltage on both ends of a line can also be on a bit line or on word line and bit line are used in a memory cell array. The means the invention is not limited to one MRAM the tension at both ends of a selective word sequence to clamp. Rather, it is also possible when reading for bit lines, the voltage at both ends hold. It can also be thought of in an MRAM when reading the voltages of selected word lines and to clamp selective bit lines at their ends.

Claims (2)

1. Arrangement for reducing the voltage drop along a word line (WL) / bit line (BL) when reading a memory cell (Z22) which is arranged in a memory cell array of an MRAM memory and which at the intersection of a selected word line (WL2) with a selected bit line (BL2) ge, where:

• a) all word lines (WL) and bit lines (BL) including the selected bit line, but with the exception of the selected word line, or
• b) all word lines (WL) and bit lines (BL) including the selected word line, but with the exception of the selected bit line,

at one end are connected to a predetermined first potential (V1)
characterized in that the selected word line or bit line is connected at both ends to a specific second potential (V1) which is higher than the first potential. 2. Method for reducing the voltage drop along a word line (WL) / bit line (BL) when reading a memory cell (Z22) which is arranged in a memory cell array of an MRAM memory and which at the intersection of a selected word line (WL2) and a selected bit line (BL2) ge, where:

• a) all word lines and bit lines including the selected bit line, but with the exception of the selected word line, or
• b) all word lines (WL) and bit lines (BL) including the selected word line, but with the exception of the selected bit line,

at one end are placed on a predetermined first potential (V1),
characterized in that the selected word line or bit line is connected at both ends to a specific second potential (V2) which is higher than the first potential (V1).