DD286072A5 - SATELLITE RUNDFUNKEMPFAENGER - Google Patents

Abstract

A satellite radio receiver obtains signals from a satellite receiving installation comprising one or more frequency converters which may, for example, undergo a frequency drift as a result of temperature variations which cannot be compensated by an AFC circuit which is located in the satellite radio receiver and which controls a carrier oscillator for carrier regeneration in a demodulator circuit. According to the invention, a local oscillator for a mixer is designed as a PLL local oscillator (44) which can be tuned in a large or a small increment. The AFC circuit (1) and a synchronizing signal evaluation circuit (40) are corrected to a control circuit (34) by means of which the PLL local oscillator (44) is tuned, outside the control range of the AFC circuit (1), with a large increment in the case of undetected synchronizing signals and with a small increment in the case of detected synchronizing signals until the control range of the AFC circuit (1) is reached. The satellite radio receiver described is suitable for connection to satellite receiving installations which comprise a plurality of frequency converters and therefore deviate the nominal receiving frequency in a summary fashion and for private individual installations which, for economic reasons, possess low frequency stability.

Description

For this 2 pages drawings Field of application of the invention

The invention relates to a satellite broadcast receiver.

Characteristic of the known state of the art

Signals transmitted by satellite broadcast receivers from eir.cr satellite reception system may be subject to frequency drift. The cause of the frequency drift is an unstable oscillator of the satellite receiving system or other intermediate converter. Due to the high transmission frequency, even slight relative frequency deviations on the intermediate frequency in the satellite radio receiver act as a steric absolute deviation. This phenomenon can cause the automatic frequency control of the carrier oscillator for the demodulator circuit can no longer compensate for the frequency drift.

Object of the invention

The aim of the invention is to avoid the aforementioned disadvantages.

Explanation of the essence of the invention

The invention has for its object to improve a satellite radio receiver to the effect that even with frequency deviations of the received signal, which goes beyond the control range of the automatic frequency control for the Trägeroszillatcir, a fast and reliable tuning is possible.

According to the invention the object is achieved in that the local oscillator as in a large or a small

Stepwise tunable PLL local oscillator is formed, and that the synchronous signal evaluation circuit and the demodulator circuit are connected directly and / or via further circuits with inputs of a control circuit, by means of

the PLL local oscillator is tuned outside the capture range of the demodulator circuit with unrecognized sync signals or signals derived therefrom with large step size (search) and fine tuned within the capture range for detected sync signals or signals derived therefrom with small increment

It is advantageous that the large step size is smaller than the capture range of the demodulator. According to another embodiment, the small step size is so small that during the tuning process within the capture range no disturbing influence on the output signal is effected, and that the large step size to about 25OkHz and the small step size to about 62.5 kHz is measured.

In a preferred embodiment, the AFC circuit includes a comparator circuit which compares the automatic frequency control (AFC) signal with upper and lower thresholds. The outputs of the comparator circuit connected to the control circuit, wherein an output which specifies one and another output, the other tuning direction.

It is further advantageous that the comparator circuit comprises a first comparator for the upper and a second comparator for the lower threshold, and that the one inputs of the comparators, the AFC signal and the other inputs comparison voltages are supplied via a voltage divider circuit. The

Satellite broadcast receiver is further characterized in that two end terminals of the voltage divider circuit

fixed reference voltages and a tap to a settable reference voltage, and that another tap is at a positive feedback voltage, which is tapped at the outputs of the comparators. The adjustable

Reference voltage is set to a value that tunes the carrier oscillator to a nominal frequency. A further preferred embodiment is characterized in that the Spannungssteiferschaltung a series circuit

consists of resisting that a first resistor with its free end at positive potential + U, while a second

Resistor with its free end at zero potential (ground) is'. An input of the first comparator is with the tap

between two resistors and an input of the second comparator with the tap between two others

Resistors connected. The satellite broadcasting receiver is further characterized in that the adjustable reference voltage in a Circuit arrangement is generated, which is a series circuit of a first resistor, a variable resistor

with a tap and a further resistor, the first resistor with its free end at a positive potential + U, while the second resistor with its free end at a negative potential - U, and the tap connected to the tap between two resistors is.

According to another embodiment, the synchronous signal evaluation circuit is a circuit for evaluating the Error frequency of the received signals (concealement) assigned. An integration of the error signals is specified. at

predetermined time constant is the transition of a reference voltage as a criterion for switching the step size.

The vote small increment takes place in both Abstimmrichtungen. It is also advantageous that provided for the environment of the center frequency of the demodulator a window ία whose width

is less than the limit of two small increments, and that no tuning takes place if this range is sufficient.

Advantageously, a mixing program for controlling the switching from scanning to AFC control is provided. The new satellite radio receiver is for the reception and processing of digitally encoded audio signals and the Reception and processing of digitally encoded video signals designed. The invention first uses a missing synchronization signal as criterion for the tuning. In this case, the PLL local oscillator tuned in large frequency steps (search). As a result, a rapprochement succeeds very quickly

to the optimal frequency compensation for the compensation of the frequency deviation. This will approximate the

Catch range, for example, the 4PSK demodulator achieved. When a sync signal is received, the Frequency steps for the final tuning of the PLL local oscillator reduced. Further coordination of the PLL Local oscillator then takes place in small frequency steps until the frequency deviation of the demodulator

-VCOS is within the limits of a window that is in the vicinity of the center frequency of the tuning range and, for example, less than the limits of two small increments.

Ausführungsbeltplele

Further developments and advantageous embodiments of the invention will become apparent from the claims, the further description and the drawing illustrating an embodiment of the invention. In the drawing show:

2 shows a circuit diagram of a comparator circuit as part of an AFC circuit from FIG. 1, FIG. 3 shows a circuit diagram for obtaining an error signal from the concealment signal.

Fig. 1 shows a block diagram of a satellite broadcasting receiver connected to a satellite receiving system. The satellite receiving system consists of a satellite antenna 41 and two frequency converters 42 and 43. The satellite broadcasting receiver comprises a receiving section 33 with a mixer 45, a PLL local oscillator 44 and a control circuit 34, an IF amplifier 46, a demodulator circuit 47, a carrier oscillator 36th , an AFC circuit 1, a Synchronsignalauswerteschaltung 40 and a Dekodierschjltung 49. At the output of the decoder 49 sincx, tone signals can be tapped.

If the receiving frequency is maintained very accurately, then the PLL local oscillator 44 can be set to a predetermined, agreed frequency, and at the output of the mixer 45 then results in an intermediate frequency with the nominal value of the IF. In the demodulator circuit 47 connected downstream of the IF amplifier 46, the signal, which is preferably in 4 PSK modulation, can be demodulated. For carrier regeneration in the demodulation serve the carrier oscillator 36 which is controlled so that it oscillates in phase with the modulated signal. In this case, the oscillator 30 receives the input signal from the output of the demodulator circuit 47 via the abrasive filter 51. If the receiving frequency deviates from its nominal value, the demodulator 47 can no longer draw the carrier oscillator 36. This in itself for the signal recovery disadvantageous effect is exploited to readjust the control circuit 34 to the local oscillator 44 so that the intermediate frequency is controlled to its nominal value. In this case, the control circuit 34, in particular a microprocessor, receives the instruction to retune the PLL superimposition oscillator 44 step by step. The Nachstimmrichtung is specified by the respective output of the circuits 40,48. At the same time, the control circuit 34 also receives from the synchronous signal evaluation circuit 40 a signal whose state depends on detection and non-recognition of a synchronization signal. If no synchronizing signal is present, the demodulator 47 has thus not caught, the retuning of the PLL local oscillator 44 takes place in large steps, preferably 25OkHz. On the other hand, if a synchronizing signal is present, the PLL local oscillator 44 is tuned in small steps of preferably 62.5 kHz. The temporal sequence of steps is dimensioned to correspond to the system settling time. The tuning process is thus continued in the manner of a search until the demodulator has caught. The tuning process in the capture range continues in small increments until a window of the width of two small steps around the center frequency of the demodulator? is reached.

To control the Steuei circuit 34, in particular of the microprocessor, the AFC circuit 1 includes a comparator 48, which compares the AFC signal with an upper and a lower threshold. Fig. 2 shows the embodiment of a comparator circuit 43, wherein a first comparator 20 is provided for the upper and a second comparator 21 for the lower threshold. Dan one inputs 16,17 of the comparators 20,21 is the AFC signal upper resistors 12 and 13 and the other inputs 18,19 are compared voltages across resistors 14 and 15 and a voltage divider circuit 5 ... 9 supplied. The outputs 31,23 of the comparator circuit 48 are connected to the control circuit 34, wherein the output 31 the eino un'd the other output 23 specifies the other Abstimmrichtuno.

Two end connections of the voltage divider circuit 5... 9 are connected to fixed reference voltages + U, ground and one tap to an adjustable reference voltage U, i _n ". Another tap is at a positive feedback voltage U ~ "tapped at the outputs 22,23 of the comparators 20,21. The adjustable reference voltage UaIn ₁₁ becomes e'J. set a value that tunes the carrier oscillator 36 to a nominal frequency f _Mnn .

The voltage divider circuit comprises a series circuit of resistors 5, 6, 7, 8 and 9, with the resistor 5 at its free end at positive potential + U, while the resistor 9 with its free end is at zero potential (ground). The input 18 de3 first comparator 20 is connected via the resistor 14 to the tap between the resistors 5 and 6 and the input 19 of the second comparator 21 via de η resistor IBmit the tap between the resistors 7 and 8. The pickup between the resistor O- and 7 is at the adjustable reference voltage U, i _{n (} t, while the tap between the resistors 8 and 9 at the Mrikopplungsspannung U _m i, is.

The adjustable reference _voltage is generated in a circuit _comprising a series connection of a resistor 2, a variable resistor 3 with a tap 10 and a resistor 4, the resistor 2 having its free end connected to a positive potential + U, while the resistor 4 is at its free end at a negative potential -U. The tap 10 is connected to the tap between the resistors 6 and 7. A further connection of the tap 10 is on the one hand for a balance serving switch 37, the top of the tap 10 with the control input of the carrier oscillator 36 is connectable.

The output 22 of the first comparator 20 is connected via a series resistor 28 to the control input of an inverter 30 designed as an NPN transistor whose output forms the first output 31 of the comparator circuit 48. The output of the second Kornparators 21 forms the second output 23 of the comparator 48th

For positive feedback of Ausijangssignals to the inputs 18 and 19, the outputs 22 and 23 via resistors 24 and 25 with the taps zwischsn the resistors 8 unc 9 are connected. In addition, the outputs 22 and 23 through resistors 26 and 27 are also at the positive potential + SV like a resistor 29 connected to the output 31 of the transistor, resulting in a TTL match in signal level. The circuit arrangement described so far operates as follows:

To set the correct reference voltage for the comparators 20 and 21 is connected by closing the switch 37, the control input of the currency of the adjustment temporarily free-running carrier oscillator 36 with the tap 10 of the variable resistor 3. By adjusting the variable resistor 3, the voltage supplied to the control input of the carrier oscillator 36 is adjusted so that it can be adjusted to the carrier frequency of 70 MHz in the embodiment.

In the circuit described so far causes a change in temperature, for example, a shift of the window relative to the center frequency of the demodulator 47. To compensate for the temperature influence serves a temperature compensation circuit 50. Since the tuning voltage for the control input of the carrier oscillator (VCO) 36 with the influence dor Temper.iturkompensationsschaltung so acted upon is the tuning voltage already at the output of a loop filter 51 decrease or supply the signal input 32 of the AFC circuit 1, as well as the reference potential (U, i "J for nominal tuning to refer to the output of the loop filter 51.

In order to obtain the reference potential U, i _n ", the positive potential + 6.7 V set in the basic setting of the carrier oscillator (VCO) 36 at the tap 10 in FIG. 2 is first offset by the voltage drop across the temperature compensation circuit 50 with the variable resistor 3 and then reduced by means of a z. B. input via the satellite antenna 41 tuned Meßempfangssignals in such a way that the switching point of the comparator 20 coincides with the lower and the switching point of Kompaiators 21 with the upper allowable frequency deviation of the carrier signal frequency 70MHz. It follows inevitably that the reference potential obtained in this way at the tap 10 occupies a frequency-symmetrical position to the switching points. Both switching points thus give a window for tuning and tuning direction.

The switching point of the first comparator 20 is the voltage drop across the resistor β plus a hysteresis voltage above the reference voltage U "n" and the switching point of the second comparator 2 ^ to the voltage drop across the resistor 7 plus a slight hysteresis below the Betugsspannung U, _inM . This defines a window for the limits of the frequency deviations. Outside the window, a stepwise retuning of the PLL local oscillator 33 is made in small increments and the Abstlmmrichtungon are given differentiated. Within the window, the system is at rest, the control loop is interrupted. For automatic frequency control, the signal input 32 of the comparator 48 dij tuning voltage of the carrier oscillator 36 is supplied and compared with the potential of the switching point of the first comparator 70 and the second comparator 21. , The tuning voltage is within the window, is (irr output 23 on the positive control limit, while the output 22 of the first comparator 20 is connected through to the negative Aussteuernngsgrenze. Thus, the transistor 30 is disabled and the output 31 is also in the positive AusMeuerungsgrenzd. The Outputs 23 and 31 thus carry both signals logically H. The PLL local oscillator 44 is correctly tuned in. If the tuning voltage of the carrier oscillator 36 exceeds the potential of the switching section of the first comparator 20 by the hysteresis voltage as a result of detuning, the output 31 becomes The outputs 31 and 23 thus carry the signals Logic L and Logic H. The frequency of the PLL local oscillator 44 is readjusted, and the tuning voltage of the trigger oscillator 26 falls short of e of an oppositely running detuning the potential of the switching point of the second comparator 21 by the hysteresis voltage, the output 23 iur negative

In this case, the output 31 maintains the position at the positive drive limit. In this case, the outputs 31 and 23 carry the signals logical H and logic L. The frequency regulation of the PLL Local oscillator 44 acts in this case in the opposite direction. In the absence of sync signal, the inputs connected to the outputs 23 and 31 of the Synchronsignalauswerteschaltung 40 switched to inactive, so that the control loop is interrupted. The control circuit 34

starts a station search. When a signal is detected or a sync signal is generated, the control loop takes over further processing, the control circuit 34 evaluating the signals obtained by the comparator circuit 48 to obtain the tuning direction.

The circuit described has the advantage that the window width regardless of the setting of the variable Resistance is 3. By dimensioning the resistors within the voltage divider circuit and the arrangement

the resistors 6 and 7 for obtaining the Komparatorschaltpunkte is achieved that a setting change due to a possibly necessary component replacement equal potential shifts at the inputs 18 and 19 of the comparators 20 and21 result.

The 4PSK demodulator circuit 47 includes a phase locked loop 47, 51, 50, 36 (PLL) in which, when signal is received to Recovery of the non-present in the signal spectrum carrier signal the control input of a voltage-controlled Oscillator (VCO) 36 via a obtained from the output signals of the 4PSK demodulator 47 tuning over

a loop filter 51 and a subsequent VDO temperature compensation sound 50 is supplied. For such

Circuit is a so-called Costas loop advantageous. From the control input of the Trägero & tillators (VCO) 36 is also a connection to a switch 37 via which the Control input to the tap 10 of the variable resistor 3 can be connected with simultaneous interruption

of the phase locked loop. This connection is for default setting of the free running carrier oscillator (VCO) 36 to a frequency of 70 MHz at a positive potential + 6.7 V at the tap 10 before performing the adjustment of the 4PSK demodulator circuit.

The output voltage of the loop filter 51 is a direct measure of the frequency or frequency deviation of the carrier signal in Intermediate frequency. Under certain circumstances, the Synkononsignatauswerteschaltung 40 even in the absence of a sync signal existence

simulate such a sync signal and unfavorably influence the Abutimmung.

3 shows a circuit for obtaining a missing signal, d. H. an error signal for controlling the control circuit 34,

with which this effect can be overcome. For this purpose, a circuit for integrating concealment signals is connected to the synchronous signal evaluation circuit 40. Such concealment signals are used in evaluation circuits for the

Processing of digital signals is usually generated and evaluated, for example by an IC SAA 7500. In FIG

integrated these Concealmentsignale. This is achieved by an RC element 53,54 through which the capacitor 54 of the

Operating voltage UB is charged via the resistor 53 to a voltage logical high. This voltage is on Input of the control circuit 34 in Fig. 1. The full voltage logic high indicates that the scan is initiated. This Charge state of the capacitor 54 is maintained as long as error signals in large numbers at the input of the Synchronous Signalauswerteschaltung 40 occur. As soon as the number of error signals is lower, finds over the Resistor 55, the diode 56 and the circuit 40, a discharge of the capacitor 54 instead; the voltage at the entrance of the Control circuit 34 drops to logic low and causes a switch to vote with small increment until the Window area is reached by the center frequency of the demodulator 47. For charging the capacitor 54 with

the resistor 53 is a larger time constant favorable. For unloading over 40, d. H. for switching to

Fine tuning, however, a small time constant is required. For the control circuit 34, a microprocessor, for example of the type μΡΟ 7811 is advantageous. This can not only be the Tasks of the control circuit 34 take over, but in addition to the evaluations of the information of the (comparator 48 and

the synchronizing signal circuit 40 for the search and the fine tuning operation also the timing of switching the

Control circuit 34 of FIG. 3 for the query of the control lines 481 and 482 and for the gradual changes. η the Frequency of Oscillator 44. In search or fine tune mode, the processor adds to ensure a flawless Settling the system a different waiting times that can replace or support the integration of FIG. 3. Under unfavorable reception conditions, short-term synchronization failures can occur. At this time

The processor must not immediately switch to the search mode, otherwise it would disturb long mute times. The processor waits for a new synchronization of the system in a given period of time without changing the tuning of the oscillator.

The circuit shown in Fig. 1 can be modified so that the frequency of the oscillator 36 in a highly accurate Discriminator is evaluated and the control voltage of the comparator 48 is supplied. This will be the Temperature influences reduced.

Claims (17)

A satellite broadcasting receiver to which signals of a satellite receiving system comprising a receiving antenna and at least one frequency converter are fed, the satellite broadcasting receiver comprising a receiving section with a local oscillator and a demodulator circuit comprising a carrier oscillator and a synchronous signal evaluation circuit for signal recovery, characterized in that the local oscillator (44) is designed as a PLL local oscillator (44) which can be tuned in a large or small step size, and in that the synchronous signal evaluation circuit (40) and the demodulator circuit (47) have direct and / or further inputs (48) Control circuit (34) are connected, by means of which the PLL local oscillator (44) is tuned out of the capture range of the demodulator circuit (4) recognized sync signals or signals obtained therefrom with large step size (Suchla uf) and fine tuned within the capture range for detected sync signals or signals obtained therefrom with a small step size. 2. Satellite radio receiver according to claim 1, characterized in that the large step size is smaller than the capture range of the demodulator (47). 3. Satellite radio receiver according to claim 2, characterized in that the small increment is dimensioned so small that no disturbing influence of the output signal is effected during the tuning process within the capture range. 4. Satellite radio receiver according to claim 2, characterized in that the large step size to about 250 kHz and the small step size to about 62.5 kHz is dimensioned. 5. Satellite radio receiver according to claim 1 or 2, characterized in that the AFC circuit (1) comprises a comparator circuit (48) which compares the signal of the automatic frequency control (AFC signal) with an upper and a lower threshold and that Outputs (31,23) of the Kcmparatorschaltung (48) with the Steuer¬ attitude (34) are connected, wherein an output (31) which specifies one and another output (23) the other tuning direction. 6. Satellite radio receiver according to claim 3, characterized in that the comparator circuit (48) comprises a first comparator (20) for the upper and a second comparator (21) for the lower threshold value, and that the one inputs (16,17) the comparators (20,21) the AFC signal and other inputs (18,19) comparison voltages via a voltage divider circuit (5 ... 9) are supplied. 7. satellite broadcasting receiver according to claim 4, characterized in that two end terminals of the Spannungsteilorschaltung (5 ... 9) to fixed reference voltages (+ U, earth) and a tapping of an adjustable reference voltage (U _{a, t)} lie. 8. Satellite radio receiver according to claim 5, characterized in that a further tap at a Mitkopplungsspannung (U _mil ), which is tapped at the outputs (22,23) of the comparators (20,21). 9. Satellite radio receiver according to claim 4 or 5, characterized in that the adjustable reference voltage (U _e j _{n (t} ) is set to a value which tunes the carrier oscillator (36) to a nominal frequency (f _ne nn). 10. Satellite radio receiver according to one or more of claims 5 to 7, characterized in that the voltage divider circuit comprises a series circuit of resistors (5,6, 7,8 and 9) that the resistor (5) with its free end to positive Potential + U, while the resistor (9) is at its free end at zero potential (ground) that an input (18) of the first comparator (20) with the tap between the resistors (5,6) and an input (19) of the second comparator (21) is connected to the tap between the Widerutänden (7,8), that the tap between the resistor (6,7) at the adjustable reference voltage (U _e in »t) and that the tap between the resistors (8, 9) is at the positive feedback voltage (U _with ). 11. Satellite radio receiver according to one of claims 5 to 8, characterized in that the adjustable reference voltage (U _a ") is generated in a circuit arrangement comprising a series circuit of a resistor (2), a variable resistor (3) with a tap (10) and a resistor (4), wherein the resistor (2) with its free end at a positive potential + U, while the resistor (4) lies with its free end at a negative potential -U, and that the Tap (10) is connected to the tap between the resistors (6 and 7). 12. Satellite radio receiver according to one of claims 1 to 11, characterized in that the synchronization signal evaluation circuit (40) is associated with a circuit for evaluating the error rate of the received signals (concealement) that an integration of the error signals is predetermined, and that at predetermined time constants Transfer of a reference voltage serves as a criterion for switching the step size. 13. Satellite radio receiver according to one of claims 1 to 12, characterized in that the vote small increment takes place in both Abstimmrichtungen. 14. Satellite radio receiver according to one of claims 1 to 13, characterized in that for the environment of the center frequency of the demodulator, a window is provided whose width is smaller than the limit of two small increments, and that no tuning takes place when this range is reached is. 15. Satellite radio receiver according to one of claims 1 to 14, characterized in that a mixing program for the control of switching from scanning to AFC control is vorgesetztenhen. 16. Satellite radio receiver according to one of claims 1 to 15, characterized in that it is designed for the reception and processing of digitally encoded audio signals. 17. Satellite radio receiver according to one of claims 1 to 15, characterized in that it is designed for receiving and processing of digitally encoded video signals.