CN222509270U

CN222509270U - Oscillation circuits, chips and electronic devices

Info

Publication number: CN222509270U
Application number: CN202421118745.3U
Authority: CN
Inventors: 郑文彬
Original assignee: Beijing Xuanjie Technology Co ltd
Current assignee: Beijing Xuanjie Technology Co ltd
Filing date: 2024-05-21
Publication date: 2025-02-18
Anticipated expiration: 2034-05-21

Abstract

The present utility model relates to the field of circuit technologies, and in particular, to an oscillating circuit, a chip, and an electronic device. The circuit comprises a main inductor, a first cross-coupling differential circuit and a second cross-coupling differential circuit, wherein the main inductor is respectively connected with the first cross-coupling differential circuit and the second cross-coupling differential circuit in parallel, and comprises four single-loop inductors which are connected in parallel, so that the effects of reducing power consumption and improving phase noise are achieved under the condition that the quality factor of the main inductor is not influenced.

Description

Oscillating circuit, chip and electronic equipment

Technical Field

The present utility model relates to the field of circuit technologies, and in particular, to an oscillating circuit, a chip, and an electronic device.

Background

The current 5G high-speed mobile Internet age has stringent requirements on phase noise, power consumption and layout area of a wireless communication system. Since the oscillating circuit is an important component in a wireless communication system, the phase noise level of the entire communication system is determined. It is therefore important how to design a low power consumption and low noise oscillating circuit at high frequencies.

At present, the magnitude of the phase noise is proportional to the inductance value and inversely proportional to the quality factor value of the inductance. Therefore, the inductance in the oscillating circuit needs to be designed in a direction of a smaller inductance and a higher quality factor. The related art mostly reduces the inductance value by reducing the area of the inductor, thereby meeting the requirement of improving the phase noise, but reducing the area of the inductor can deteriorate the quality factor of the inductor. Meanwhile, under the condition of double resonant frequency, current can flow to the ground from the differential pair tube, so that the quality factor of the inductor is reduced, phase noise is deteriorated, the efficiency of the oscillating circuit for converting direct current into first-order resonant frequency current is low, and power consumption is high.

Disclosure of utility model

The utility model provides an oscillating circuit, a chip and electronic equipment, and aims to reduce the power consumption of the oscillating circuit and improve the phase noise under the condition of not influencing the quality factor of an inductor.

According to a first aspect of the present utility model there is provided an oscillating circuit comprising a main inductance, a first cross-coupled differential circuit and a second cross-coupled differential circuit;

the main inductor is respectively connected with the first cross-coupling differential circuit and the second cross-coupling differential circuit in parallel;

The main inductance comprises four single-turn inductances connected in parallel.

Optionally, the oscillating circuit further includes a first common mode resonant circuit and a second common mode resonant circuit, the first common mode resonant circuit is connected with the first cross-coupled differential circuit through a first common mode connection port, and the second common mode resonant circuit is connected with the second cross-coupled differential circuit through a second common mode connection port;

the first common mode resonant circuit comprises a first common mode inductor, the second common mode resonant circuit comprises a second common mode inductor, the first common mode inductor and/or the second common mode inductor comprise two single-loop inductors, and the electromagnetism generated by the two single-loop inductors is offset.

Optionally, the first common mode inductance and/or the second common mode inductance are 8-shaped common mode inductances.

Optionally, the first common-mode inductor and the second common-mode inductor are symmetrically arranged in a closed area formed by four single-turn inductors of the main inductor.

Optionally, the first common mode resonant circuit further includes a first capacitor, and the first common mode inductor is connected with the first capacitor;

the second common mode resonant circuit further comprises a second capacitor, and the second common mode inductor is connected with the second capacitor;

The first ends of the first common-mode inductor and the first capacitor are connected with a first common-mode connection port, and the second ends of the first common-mode inductor and the first capacitor are connected with a voltage port;

The first ends of the second common-mode inductor and the second capacitor are connected with the second common-mode connection port, and the second ends of the second common-mode inductor and the second capacitor are grounded.

Optionally, the oscillating circuit further comprises an adjustable transistor;

The source of the adjustable transistor is connected with the voltage port, and the grid of the adjustable transistor is connected with the power supply voltage.

Optionally, the first cross-coupled differential circuit comprises a first transistor of a first type and a second transistor of the first type;

The second cross-coupled differential circuit includes a third transistor of a second type and a fourth transistor of the second type;

Sources of the first transistor and the second transistor are connected to the first common mode connection port, and sources of the third transistor and the fourth transistor are connected to the second common mode connection port.

Optionally, a gate of the first transistor is connected to the second end of the main inductor, and a drain of the first transistor is connected to the first end of the main inductor;

The grid electrode of the fourth transistor is connected with the first end of the main inductor, and the drain electrode of the third transistor is connected with the second end of the main inductor.

Optionally, the oscillating circuit further comprises a parameter adjusting circuit, and the parameter adjusting circuit is connected with the main inductor in parallel.

Optionally, the parameter adjusting circuit includes a first branch including a first diode and a second diode connected in series;

The second branch comprises a third diode and a fourth diode which are connected in series;

The third branch comprises a first resistor and a second resistor which are connected in series;

The first branch, the second branch and the third branch are connected in parallel and connected in series with the first capacitor and the second capacitor.

Optionally, the oscillating circuit further comprises a capacitive switch array;

The capacitive switch array comprises at least one capacitive switch circuit, and two ends of the at least one capacitive switch circuit are respectively connected with the parameter adjusting circuit and the second cross-coupling differential circuit.

Optionally, the at least one capacitive switching circuit includes a third capacitor, a fourth capacitor, and a fifth transistor;

The third capacitor is connected with the source electrode of the fifth transistor, and the fourth capacitor is connected with the grid electrode of the fifth transistor;

the third capacitor is connected with the first capacitor, and the fourth capacitor is connected with the drains of the third transistor and the fourth transistor.

According to a second aspect of the present utility model there is provided a chip comprising an oscillating circuit as described in any of the preceding first aspects.

According to a third aspect of the present utility model, there is provided a chip comprising a first region and a second region,

The first area is used for arranging a main inductor consisting of four parallel single-turn inductors, and is an octagonal closed area;

The second area is used for arranging a first cross-coupling differential circuit and a second cross-coupling differential circuit, the main inductor is respectively connected with the first cross-coupling differential circuit and the second cross-coupling differential circuit in parallel, and the second area is chain-shaped in the first direction and is arranged in the first area in the middle.

Optionally, the chip further includes a third region, where the third region is configured to arrange a first common mode resonant circuit and a second common mode resonant circuit, and the third region is symmetrically arranged in the first region in the second direction, where the first common mode resonant circuit includes a first common mode inductance, where the second common mode resonant circuit includes a second common mode inductance, where the first common mode inductance and the second common mode inductance include two single-turn inductances, and where the two single-turn inductances generate electromagnetic waves that cancel each other.

According to a fourth aspect of the present utility model, there is provided an electronic device comprising the oscillating circuit described in any of the preceding first aspects, or comprising the chip described in the preceding second aspect, or comprising the chip described in any of the preceding third aspects.

In summary, in one or more embodiments of the present utility model, by using the main inductor, the first cross-coupling differential circuit and the second cross-coupling differential circuit in the oscillating circuit structure in the present disclosure, the main inductor is respectively connected in parallel with the first cross-coupling differential circuit and the second cross-coupling differential circuit, and the main inductor includes four parallel single-loop inductors, so that effects of reducing power consumption and improving phase noise are achieved without affecting quality factors of the main inductor.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The foregoing and/or additional aspects and advantages of the utility model will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram of a radio frequency transceiver according to a specific application scenario provided in an embodiment of the present utility model;

Fig. 2 is a schematic diagram of an oscillating circuit according to an embodiment of the present utility model;

Fig. 3 is a schematic diagram of a main inductor provided by an embodiment of the present utility model;

fig. 4 is a schematic structural diagram of a specific oscillating circuit according to an embodiment of the present utility model;

FIG. 5 is a schematic diagram of a chip according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of a chip according to an embodiment of the present utility model;

Fig. 7 is a schematic diagram of a specific chip according to an embodiment of the present utility model.

Detailed Description

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model. On the contrary, the embodiments of the utility model include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.

The current 5G high-speed mobile Internet age has stringent requirements on phase noise, power consumption and layout area of a wireless communication system. The oscillating circuit, as an important component in a wireless communication system, determines the phase noise level of the overall communication system. It is therefore important how to design a low power consumption and low noise oscillating circuit at high frequencies.

In order to solve the problems in the related art, the present disclosure provides an oscillating circuit, in which a main inductor includes four single-turn inductors connected in parallel, so as to achieve the effects of reducing power consumption and improving phase noise without affecting the quality factor of the inductor. Meanwhile, the common mode resonant circuit is connected to the power supply end and the ground end to provide high impedance at double resonant frequency, meanwhile, 2 times frequency multiplication current from the power supply to the first type transistor and the second type transistor to the ground is restrained, and the efficiency of converting direct current (DC current) into first-order resonant frequency current is improved, so that the power consumption is further reduced, and the phase noise is effectively improved.

The resonant circuit and the electronic device provided by the disclosure can be applied to the field of radio frequency communication, and in particular, can also be applied to inductance design of an LC-VCO (Inductor and Capacitor based Voltage Controlled Oscillator, inductance capacitance type voltage-controlled oscillator) in a PLL (Phase-Locked Loops) in a 5G NR radio frequency chip. In addition, the oscillating circuit and the electronic device in the disclosure can also be used in the field of radio frequency chip design such as WIFI, bluetooth, GPS and the like, and are not limited in the embodiments of the disclosure.

One specific application scenario shown in fig. 1 is a schematic diagram of a radio frequency transceiver. Referring to fig. 1, a radio frequency transceiver is generally composed of a transceiving antenna, a low noise amplifier, a mixer, a voltage controlled oscillator, a power amplifier, and a modulator/demodulator. When the receiving antenna receives electromagnetic waves, it passes the signal to a low noise amplifier for amplification and converts it to a lower frequency signal by a mixer. This signal is then fed into a voltage controlled oscillator to generate a lower intermediate frequency signal, which is then fed into a demodulator to convert it into a digital signal, completing the decoding of the data.

For the transmission process, the digital signal is first modulated and fed into a power amplifier for transmission to the receiving end via a radio frequency antenna. During transmission, the radio frequency transceiver plays a key role in converting digital signals into electromagnetic signals and modulating them.

The inductances mentioned in this disclosure are used in the oscillating circuit of a voltage controlled oscillator. Voltage controlled oscillators are used in radio frequency transceivers to generate high frequency signals whose frequency is adjusted by varying the value of the input voltage. In a phase-locked loop in a radio frequency transceiver, the phase-locked loop detects the phase difference between an input signal and an output signal, converts the detected phase difference signal into a voltage signal through a phase discriminator, outputs the voltage signal, filters the voltage signal through a low-pass filter to form a control voltage of the voltage-controlled oscillator, controls the frequency of the output signal of the oscillator, and feeds back the frequency and the phase of the output signal of the oscillator to the phase discriminator through a feedback path. Finally, the frequency and the phase of the voltage-controlled oscillator are kept in a definite relation with the input signal.

The present utility model will be described in detail with reference to specific examples.

Fig. 2 is a schematic diagram of an oscillating circuit according to an embodiment of the present utility model.

As shown in fig. 2, the oscillating circuit includes:

a main inductance 23, a first cross-coupled differential circuit 24, and a second cross-coupled differential circuit 25;

The main inductor 23 is connected in parallel with the first cross-coupled differential circuit 24 and the second cross-coupled differential circuit 25 respectively;

The main inductance 23 comprises four parallel single-turn inductances.

The main inductor may be a flower-type inductor.

One type of primary inductor is shown in fig. 3 as a schematic diagram of a flower-type inductor. With reference to fig. 3, the current flow in the flower-shaped inductor is four circles, namely 1,2,3 and 4, so that the overall flower-shaped inductor can be equivalent to the parallel connection of four single-circle inductors. The quality factor of the flower-shaped inductor is equivalent to that of the single-turn inductor, but the inductance value of the flower-shaped inductor is one fourth of that of the single-turn inductor, so that the main inductor in the present disclosure adopts the structure of the flower-shaped inductor, and the requirement of low inductance value and high quality factor can be realized, thereby achieving the effects of reducing power consumption and improving phase noise under the condition that the quality factor of the main inductor is not influenced in the present disclosure.

The oscillating circuit further comprises a first common-mode resonant circuit 21 and a second common-mode resonant circuit 22, the first common-mode resonant circuit 21 being connected to a first cross-coupled differential circuit 24 via a first common-mode connection port 10, the second common-mode resonant circuit 22 being connected to a second cross-coupled differential circuit 25 via a second common-mode connection port 11. According to the common-mode resonant circuit, the common-mode resonant circuit is additionally added on the basis of the oscillating circuit, so that the power consumption is further reduced, and the phase noise is improved.

The oscillating circuit structure can adopt a CMOS (Complementary Metal Oxide Semiconductor) differential amplifier structure, the efficiency of the DC current of the oscillating circuit structure is doubled as compared with that of an NMOS structure, and the CMOS differential amplifier structure can add a common-mode resonant circuit on two sides and resonate at 2 times of the frequency of the oscillator circuit, so that a common-mode point presents high impedance, and the periodic reduction of the quality factor (Q value) of the overall inductance of the oscillating circuit is reduced. Thereby reducing the power consumption and phase noise of the oscillating circuit.

Optionally, as shown in the schematic structural diagram of a specific oscillating circuit in fig. 4, the first common-mode resonant circuit 21 includes a first common-mode inductor 211, the second common-mode resonant circuit 22 includes a second common-mode inductor 221, and the first common-mode inductor 211 and/or the second common-mode inductor 221 include two single-turn inductors, and the electromagnetic generated by the two single-turn inductors cancel each other.

The first common mode inductor 211 and/or the second common mode inductor 221 are 8-shaped common mode inductors.

In the disclosure, the first common-mode inductor and the second common-mode inductor are both 8-shaped inductors and are symmetrically connected with the main inductor, so that induction currents generated by the two 8-shaped inductors on adjacent wires are mutually offset, and therefore the two 8-shaped inductors have stronger anti-interference capability, and magnetic fields generated by current changes are opposite in direction and mutually offset, and electromagnetic interference generated by the main inductor and the oscillating circuit is very low.

Meanwhile, the first common-mode inductor 211 and the second common-mode inductor 221 are symmetrically arranged in a closed area formed by four single-turn inductors of the main inductor 23, so that the effect of not increasing additional layout area is achieved on the practical layout.

The first common mode resonant circuit 21 further comprises a first capacitor 212, the first common mode inductor 211 is connected with the first capacitor 212, and the second common mode resonant circuit 22 further comprises a second capacitor 222, and the second common mode inductor 221 is connected with the second capacitor 222.

Alternatively, referring to fig. 4, first ends of the first common-mode inductor 211 and the first capacitor 212 are connected to the first common-mode connection port 10, second ends of the first common-mode inductor 211 and the first capacitor 212 are connected to the voltage port 12, first ends of the second common-mode inductor 221 and the second capacitor 222 are connected to the second common-mode connection port 11, and second ends of the second common-mode inductor 221 and the second capacitor 222 are grounded.

Optionally, referring to fig. 4, in order to adjust the power supply voltage VDD, the oscillating circuit further includes an adjustable transistor 26, wherein a source of the adjustable transistor 26 is connected to the voltage port 12, and a gate of the adjustable transistor 26 is connected to the power supply voltage VDD.

Wherein the tunable transistor is a PMOS transistor in the present disclosure.

Alternatively, referring to fig. 4, the first cross-coupled differential circuit 24 includes a first transistor 241 of a first type and a second transistor 242 of a first type, the second cross-coupled differential circuit 25 includes a third transistor 251 of a second type and a fourth transistor 252 of a second type, sources of the first transistor 241 and the second transistor 242 are connected to the first common mode connection port 10, and sources of the third transistor 251 and the fourth transistor 252 are connected to the second common mode connection port 11.

The first type of transistor may be a PMOS transistor in the present disclosure, the second type of transistor may be an NMOS transistor in the present disclosure, that is, the first transistor 241 and the second transistor 242 are PMOS transistors, and the third transistor 251 and the fourth transistor 252 are NMOS transistors.

In the present disclosure, the combination of the first cross-coupled differential circuit 24 and the second cross-coupled differential circuit 25 is a complementary cross-coupled structure, i.e., a differential pair is formed by using 2 NMOS transistors and 2 PMOS transistors, which increases 2 transistors, increases thermal noise, and increases parasitic capacitance, affecting the tuning range.

Alternatively, referring to fig. 4, the gate of the first transistor 241 is connected to the second terminal of the main inductor 23, the drain of the first transistor 241 is connected to the first terminal of the main inductor 23, the gate of the fourth transistor 252 is connected to the first terminal of the main inductor 23, and the drain of the third transistor 251 is connected to the second terminal of the main inductor 23.

In the present disclosure, since the main inductor includes four single-turn inductors connected in parallel, referring to fig. 3, the main inductor has four inductor arms, where P1 is a first inductor arm, P2 is a second inductor arm, P3 is a third inductor arm, and P4 is a fourth inductor arm. The four inductor arms of the main inductor may be cross-connected through transistors of the first cross-coupled differential circuit and the second cross-coupled differential circuit in the oscillating circuit, i.e. the first inductor arm P1 of the main inductor may be connected to the gate of the second transistor 242, the second inductor arm P2 of the main inductor may be connected to the gate of the first transistor 241, the third inductor arm P3 of the main inductor may be connected to the gate of the fourth transistor 252, and the fourth inductor arm P4 of the main inductor may be connected to the gate of the third transistor 251. Therefore, four single-turn inductors in the main inductor are connected in parallel, and can present a smaller inductance value (the main inductor is 90 pH).

Optionally, referring to fig. 4, the oscillating circuit further includes a parameter adjusting circuit 27, and the parameter adjusting circuit 27 is connected in parallel with the main inductor 13.

Optionally, the parameter tuning circuit comprises a first branch comprising a first diode 273 and a second diode 274 in series, a second branch comprising a third diode 275 and a fourth diode 276 in series, a third branch comprising a first resistor 277 and a second resistor 278 in series, wherein the first branch, the second branch, and the third branch are in parallel and in series with the first capacitor 271 and the second capacitor 272.

Specifically, the parameter adjusting circuit 27 includes a first capacitor 271, a second capacitor 272, a first diode 273, a second diode 274, a third diode 275, a fourth diode 276, a first resistor 277, and a second resistor 278, wherein an anode of the first diode 273 is connected to an anode of the second diode 274, an anode of the third diode 275 is connected to an anode of the fourth diode 276, the first resistor 277 is connected to the second resistor 278, a cathode of the first diode 273, a cathode of the third diode 275, and the first resistor 277 are respectively connected to the first capacitor 271, a cathode of the second diode 274, a cathode of the fourth diode 276, and the second resistor 278 are respectively connected to the second capacitor 272, the first capacitor 271 is connected to a first end of the main inductor 23, and the second capacitor is connected to a second end of the main inductor 23.

The loop formed by the first capacitor 271, the third diode 275, the fourth diode 276 and the second capacitor 272 can adjust the output frequency of the oscillating circuit, such as Kvco var, according to the control voltage in the PLL loop, the loop formed by the first capacitor 271, the first diode 273, the second diode 274 and the second capacitor 272 can adjust the temperature parameter in the oscillating circuit, such as V _- ctat, and the loop formed by the first capacitor 271, the first resistor 277, the second resistor 278 and the second capacitor 272 can adjust the bias voltage in the oscillating circuit, such as V _- bias.

Optionally, referring to fig. 4, the oscillating circuit further comprises a capacitive switch array 28, and the capacitive switch array 28 comprises at least one capacitive switch circuit 281, wherein two ends of the at least one capacitive switch circuit 281 are respectively connected with the parameter adjusting circuit 27 and the second cross-coupling differential circuit 25.

The capacitive switch array 28 is used to adjust the capacitance value of the oscillating circuit, and since the frequency in the oscillating circuit is determined by the capacitance and the inductance, the capacitance value of the oscillating circuit is adjusted by the capacitive switch array 28, so that the frequency of the oscillating circuit can be adjusted. The number of capacitive switch circuits 281 in the capacitive switch array 28 may be set according to the actually required capacitance, which is not limited in the embodiment of the present disclosure.

Optionally, referring to fig. 4, the at least one capacitance switch circuit 281 includes a third capacitance 2811, a fourth capacitance 2812 and a fifth transistor 2813, the third capacitance 2811 is connected to a source of the fifth transistor 2813, the fourth capacitance 2812 is connected to a gate of the fifth transistor 2813, the third capacitance 2811 is connected to the first capacitance 271, and the fourth capacitance 2812 is connected to drains of the third transistor 251 and the fourth transistor 252.

In this disclosure, the fifth transistor 2813 may be a first type transistor, that is, an NMOS transistor is used as the fifth transistor.

In summary, the oscillating circuit provided by the embodiment of the utility model realizes the main inductance, the first cross-coupling differential circuit and the second cross-coupling differential circuit, wherein the main inductance is respectively connected with the first cross-coupling differential circuit and the second cross-coupling differential circuit in parallel, and comprises four single-loop inductances which are connected in parallel, so that the effects of reducing power consumption and improving phase noise are achieved under the condition that the quality factor of the main inductance is not influenced.

The embodiment of the utility model also provides a chip, which comprises the oscillating circuit described in the embodiment.

A schematic diagram of a chip, specifically a layout of an oscillating circuit on the chip, is shown in fig. 5. The embodiment of the present utility model also provides a chip, referring to fig. 5, which includes a first region 51 and a second region 52,

The first area 51 is used for arranging a main inductor 23 consisting of four parallel single-turn inductors, and the first area 51 is an octagonal closed area;

Referring to the dotted line portion in fig. 5, the second region 52 is for arranging the first cross-coupled differential circuit 24 and the second cross-coupled differential circuit 25, and the main inductor 23 is connected in parallel with the first cross-coupled differential circuit 24 and the second cross-coupled differential circuit 25, respectively, and the second region 52 is chain-shaped in the first direction and centrally arranged within the first region 51.

Optionally, as shown in the schematic diagram of a chip in fig. 6, the chip further includes a third area 53, where the third area 53 is used to arrange the first common mode resonant circuit 21 and the second common mode resonant circuit 22, the third area 53 is symmetrically arranged in the first area 51 in the second direction, the first common mode resonant circuit 21 includes a first common mode inductor 211, the second common mode resonant circuit 22 includes a second common mode inductor 221, and the first common mode inductor 211 and the second common mode inductor 221 include two single-turn inductors and the electromagnetic generated by the two single-turn inductors cancel each other.

In an alternative embodiment of the present disclosure, as shown in fig. 7, the present disclosure also provides a schematic diagram of a specific chip.

Referring to fig. 7, the main inductor is a black thick line, a left dotted line box symmetrically placed in the main inductor represents a first common mode inductor in the first common mode resonant circuit, and a right dotted line box represents a second common mode inductor in the second common mode resonant circuit, and the first common mode inductor and the second common mode inductor are 8-shaped inductors. GM denotes a first cross-coupled differential circuit and a second cross-coupled differential circuit, and SCA denotes a capacitive switch array. The SCA _- C represents that the capacitance adjustment level is lower, the adjustment effect is rough, the SCA _- M represents that the capacitance adjustment level is middle, the adjustment effect is moderate, the SCA _- F represents that the capacitance adjustment level is higher, and the adjustment effect is fine. Kvco and TC each represent a parameter adjustment circuit. Where Kvco represents the ability of the tank circuit to adjust the output frequency based on the control voltage in the PLL loop, and TC represents the temperature compensation of the entire tank circuit.

In summary, the present disclosure provides a low-power consumption low-phase noise oscillating circuit, which uses a low inductance and high quality factor flower-shaped main inductor and 8-shaped inductors for the first common-mode inductor and the second common-mode inductor through the main inductor, so that the common-mode inductor can be introduced without affecting the quality factor of the main inductor, increasing the layout area of a chip, and increasing mutual electromagnetic interference, and the power consumption and phase noise of the oscillating circuit are further optimized.

The embodiment of the utility model also provides electronic equipment.

Specifically, the electronic equipment comprises the oscillating circuit described in any one of the above embodiments.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms may be directed to different embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the utility model as defined by the appended claims and their equivalents.

Claims

1. An oscillating circuit, characterized in that the oscillating circuit comprises:

a main inductor, a first cross-coupled differential circuit, and a second cross-coupled differential circuit;

The main inductor comprises four single-turn inductors connected in parallel.

2. The oscillating circuit of claim 1, further comprising a first common mode resonant circuit connected to the first cross-coupled differential circuit through a first common mode connection port and a second common mode resonant circuit connected to the second cross-coupled differential circuit through a second common mode connection port;

The first common mode resonant circuit comprises a first common mode inductor, the second common mode resonant circuit comprises a second common mode inductor, and the first common mode inductor and/or the second common mode inductor comprise two single-loop inductors and the electromagnetism generated by the two single-loop inductors is offset.

3. The oscillating circuit of claim 2, wherein the first common-mode inductance and/or the second common-mode inductance is an 8-shaped common-mode inductance.

4. An oscillating circuit according to claim 2 or 3, characterized in that the first common-mode inductance and the second common-mode inductance are symmetrically arranged within a closed area formed by four single-turn inductances of the main inductance.

5. An oscillating circuit according to claim 2 or 3, wherein the first common mode resonant circuit further comprises a first capacitor, the first common mode inductance being connected to the first capacitor;

The first common-mode inductor and the first end of the first capacitor are connected with the first common-mode connection port, and the second end of the first capacitor and the first common-mode inductor are connected with the voltage port;

6. The oscillating circuit of claim 5, further comprising an adjustable transistor;

The source electrode of the adjustable transistor is connected with the voltage port, and the grid electrode of the adjustable transistor is connected with the power supply voltage.

7. The oscillating circuit of claim 2, wherein the first cross-coupled differential circuit comprises a first transistor of a first type and a second transistor of the first type;

8. The oscillating circuit of claim 7, wherein a gate of the first transistor is connected to the second end of the main inductor and a drain of the first transistor is connected to the first end of the main inductor;

9. The oscillating circuit of claim 8, further comprising a parameter adjustment circuit, the parameter adjustment circuit being in parallel with the main inductance.

10. The oscillating circuit of claim 9, wherein the parameter tuning circuit comprises a first branch comprising a first diode and a second diode in series;

the second branch circuit comprises a third diode and a fourth diode which are connected in series;

the third branch circuit comprises a first resistor and a second resistor which are connected in series;

Wherein the first branch, the second branch, the third branch are connected in parallel and in series with a first capacitor and a second capacitor.

11. The oscillating circuit of claim 10, further comprising an array of capacitive switches;

12. The oscillating circuit of claim 11, wherein the at least one capacitive switching circuit comprises a third capacitor, a fourth capacitor, and a fifth transistor;

13. A chip, characterized in that it comprises an oscillating circuit according to any one of claims 1 to 10.

14. A chip, characterized in that the chip comprises a first area and a second area,

The first area is used for arranging a main inductor composed of four parallel single-turn inductors, and is an octagonal closed area;

15. The chip of claim 14, further comprising a third region for arranging a first common mode resonant circuit and a second common mode resonant circuit, the third region being symmetrically arranged in a second direction within the first region, the first common mode resonant circuit comprising a first common mode inductance, the second common mode resonant circuit comprising a second common mode inductance, the first common mode inductance and the second common mode inductance comprising two single turn inductances and the electromagnetic produced by the two single turn inductances cancel each other.

16. An electronic device comprising an oscillating circuit according to any one of claims 1 to 12, or comprising a chip according to claim 13, or comprising a chip according to any one of claims 14 to 15.