CN221899549U - Multi-chip interconnection device, main board and electronic equipment - Google Patents
Multi-chip interconnection device, main board and electronic equipment Download PDFInfo
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- CN221899549U CN221899549U CN202323562346.4U CN202323562346U CN221899549U CN 221899549 U CN221899549 U CN 221899549U CN 202323562346 U CN202323562346 U CN 202323562346U CN 221899549 U CN221899549 U CN 221899549U
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Abstract
The utility model provides a multi-chip interconnection device, a main board and electronic equipment, wherein the multi-chip interconnection device comprises a plurality of main control chips, the main control chips are interconnected through interconnection buses, the interconnection buses are serial peripheral interface buses or analog serial peripheral interface buses, and each main control chip is connected with at least one interconnection bus; at least one main control chip in the plurality of main control chips is connected with at least two interconnection buses, and the at least one main control chip is a master device of at least one interconnection bus and is a slave device or master device of other interconnection buses. In the embodiment of the utility model, the plurality of main control chips are interconnected through the interconnection bus which is a serial peripheral interface bus or an analog serial peripheral interface bus, and the interconnection bus has simple protocol, is beneficial to operation and is a non-point-to-point connection bus.
Description
Technical Field
The present utility model relates to the field of computer technologies, and in particular, to a multi-chip interconnection device, a motherboard, and an electronic device.
Background
In the field of computers, there is a need for data/signal transmission between a plurality of chips, based on which communication between a plurality of chips is required to be achieved through an interconnection structure.
However, the protocol of the interconnection structure capable of realizing communication between the plurality of chips requires rate negotiation, handshake negotiation, and the like at the time of communication, and the connection structure is relatively complex.
Disclosure of utility model
In view of the above problems, embodiments of the present utility model provide a multi-chip interconnection device, a motherboard and an electronic device, so as to at least solve the technical problem in the prior art that an interconnection structure capable of implementing communication between a plurality of chips is relatively complex.
The embodiment of the utility model provides a multi-chip interconnection device, which comprises a plurality of main control chips, wherein the main control chips are interconnected through an interconnection bus, the interconnection bus is a serial peripheral interface bus or an analog serial peripheral interface bus, and each main control chip is connected with at least one interconnection bus;
at least one master control chip in the plurality of master control chips is connected with at least two interconnection buses, and the at least one master control chip is a master device of at least one interconnection bus and is a slave device or a master device of other interconnection buses;
The main control chip is provided with a serial peripheral interface, and the serial peripheral interface is used for connecting with the serial peripheral interface bus; and/or the main control chip is provided with a general input/output interface group, the general input/output interface group comprises a plurality of general input/output interfaces, and the general input/output interface group is used for being connected with the analog serial peripheral interface bus.
Optionally, at least two main control chips are interconnected by the interconnection bus.
Optionally, at least one master control chip connected with at least two interconnection buses comprises a first master control chip and a second master control chip, the first master control chip is interconnected with the second master control chip through a first interconnection bus and a second interconnection bus, the first master control chip is a master device of the first interconnection bus, the first master control chip is a slave device of the second interconnection bus, the second master control chip is a slave device of the first interconnection bus, and the second master control chip is a master device of the second interconnection bus.
Optionally, at least one of the main control chips is a system-on-chip.
Optionally, at least one master control chip connected with at least two interconnection buses comprises three third master control chips, the three third master control chips are mutually connected in pairs through at least three third interconnection buses, each third master control chip is at least connected with two third interconnection buses, the third master control chip is a master device of at least one third interconnection bus, and/or the third master control chip is a slave device of at least one third interconnection bus.
Optionally, at least one of the master control chips connected with at least two interconnection buses includes four fourth master control chips, the four fourth master control chips are interconnected in pairs through at least six fourth interconnection buses, each of the fourth master control chips is at least connected with three fourth interconnection buses, and the fourth master control chip is a master device of at least one fourth interconnection bus and is a slave device of at least one fourth interconnection bus.
Optionally, the plurality of master control chips include a fifth master control chip and a plurality of sixth master control chips, the fifth master control chip is connected with the plurality of sixth master control chips through a fifth interconnection bus, the fifth master control chip is a master device of the fifth interconnection bus, and the plurality of sixth master control chips are slave devices of the fifth interconnection bus.
Optionally, the master control chip has a plurality of the serial peripheral interfaces, wherein at least two of the serial peripheral interfaces support a master-slave mode.
The utility model also provides a motherboard comprising the multi-chip interconnection device.
The utility model also provides electronic equipment, which comprises the main board.
The embodiment of the utility model has the following advantages:
in the embodiment of the utility model, the plurality of main control chips are interconnected through the interconnection bus which is a serial peripheral interface bus or an analog serial peripheral interface bus, and the interconnection bus has simple protocol, is beneficial to operation and is a non-point-to-point connection bus. Meanwhile, the interconnection bus occupies fewer pins on the main control chip when being connected to the main control chip, saves space for the PCB component while saving pins of the chip, and reduces the complexity of PCB design wiring. In addition, for the main control chip connected with at least two interconnection buses, the main control chip can be a slave device or a master device, so that the main control chip can actively initiate access, and information interaction among a plurality of different main control chips is facilitated.
Drawings
FIG. 1 is a block diagram of a multi-chip interconnect apparatus according to an embodiment of the present utility model;
FIG. 2 is a block diagram of a first master control chip and a second master control chip interconnected in an embodiment of the utility model;
FIG. 3 is a block diagram illustrating an interconnection structure of three third main control chips according to an embodiment of the present utility model;
FIG. 4 is a block diagram illustrating the interconnection of four fourth host chips in an embodiment of the present utility model;
Fig. 5 is a block diagram of a fifth main control chip and a sixth main control chip interconnected in an embodiment of the present utility model.
Detailed Description
In order that the above-recited objects, features and advantages of the present utility model will become more readily apparent, a more particular description of the utility model will be rendered by reference to the appended drawings and appended detailed description.
In the field of computers, there is a need for data/signal transmission between multiple chips, and based on this need, a PCIE bus or an OTG bus is generally used to interconnect two chips. The PCIE bus belongs to a high-speed bus, and at least a plurality of pairs of differential signals and single-ended signals are required to be connected to realize communication during bus transmission, and more signal pins are required to be occupied by more signals, so that hardware design is complex; secondly, the PCIE protocol includes requirements of device detection, rate negotiation, bit width connection, etc., the overall protocol is complex, which is not beneficial to operation, and in addition, the PCIE bus can only perform point-to-point connection. The OTG bus also belongs to a high-speed bus, the inter-chip interconnection mainly comprises 1 pair of differential signals, the design requirement on a PCB (Printed Circuit Board, a printed circuit board) is high, the USB protocol comprises three modes of low speed, full speed and high speed, handshake negotiation and the like can be carried out among different modes, the whole protocol is complex, the operation is not facilitated, in addition, the OTG bus can only carry out point-to-point connection, in the mode of point-to-point connection, the number of buses is large and long, the bus utilization rate is low and the expansion is difficult.
Referring to fig. 1, an embodiment of the present utility model provides a multi-chip interconnection apparatus, including a plurality of main control chips, where the plurality of main control chips are interconnected by an interconnection bus, where the interconnection bus is a serial peripheral interface bus or an analog serial peripheral interface bus, and each main control chip is connected with at least one interconnection bus; at least one main control chip in the plurality of main control chips is connected with at least two interconnection buses, and the at least one main control chip is a master device of at least one interconnection bus and is a slave device or master device of other interconnection buses; the main control chip is provided with a serial peripheral interface, and the serial peripheral interface is used for connecting a serial peripheral interface bus; and/or the main control chip is provided with a general input/output interface group, wherein the general input/output interface group comprises a plurality of general input/output interfaces, and the general input/output interface group is used for being connected with an analog serial peripheral interface bus.
Specifically, the multi-chip interconnection device is specifically applied to electronic equipment, and the electronic equipment can be a computer, an embedded device and the like. In a highly reliable application scenario, a plurality of main control chips are generally required to communicate, so that the reliability of system operation is ensured. The equipment controlled by the plurality of main control chips is the same, and the plurality of main control chips communicate to mutually check whether the data received by the main control chips are consistent. SPI (SERIAL PERIPHERAL INTERFACE ) bus is a high-speed, synchronous, full duplex, master-slave supporting bus, and occupies very few pins on the chip, saves chip pins, saves space for PCB layout, and reduces the complexity of PCB design routing. The SPI bus is typically made up of four wires that occupy only four pins when connected to the chip, which occupies very few pins on the chip compared to at least ten pins on the chip that are required for PCIE buses.
In the SPI bus, the master device can actively initiate access to the slave device, and the slave device responds according to the request content after receiving the request of the master device, so that multiparty communication based on the SPI bus is realized. The number of the main control chips can be more than or equal to two and less than or equal to sixteen. The number of the interconnection buses connected with the main control chip can be one, two, three, four and the like.
Referring to fig. 2, two master control chips in fig. 2 are connected to two interconnection buses, and the two master control chips are both a master device of one interconnection bus and a slave device of the other interconnection bus. Referring to fig. 3, the three master control chips in fig. 3 are all connected with two interconnection buses, wherein one master control chip is a master device of one interconnection bus and is a slave device of the other interconnection bus. Referring to fig. 4, the four master control chips in fig. 4 are all connected with three interconnection buses, and are all master devices of at least one interconnection bus and slave devices of at least one interconnection bus. When the number of the main control chips is greater than four, the connection modes of the plurality of main control chips can be designed according to actual requirements based on the scheme provided by the embodiment of the utility model, for example, the connection modes can be designed based on any one of the connection modes shown in fig. 2 to 4, and the connection modes shown in fig. 2 to 5 can be combined.
The SPI bus is the bus that actually connects the two serial peripheral interfaces. An analog serial peripheral interface bus refers to a bus that connects a set of universal Input/Output interfaces, the function of which is consistent with that of an SPI bus, and which essentially includes four GPIO (General-Purpose Input/Output) buses. The serial peripheral interface may include four pins, SCLK pin, MOSI pin, MISO pin, CS/SS pin, respectively, and the SPI bus consists of four lines corresponding to the four pins. The SCLK pin is used to send out clock signal, the CS/SS pin is used to send out chip select signal to control which slave the master chip communicates with, one line connected to MOSI pin is used for master to output slave to input, and one line connected to MISO pin is used for master to input slave to output.
The serial peripheral interfaces on the main control chips can be connected with each other through the SPI bus. The universal input/output interface specifically comprises four universal input/output interfaces. Because the SPI bus protocol is simple, if the main control chip has no serial peripheral interfaces or the number of the serial peripheral interfaces is insufficient, the serial peripheral interfaces can be simulated through four GPIO interfaces, and at the moment, the four GPIO interfaces respectively correspond to four pins in the serial peripheral interfaces, namely, the function of the SPI interfaces is realized through multiplexing of the GPIO interfaces.
When the SPI interface function is realized through multiplexing of the GPIO interface, the GPIO interface can be configured into an input/output mode, before data transmission is started, a chip selection signal is required to be pulled down so as to realize control of a main control chip to select a slave device, then the data is sequentially sent to the slave device according to the time sequence of an SPI protocol, the slave device can receive the corresponding data according to the protocol, and after the data transmission is completed, the chip selection signal is pulled up so as to finish communication.
In the embodiment of the utility model, the plurality of main control chips are interconnected through the interconnection bus which is a serial peripheral interface bus or an analog serial peripheral interface bus, and the interconnection bus has simple protocol, is beneficial to operation and is a non-point-to-point connection bus. Meanwhile, the interconnection bus occupies fewer pins on the main control chip when being connected to the main control chip, saves space for the PCB component while saving pins of the chip, and reduces the complexity of PCB design wiring. In addition, for a master control chip connected with at least two interconnection buses, the master control chip can be a slave device or a master device, so that the master control chip can actively initiate access. In the embodiment of the utility model, the SPI bus is used for interconnecting a plurality of main control chips, so that the bus protocol is simple, the design is convenient, and the cost is low.
In addition, since the clock signal is controlled by the master device, the slave device does not collect or transmit data when no clock jump exists, and therefore, the master device can complete the control of data transmission through the control of the clock signal.
Referring to fig. 2 to 4, at least two main control chips are interconnected by an interconnection bus.
Specifically, when two main control chips communicate with each other, one main control chip is used as a main device, the other main control chip is used as a slave device, the main control chip used as the main device initiates access, and the main control chip used as the slave device returns corresponding data after receiving a chip selection and command. When at least two main control chips are mutually connected through an interconnection bus, communication between any two main control chips can be realized.
Referring to fig. 2, at least one master control chip connected with at least two interconnection buses includes a first master control chip and a second master control chip, the first master control chip is interconnected with the second master control chip through the first interconnection bus and the second interconnection bus, the first master control chip is a master device of the first interconnection bus, the first master control chip is a slave device of the second interconnection bus, the second master control chip is a slave device of the first interconnection bus, and the second master control chip is a master device of the second interconnection bus.
Specifically, the first interconnection bus and the second interconnection bus differ in that the master device and the slave device of the two are different. The first main control chip is a master device of the first interconnection bus, and the second main control chip is a slave device of the first interconnection bus. The first main control chip is a slave device of the second interconnection bus, and the second main control chip is a master device of the second interconnection bus. In the embodiment of the utility model, the first main control chip and the second main control chip can be the main equipment through the arrangement of the first interconnection bus and the second interconnection bus, namely, the first main control chip and the second main control chip can actively initiate access, and the first interconnection bus and the second interconnection bus can simultaneously realize communication, so that the bandwidth of the interconnection bus is improved.
At least one main control chip is a system-in-chip.
Specifically, the plurality of main control chips may be the same type chips, and in this case, the plurality of main control chips are all system level chips. The plurality of main control chips can also be different types of chips, and at the moment, part of the main control chips are system-level chips, and part of the main control chips can be CPUs (Central Processing Unit, central processing units).
Referring to fig. 3, at least one master control chip connected with at least two interconnection buses includes three third master control chips, each of the three third master control chips is connected with at least two third interconnection buses through at least three third interconnection buses, the third master control chip is a master device of at least one third interconnection bus, and/or the third master control chip is a slave device of at least one third interconnection bus.
Referring to fig. 4, at least one master control chip connected with at least two interconnection buses includes four fourth master control chips, each of the four fourth master control chips is connected with at least three fourth interconnection buses through at least six fourth interconnection buses, and the fourth master control chip is a master device of at least one fourth interconnection bus and is a slave device of at least one fourth interconnection bus.
Specifically, at least n× (n-1)/2 interconnection buses are required to implement two-by-two interconnection of n master control chips, where n is a positive integer greater than or equal to 3. Any two third main control chips are interconnected through at least one third interconnection bus, and any two fourth main control chips are interconnected through at least one fourth interconnection bus. Schematically, fig. 3 shows three third main control chips interconnected by three third interconnection buses, and fig. 4 shows four fourth main control chips interconnected by six fourth interconnection buses. Each third main control chip in fig. 3 is connected with two third interconnection buses, and each fourth main control chip in fig. 4 is connected with three fourth interconnection buses. In fig. 3, at least one third master control chip is used as a master device and a slave device, and in fig. 4, the four fourth master control chips are used as master devices and slave devices.
Referring to fig. 5, the plurality of master control chips includes a fifth master control chip and a plurality of sixth master control chips, the fifth master control chip is connected to the plurality of sixth master control chips through a fifth interconnection bus, the fifth master control chip is a master device of the fifth interconnection bus, and the plurality of sixth master control chips are slave devices of the fifth interconnection bus.
Specifically, the number of the sixth main control chips is greater than or equal to 2, and three sixth main control chips are interconnected with one fifth main control chip as shown in fig. 5. The plurality of sixth main control chips may not be interconnected, but may be interconnected. The fifth main control chip can be interconnected with the first main control chip, the second main control chip, the third main control chip and the fourth main control chip besides being interconnected with the sixth main control chip. In the embodiment of the utility model, the fifth main control chip can be connected with a plurality of sixth main control chips serving as slave devices through one serial peripheral interface, so that interface resources are saved.
It should be noted that the interconnection structures of the four different main control chips shown in fig. 2 to 5 may be arbitrarily combined.
The main control chip is provided with a plurality of serial peripheral interfaces, wherein at least two serial peripheral interfaces support a master-slave mode.
Specifically, the main control chip is provided with four serial peripheral interfaces, wherein two serial peripheral interfaces support a master-slave mode, and the other two serial peripheral interfaces only support a master mode. When the serial peripheral interface which only supports the main mode on the main control chip is connected with the SPI bus, the main control chip is the main equipment of the SPI bus. When the serial peripheral interface supporting the master-slave mode on the master control chip is connected with the SPI bus, the master control chip can be a master device of the SPI bus or a slave device of the SPI bus.
The embodiment of the utility model also provides a mainboard comprising the multi-chip interconnection device provided by any one of the above. The main board comprises the multi-chip interconnection device, so that the multi-chip interconnection device has the beneficial effects and is not repeated here.
The embodiment of the utility model also provides electronic equipment, which comprises the main board. The electronic device includes the main board, so that the electronic device also has the beneficial effects of the main board, and the description is omitted here.
The multi-chip interconnection device, the motherboard and the electronic device provided by the utility model are described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the utility model, and the description of the above examples is only used for helping to understand the method and the core idea of the utility model; the scope of the present utility model is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present utility model, and it is intended to cover the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims. It should be noted that modifications and adaptations to the utility model may occur to one skilled in the art without departing from the principles of the present utility model and are intended to be within the scope of the utility model.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the utility model.
Claims (10)
1. The multi-chip interconnection device is characterized by comprising a plurality of main control chips, wherein a plurality of main control chips are interconnected through an interconnection bus, the interconnection bus is a serial peripheral interface bus or an analog serial peripheral interface bus, and each main control chip is connected with at least one interconnection bus;
at least one master control chip in the plurality of master control chips is connected with at least two interconnection buses, and the at least one master control chip is a master device of at least one interconnection bus and is a slave device or a master device of other interconnection buses;
The main control chip is provided with a serial peripheral interface, and the serial peripheral interface is used for connecting with the serial peripheral interface bus; and/or the main control chip is provided with a general input/output interface group, the general input/output interface group comprises a plurality of general input/output interfaces, and the general input/output interface group is used for being connected with the analog serial peripheral interface bus.
2. The multi-chip interconnect device of claim 1, wherein at least two of the master chips are interconnected by the interconnect bus.
3. The multi-chip interconnection apparatus according to claim 2, wherein at least one of the master control chips to which at least two of the interconnection buses are connected includes a first master control chip and a second master control chip, the first master control chip is interconnected with the second master control chip through a first interconnection bus and a second interconnection bus, the first master control chip is a master device of the first interconnection bus, the first master control chip is a slave device of the second interconnection bus, the second master control chip is a slave device of the first interconnection bus, and the second master control chip is a master device of the second interconnection bus.
4. The multi-chip interconnect device of claim 1, wherein at least one of the master chips is a system-on-chip.
5. The multi-chip interconnection device according to claim 2, wherein at least one of the master control chips connected with at least two of the interconnection buses includes three third master control chips, the three third master control chips are interconnected in pairs by at least three of the third interconnection buses, each of the third master control chips is connected with at least two of the third interconnection buses, the third master control chip is a master device of at least one of the third interconnection buses, and/or the third master control chip is a slave device of at least one of the third interconnection buses.
6. The multi-chip interconnection apparatus according to claim 2, wherein at least one of the master control chips connected with at least two of the interconnection buses includes four fourth master control chips, the four fourth master control chips are interconnected in pairs by at least six fourth interconnection buses, each of the fourth master control chips is connected with at least three of the fourth interconnection buses, and the fourth master control chip is a master device of at least one of the fourth interconnection buses and is a slave device of at least one of the fourth interconnection buses.
7. The multi-chip interconnect device of any one of claims 1 to 6, wherein the plurality of master chips includes a fifth master chip and a plurality of sixth master chips, the fifth master chip is connected to the plurality of sixth master chips through a fifth interconnect bus, the fifth master chip is a master device of the fifth interconnect bus, and the plurality of sixth master chips are slave devices of the fifth interconnect bus.
8. The multi-chip interconnect device of any of claims 1 to 6, wherein the master chip has a plurality of the serial peripheral interfaces, wherein at least two of the serial peripheral interfaces support a master-slave mode.
9. A motherboard comprising the multi-chip interconnect device of any one of claims 1 to 8.
10. An electronic device comprising the motherboard of claim 9.
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| CN202323562346.4U CN221899549U (en) | 2023-12-25 | 2023-12-25 | Multi-chip interconnection device, main board and electronic equipment |
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| CN202323562346.4U CN221899549U (en) | 2023-12-25 | 2023-12-25 | Multi-chip interconnection device, main board and electronic equipment |
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