CN221352756U - Semiconductor packaging structure, semiconductor power module and equipment - Google Patents
Semiconductor packaging structure, semiconductor power module and equipment Download PDFInfo
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- CN221352756U CN221352756U CN202322676957.5U CN202322676957U CN221352756U CN 221352756 U CN221352756 U CN 221352756U CN 202322676957 U CN202322676957 U CN 202322676957U CN 221352756 U CN221352756 U CN 221352756U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
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- 230000009467 reduction Effects 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model discloses a semiconductor packaging structure, a semiconductor power module and equipment, wherein the semiconductor packaging structure comprises: the power device comprises a substrate, at least one power chip, a plurality of power terminals and at least one driving terminal. The base plate includes drain electrode power conducting layer and the drive conducting layer that the interval set up, and drain electrode power conducting layer is located to power chip, and power chip's drain electrode and drain electrode power conducting layer electricity are connected, and power chip's drive pole is connected with the drive conducting layer electricity, and a plurality of power terminals are connected with power chip's source and drain electrode power conducting layer electricity respectively, and drive terminal is connected with the drive conducting layer electricity, and drive terminal and power terminal are located the different sides of base plate respectively. Therefore, the width of the power terminal can be increased under the same device size, the current passing capability of the power terminal is improved, the influence of parasitic inductance on the operation of the semiconductor packaging structure is reduced, the possibility of coupling mutual inductance between a driving loop where the driving terminal is positioned and the power loop where the power terminal is positioned can be effectively reduced, and the interference of the power loop on the driving loop is reduced.
Description
Technical Field
The present utility model relates to the field of electrical and electronic technologies, and in particular, to a semiconductor package structure, a semiconductor power module, and a device.
Background
The semiconductor packaging structure is a core device for realizing electric energy conversion in the power electronic conversion device, but the through-flow capacity of a single power chip is limited due to the limitation of process and yield.
In the prior art, the power terminal of the semiconductor packaging structure has poor current passing capability; and the CLIP/bonding wire connected with the power terminal is too close to the bonding wire of the driving terminal and is arranged in parallel, so that large coupling mutual inductance can be introduced, and the driving circuit can be influenced by current change in a power circuit where the power terminal is positioned.
Disclosure of utility model
The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, a first object of the present utility model is to provide a semiconductor package structure, which improves the current capacity and reduces the interference of the power circuit to the driving circuit.
A second object of the present utility model is to provide a semiconductor power module, which includes the semiconductor package structure described above.
A third object of the present utility model is to provide an apparatus comprising the above-mentioned semiconductor package.
A semiconductor package structure according to an embodiment of the first aspect of the present utility model includes: the power chip is arranged on the drain power conducting layer, the drain of the power chip is electrically connected with the drain power conducting layer, and the driving electrode of the power chip is electrically connected with the driving conducting layer; the power terminals are respectively and electrically connected with the source electrode and the drain electrode of the power chip, the driving terminals are electrically connected with the driving conductive layers, and the driving terminals and the power terminals are respectively positioned on different sides of the substrate.
According to the semiconductor packaging structure provided by the embodiment of the utility model, the driving terminal and the power terminal are respectively positioned at different sides of the substrate, so that the width of the power terminal can be increased under the same device size, the current passing capability of the power terminal is improved, the influence of parasitic inductance on the operation of the semiconductor packaging structure is reduced, the distance between the power terminal and the driving terminal is far due to the fact that the driving terminal and the power terminal are positioned at different sides, the possibility of coupling mutual inductance between a driving loop where the driving terminal is positioned and a power loop where the power terminal is positioned can be effectively reduced, and the interference of the power loop on the driving loop is reduced.
In some embodiments, the driving terminal and the power terminal are respectively located at opposite sides of the substrate in the first direction.
In some embodiments, the drain power conductive layer and the driving conductive layer are sequentially arranged along a first direction.
In some embodiments, the drive terminal is located in the middle of the side of the substrate.
In some embodiments, the drive conductive layer includes a drive gate conductive layer extending in a second direction, the drive gate conductive layer disposed adjacent the drive terminal; the drive pole includes: and the driving grid electrode is electrically connected with the driving grid electrode conducting layer.
In some embodiments, the driving conductive layer includes: a driving source electrode conductive layer extending in the second direction, the driving source electrode conductive layer being disposed adjacent to the driving terminal; the drive pole includes: and the driving source electrode is electrically connected with the driving source electrode conducting layer.
In some embodiments, the drive source conductive layer and the drive gate conductive layer are parallel to each other.
In some embodiments, the driving source conductive layer and the driving gate conductive layer extend in a second direction, and the power terminal and the driving terminal are arranged in a first direction, the first direction and the second direction being perpendicular.
In some embodiments, the drive source conductive layer and the drive gate conductive layer are elongated.
In some embodiments, the power terminal comprises: and the source electrode is positioned on the same side of the substrate.
In some embodiments, the drain power terminal is electrically connected with the drain power conductive layer.
In some embodiments, the source power terminal is electrically connected with a source of the power chip.
In some embodiments, the power terminal is electrically connected to the drain power conductive layer and the source of the power chip, respectively, by a bond wire.
In some embodiments, the source power terminal has a width W 1, the semiconductor package has a width L, and the W 1, L satisfy: w 1 is more than 0 and less than L/2; and/or the width of the drain power terminal is W 2, the width of the semiconductor packaging structure is L, and the W 2, L satisfy: w 2 is more than 0 and less than L/2.
In some embodiments, the drive terminal includes: a source drive terminal and a gate drive terminal, both of which are located on the same side of the substrate.
In some embodiments, the source drive terminal is electrically connected to the drive source through the drive source conductive layer.
In some embodiments, the gate drive terminal is electrically connected to the drive gate through the drive gate conductive layer.
In some embodiments, the source drive terminal and the gate drive terminal have widths H, respectively, that satisfy: h is more than or equal to 1mm and less than or equal to 2mm.
In some embodiments, the power chips are a plurality of, and the power chips are arranged at intervals along the second direction.
In some embodiments, the plurality of power chips are divided into a plurality of groups of power chips, each group of power chips comprising two of the power chips; the drain power terminal comprises a plurality of drain power terminal parts, the plurality of drain power terminal parts are respectively positioned at two sides of the source power terminal, and the plurality of drain power terminal parts are electrically connected with the drain power conducting layer.
In some embodiments, the drain power terminal is electrically connected to the drain power conductive layer through a first connection tab.
In some embodiments, the source power terminal is electrically connected to the power chip through a second connection pad.
In some embodiments, at least one through hole is formed on the second connecting piece, and the through hole is located between two adjacent power chips.
In some embodiments, one end of each of the adjacent two power chips is exposed from the through hole.
In some embodiments, the drive conductive layer and the drive electrode are electrically connected by a first bond wire, and the drive conductive layer and the drive terminal are electrically connected by a second bond wire.
In some embodiments, the substrate further comprises: and the source power conducting layer is arranged at intervals with the drain power terminal, and is electrically connected with the source and the power terminal respectively.
In some embodiments, the source power conductive layer is disposed between the drain power conductive layer and the power terminal.
A semiconductor power module according to an embodiment of the second aspect of the present utility model includes a semiconductor package structure as claimed in any one of the above.
An apparatus according to an embodiment of the third aspect of the present utility model comprises a semiconductor package as defined in any one of the preceding claims.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic cross-sectional view of a power terminal according to an embodiment of the present utility model.
Fig. 2 is a schematic distribution diagram of conductive layers and terminals according to an embodiment of the present utility model.
Fig. 3 is a schematic diagram of connection in a bonding wire connection manner inside a semiconductor package structure according to an embodiment of the present utility model.
Fig. 4 is a schematic diagram of a connection in a CLIP connection manner inside a semiconductor package according to an embodiment of the present utility model.
Fig. 5 is an equivalent circuit diagram of a semiconductor package structure according to an embodiment of the present utility model.
Fig. 6 is a schematic diagram of a connection in a CLIP connection manner inside a semiconductor package according to another embodiment of the present utility model.
Reference numerals:
100. a semiconductor package structure;
10. A substrate; 11. a drain power conductive layer; 12. driving the conductive layer; 121. a driving source electrode conductive layer; 122. a driving gate conductive layer; 13. a second metal layer; 14. an insulating layer;
20. A power chip; 21. a first power chipset; 22. a second power chipset; 23. a first power chip; 24. a second power chip; 25. a source electrode; 26. driving a source electrode; 27. driving the grid electrode;
30. A power terminal; 31. a source power terminal; 32. a drain power terminal; 321. a drain power terminal portion; 33. a first connecting piece; 34. a second connecting piece; 341. a first connection sub-sheet; 342. a second connector sub-sheet; 343. a through hole;
40. A drive terminal; 41. a source drive terminal; 42. a gate driving terminal;
50. A plastic package shell;
60. and (5) a solder layer.
Detailed Description
Embodiments of the present utility model are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary, and a semiconductor package structure 100 according to an embodiment of the present utility model is described below with reference to fig. 1 to 6, the semiconductor package structure 100 including: a substrate 10, at least one power chip 20, a plurality of power terminals 30, at least one drive terminal 40.
Specifically, as shown in fig. 1 to 6, the substrate 10 includes a drain power conductive layer and a driving conductive layer 12 disposed at intervals, the power chip 20 is disposed on the drain power conductive layer, the drain of the power chip 20 is electrically connected to the drain power conductive layer 11, the driving electrode of the power chip 20 is electrically connected to the driving conductive layer 12, the plurality of power terminals 30 are electrically connected to the source and drain power conductive layers of the power chip 20, the driving terminal 40 is electrically connected to the driving conductive layer 12, and the driving terminal 40 and the power terminals 30 are disposed on different sides of the substrate 10.
The substrate 10 includes a first metal layer configured as a drain power conductive layer, a second metal layer 13 configured as a heat conductive layer of the semiconductor package structure 100 as a main heat dissipation of the semiconductor package structure 100, and an insulating layer 14 disposed between the first metal layer and the second metal layer 13. The insulating layer 14 may be a ceramic layer, which can be used to provide insulation inside the substrate 10 and to ensure good heat dissipation capability of the substrate 10. The substrate 10 may be an AMB (ACTIVE METAL Brazing: active metal brazing) substrate. The power chip 20 may be connected to a side of the drain power conductive layer away from the heat conductive layer 13 through a sintering process, and the power chip 20 is disposed in the middle of the semiconductor package structure 100, and a solder layer 60 is further disposed between the power chip 20 and the drain power conductive layer, so that the power chip 20 is soldered on the substrate 10.
On the semiconductor package structure 100, the drain power conductive layer and the driving conductive layer 12 are disposed at intervals along the first direction a, the drain power conductive layer and the driving conductive layer 12 are disposed between the power terminal 30 and the driving terminal 40, and the power terminal 30 is disposed adjacent to the drain power conductive layer and the driving terminal 40 is disposed adjacent to the driving conductive layer 12.
It is understood that the driving terminal 40 and the power terminal 30 are disposed at different sides of the substrate 10, and that the driving terminal 40 and the power terminal 30 are disposed at two sides of the substrate 10 along the first direction a, or that the driving terminal 40 and the power terminal 30 are disposed at two adjacent sides of the substrate 10, to increase the distance between the power terminal 30 and the driving terminal 40, and to avoid interference between the circuits of the power terminal 30 and the driving terminal 40. The drain power terminal 32 is directly connected to the drain power conductive layer, preferably by ultrasonic welding; the power chip 20 is connected to the source power terminal 31, preferably by sintering.
The plastic package case 50 is formed on the semiconductor package structure 100 to seal the semiconductor package structure 100, thereby protecting and supporting the semiconductor package structure 100, and at least a portion of the substrate 10, such as the second metal layer 13, leaks out of the bottom of the plastic package case 50 during the molding process to dissipate heat of the semiconductor package structure 100. Moreover, the power terminal 30 and the driving terminal 40 at least partially extend out of the plastic package housing to be connected with an external circuit, and the shape of the portion extending out of the plastic package housing 50 can be processed into different shapes according to requirements, so that the connection with the external circuit can be realized in a mode of being suitable for a plurality of different processes, such as jack welding, surface mount welding or laser welding. The power chip 20 and the power terminal 30 or the driving terminal 40 may be connected by bonding wires or by CLIP (copper sheet plus bonding wires). The power chip 20 is a SiC MOSFET power chip.
According to the semiconductor package structure 100 of the embodiment of the present utility model, the driving terminal 40 and the power terminal 30 are respectively located at different sides of the substrate 10, so that the width of the power terminal 30 can be increased under the same device size, the current passing capability of the power terminal 30 is improved, the influence of parasitic inductance on the operation of the semiconductor package structure 100 is reduced, the distance between the driving terminal 30 and the driving terminal 40 is far due to the fact that the driving terminal 40 and the power terminal 30 are located at different sides, the possibility of coupling mutual inductance between the driving circuit where the driving terminal 40 is located and the power circuit where the power terminal 30 is located can be effectively reduced, and the interference of the power circuit on the driving circuit is reduced.
Preferably, as shown in fig. 2 to 5, in the present embodiment, the driving terminal 40 and the power terminal 30 are respectively located at both sides of the substrate 10 opposite to each other in the first direction a. That is, the driving terminals 40 and the power terminals 30 are disposed on two sides of the substrate 10 along the arrangement direction of the drain power conductive layer and the driving conductive layer 12, i.e., the first direction a, at this time, the distance between the driving terminals 40 and the power terminals 30 is the largest, and the distance between the driving circuit where the driving terminals 40 are located and the power circuit where the power terminals 30 are located is the largest, so that the driving circuit and the power circuit can be prevented from crossing, the coupling mutual inductance between the driving circuit and the power circuit can be effectively avoided, and the influence of the current variation on the power circuit on the driving circuit can be reduced.
In some embodiments, as shown in fig. 3 and 4, the drain power conductive layer 11 and the driving conductive layer 12 are sequentially arranged in the first direction a. The drain power conductive layer and the driving conductive layer 12 are sequentially arranged in a direction from the power terminal 30 toward the driving terminal 40. Along the first direction a, the drain power conductive layer and the driving conductive layer 12 are sequentially arranged towards a direction far away from the power terminal 30, so that the drain power conductive layer is arranged adjacent to the power terminal 30, the driving conductive layer 12 is arranged adjacent to the driving terminal 40, electric connection between the power terminal 30 and the drain power conductive layer is avoided, meanwhile, electric connection between the driving conductive layer 12 and the driving terminal 40 is also facilitated, the power terminal 30, the driving terminal 40, the drain power conductive layer and the driving conductive layer 12 can be reasonably distributed on the substrate 10, the utilization rate of space on the substrate 10 is increased, and mutual interference between a driving loop and the power loop is avoided.
In some embodiments, as shown in fig. 6, the driving terminal 40 is located at the middle of the side of the substrate 10. For example, the substrate 10 is provided with a driving terminal 40 on a side opposite to the power terminal 30, the driving terminal 40 is provided on a side of the substrate 10 away from the power terminal 30 along the first direction a, and the driving terminal 40 is provided adjacent to a center of the substrate 10 on a side wall of the side. That is, at this time, the driving terminal 40 is disposed on one side of the substrate 10 along the first direction a and the power terminals 30 are disposed on two sides of the driving terminal 40 along the first direction a, so that when the driving terminal 40 is electrically connected with different power chips 20, it can be ensured that bonding wires or copper sheets for electrical connection between the driving terminal 40 and the different power chips 20 are equal in equidistance, so that driving loops between the different power chips 20 are symmetrical about the first direction a, thereby reducing the difference between the driving loops of the different power chips 20 and reducing the influence of the driving loops on the performance of the power chips 20.
In some embodiments, as shown in fig. 2 and 3, the drive conductive layer 12 includes a drive gate conductive layer 122, the drive conductive layer 12 extending in the second direction B, the drive gate conductive layer 122 being disposed adjacent to the drive terminal 40. The drive pole includes: the drive gate 27, the drive gate 27 and the drive gate conductive layer 122 are electrically connected. The driving terminal 40 is adjacent to the driving gate conductive layer 122 disposed on the substrate 10, so that the length of a bonding wire between the driving terminal 40 and the driving gate conductive layer 122 can be shortened, the space inside the semiconductor package structure 100 is optimized, meanwhile, the driving gate 27 and the driving gate conductive layer 122 are correspondingly convenient to realize electrical connection, and the arrangement of the driving gate 27 is conducive to realizing accurate connection of the power chip 20 and the driving conductive layer 12, so that the connection rate of the semiconductor package structure 100 is improved.
Further, with reference to fig. 2 and 3, the driving conductive layer 12 includes: the driving source conductive layer 121, the driving source conductive layer 121 extends along the second direction B, and the driving source conductive layer 121 is disposed adjacent to the driving terminal 40. The drive pole includes: the driving source electrode 26, the driving source electrode 26 and the driving source conductive layer 121 are electrically connected. That is, the driving conductive layer 12 includes the driving source conductive layer 121 and the driving gate conductive layer 122, the driving electrode includes the driving gate 27 and the driving source 26, when the driving conductive layer 12 is electrically connected with the driving electrode of the power chip 20, the driving source conductive layer 121 is electrically connected with the driving source 26, and the driving gate conductive layer 122 is electrically connected with the driving gate 27, so that the power chip 20 is electrically connected with the driving conductive layer 12 without cross mutual inductance between bonding wires for connection, and the mounting efficiency of the semiconductor package structure 100 can be improved.
In some embodiments, as in fig. 2-6, the drive source conductive layer 121 and the drive gate conductive layer 122 are parallel to each other in the first direction a. Thus, the driving source electrode conductive layer 121 and the driving gate electrode conductive layer 122 are arranged in parallel, so that the driving gate electrode conductive layer 122 and the driving source electrode conductive layer 121 can be conveniently arranged, the inductance influence between the driving source electrode conductive layer 121 and the driving gate electrode conductive layer 122 is reduced, the structure of the driving conductive layer 12 is optimized, and the driving conductive layer 12 is conveniently arranged on the substrate 10.
Alternatively, as shown in fig. 2, the driving source conductive layer 121 and the driving gate conductive layer 122 extend in the second direction B, and the power terminal 30 and the driving terminal 40 are arranged in the first direction a, which is perpendicular to the second direction B. Thus, the positions and arrangement of the driving conductive layer 12, the driving terminals 40 and the power terminals 30 on the substrate 10 can increase the utilization of the space in the substrate 10, optimize the space in the semiconductor package structure 100, and facilitate the miniaturization and integration design of the semiconductor package structure 100.
In some embodiments, referring to fig. 2, the driving source conductive layer 121 and the driving gate conductive layer 122 extend along the second direction B in a strip shape, so as to increase the utilization of the space in the substrate 10, and avoid the cross mutual inductance of the driving source conductive layer 121 and the driving gate conductive layer 122, which affects the flow of current.
As shown in fig. 2, the power terminal 30 includes: the drain power terminal 32 and the source power terminal 31, and the source 25 drain power terminal 32 and the source power terminal 31 are located on the same side of the substrate 10. In the present embodiment, the drain power terminal 32 and the source power terminal 31 are provided on the same side of the substrate 10 along the first direction a of the substrate 10. The drain power terminal 32 is electrically connected to the drain power conductive layer 11, and the drain power conductive layer 11 is electrically connected to the drain of the power chip 20. The source power terminal 31 is electrically connected to the source 25 of the power chip 20.
Alternatively, if a source power conductive layer is provided between the source power terminal 31 and the source 25 of the power chip 20, the source power conductive layer is electrically connected to the source power terminal 31 and the source 25 of the power chip 20 respectively through bonding wires or copper sheets.
In the embodiment of fig. 3, the power terminals 30 are electrically connected to the drain power conducting layer 11 and the source 25 of the power chip 20, respectively, by bonding wires. That is, the power terminal 30 includes a source power terminal 31 and a drain power terminal 32, the source power terminal 31 and the source 25 are connected by a bonding wire, and the drain power terminal 32 and the drain power conductive layer 11 are connected by a bonding wire. Thus, the bonding wire connection can facilitate the electrical connection between the power terminal 30 and the power chip 20 and the drain power conductive layer 11, and can be flexibly arranged in the semiconductor package structure 100, so that the connection structure is simplified, and the connection reliability is ensured.
In some embodiments, in conjunction with fig. 2, the source power terminal 31 has a width W 1, the semiconductor package 100 has a width L, W 1, L satisfies: w 1 is more than 0 and less than L/2; or the width of the drain power terminal 32 is W 2, the width of the semiconductor package 100 is L, W 2, L satisfies: w 2 is more than 0 and less than L/2. The widths of the source power terminal 31 and the drain power terminal 32 in the second direction B are equal in the present embodiment. Thereby, the widths of the source power terminal 31 and the drain power terminal 32 are defined so as to facilitate the arrangement of the power terminal 30 on one side of the substrate 10 in the first direction a, avoid contact between the source power terminal 31 and the drain power terminal 32, and simultaneously ensure the arrangement width of the power terminal 30 to the maximum extent so as to enhance the current-passing capability thereof.
In some embodiments, the drive terminal 40 includes: the source driving terminal 41 and the gate driving terminal 42, the source driving terminal 41 and the gate driving terminal 42 are located on the same side of the substrate 10 and are disposed at intervals along the second direction B. In order to facilitate the correspondence of the driving terminals 40 with the respective driving conductive layers 12, the gate driving terminals 42 are opposite to the driving gate conductive layers 122 along the first direction a, and the source driving terminals 41 are opposite to the driving source conductive layers 121 along the first direction a. Thereby ensuring that the connecting piece for connecting the gate driving terminal 42 and the driving gate conductive layer 122 and the connecting piece for connecting the source driving terminal 41 and the driving source conductive layer 121 are mutually parallel, avoiding the cross generation of coupling mutual inductance between the two connecting pieces, reducing the influence between circuits where the gate driving terminal 42 and the source driving terminal 41 are positioned, ensuring the performance of the circuits, improving the stability and avoiding the circuit failure.
In some embodiments, as shown in fig. 3, the source driving terminal 41 is electrically connected with the driving source 26 through the driving source conductive layer 121. The gate driving terminal 42 is electrically connected to the driving gate 27 through the driving gate conductive layer 122.
In some embodiments, referring to fig. 2, the widths of the source driving terminal 41 and the gate driving terminal 42 are H, respectively, satisfying: h is more than or equal to 1mm and less than or equal to 2mm. For example, h=1.5 mm. Thereby, the widths of the source driving terminal 41 and the gate driving terminal 42 in the second direction B are defined, so that the driving terminal 40 is provided on the substrate 10 at one side of the substrate 10 in the first direction a, reducing the possibility of mutual inductance between the source driving terminal 41 and the gate driving terminal 42.
The power chip 20 is provided with a source electrode 25, a driving source electrode 26 and a driving gate electrode 27, and when the devices are required to be connected, the source electrode 25 on the power chip 20 is electrically connected to the source electrode power terminal 31, the driving source electrode 26 is electrically connected to the driving source electrode conductive layer 121, and the driving gate electrode 27 is electrically connected to the driving gate electrode conductive layer 122. And the driving source electrode conductive layer 121 and the source electrode driving terminal 41 are electrically connected, the driving gate electrode conductive layer 122 and the gate electrode driving terminal 42 are electrically connected, and the power chip 20 is connected to the driving terminal 40 through the driving conductive layer 12 to realize communication of a driving circuit. Meanwhile, the drain power terminal 32 and the drain power conductive layer 11 disposed on the substrate 10 are electrically connected, and the source power terminal 31 is electrically connected with the driving source 26, so that the source driving terminal 41 and the power chip 20 are directly electrically connected, which can reduce the resistance and parasitic inductance introduced in the packaging process of the semiconductor packaging structure 100, and improve the current passing capability of the source power terminal 31.
In some embodiments, as shown in fig. 2-4, the power chips 20 are plural, and the plural power chips 20 are spaced apart along a direction perpendicular to the arrangement direction of the drain power conductive layer and the driving conductive layer 12, that is, the second direction B.
In this embodiment, the number of the power chips 20 is two, the two power chips 20 include a first power chip 23 and a second power chip 24, and the driving source 26 and the driving gate 27 disposed on the first power chip 23 and the second power chip 24 may be disposed at one end of the first power chip 23 and the second power chip 24 away from each other along the second direction B, so as to facilitate the electrical connection between the first power chip 23 and the second power chip 24 and the driving terminal 40. The arrangement direction of the plurality of power chips 20 is perpendicular to the arrangement direction of the drain power conductive layer and the driving conductive layer 12, so that the utilization of the space in the substrate 10 can be increased, the structure of the semiconductor package structure 100 is more compact, and the miniaturization and the integrated design of the semiconductor package structure 100 are facilitated.
The first power chip 23 and the second power chip 24 are disposed on the drain power conductive layer 11, the source power terminal 31 and the drain power terminal 32 are disposed on one side of the substrate 10, the drain power terminal 32 is electrically connected with the drain power conductive layer 11, the source power terminal 31 is electrically connected with the power chip 20, and the driving source conductive layer 121 and the driving gate conductive layer 122 are electrically connected with the power chip 20 on one side of the power chip 20 away from the power terminal 30, respectively.
Referring to fig. 5, in the equivalent circuit diagram of the present embodiment, the driving source 26 and the source 25 of the plurality of power chips 20 are respectively connected so that the plurality of power chips 20 form a parallel structure, and an interface for connection to an external circuit is provided through a drain power terminal 32 electrically connected to the drain power conductive layer 11 and a source power terminal 31 electrically connected to the source 25 of the power chip 20. The driving gates 27 of the power chips 20 are respectively connected with the driving gate conductive layer 122, and provide a connection interface with an external driving circuit through the gate driving terminal 42, the driving sources 26 of the power chips 20 are mutually connected and connected on the driving source conductive layer 121, and provide an external connection interface through the source driving terminal 41, so that Kelvin connection is formed, and the influence of common source inductance on the switching performance of the power chips 20 is eliminated. Among them, kelvin connection (Kelvin connections) is a simple method for eliminating the effect of voltage drop on the wires in the circuit.
As shown in fig. 6, the plurality of power chips 20 are divided into a plurality of power chip 20 groups, each power chip 20 group including two power chips 20. The drain power terminal 32 includes a plurality of drain power terminal portions 321, the plurality of drain power terminal portions 321 are located on both sides of the source power terminal 31 along the second direction B, and the plurality of drain power terminal portions 321 are electrically connected to the drain power conductive layer 11.
In the present embodiment, the number of the power chip 20 groups and the number of the power chips 20 corresponding to each power chip 20 need to be selected according to the requirements. Here, the plural sets of power chips 20 include a first power chip set 21 and a second power chip set 22, and the first power chip set 21 and the second power chip set 22 each include two power chips 20 as an example. The source power terminal 31 is disposed between two drain power terminal portions 321, the source power terminal 31 is electrically connected to the plurality of power chips 20, the two drain power terminal portions are electrically connected to the drain power conductive layer 11, and the plurality of power chips 20 are disposed at intervals along the second direction B. To facilitate electrical connection of each power chip 20 with the driving conductive layer 12, the two power chips 20 included in the first power chip set 21 and the second power chip set 22 are symmetrically arranged in the first direction a to avoid a bonding wire crossing design for bonding between the power chips 20 and the driving conductive layer 12, and to reduce parasitic inductance between the bonding wires.
Therefore, the drain power terminal 32 includes two drain power terminal portions 321, and the two drain power terminal portions 321 are disposed on two sides of the source power terminal 31, so that the distances from the plurality of power chips 20 to the drain power terminal portions 321 are similar, the layout of the plurality of power chips 20 on the base is facilitated, the arrangement of the plurality of power chips 20 is facilitated, and the current capacity is improved. In addition, in the layout mode, parasitic inductance can be reduced while the current passing capability of the device is improved, and the current sharing performance of the power chips 20 at different positions is ensured
In some embodiments, the drain power terminal 32 is electrically connected to the drain power conductive layer 11 through a first connection tab 33, and the source power terminal 31 is electrically connected to the power chip 20 through a second connection tab 34. The first connection piece 33 is used for connecting the drain power terminal 32 and the drain power conductive layer 11, the second connection piece 34 is used for connecting the source power terminal 31 and the power chip 20, and the first connection piece 33 and the second connection piece 34 may be conductive copper sheets.
In this embodiment, the first connection piece 33 may be integrally formed with the drain power terminal 32 or be a part of the drain power terminal 32, and the second connection piece 34 may be integrally formed with the source power terminal 31 or be a part of the source power terminal 31, where the drain power terminal 32 is directly electrically connected to the drain power conductive layer 11 and the source power terminal 31 is electrically connected to the power chip 20. Thus, the arrangement of the first connection piece 33 and the second connection piece 34 facilitates the electrical connection of the drain power terminal 32 with the drain power conductive layer 11 and the electrical connection of the source power terminal 31 with the power chip 20, simplifying the structure inside the semiconductor package structure 100.
In some embodiments, as shown in fig. 6, at least one through hole 343 is formed on the second connection piece 34, the through hole 343 is located between two adjacent power chips 20, and a portion of the two adjacent power chips 20 is exposed from the through hole 343.
The second connection piece 34 includes a first connection sub-piece 341 and a second connection sub-piece 342, where the first connection sub-piece 341 is connected with the first power chipset 21, the second connection sub-piece 342 is connected with the second power chipset 22, the first connection sub-piece 341 and the second connection sub-piece 342 are both provided with a through hole 343, and the through hole 343 penetrates through the portions of the first connection sub-piece 341 and the second connection sub-piece 342 opposite to the power chips 20, so that the two power chips 20 included in the first power chipset 21 and the second power chipset 22 form a parallel structure, that is, taking the first power chipset 21 as an example, at this time, the two power chips 20 included in the first power chipset 21 are respectively electrically connected with the source power terminal 31.
Thus, the arrangement of the through holes 343 facilitates the parallel connection of the plurality of power chips 20 in the power chip 20 group, thereby improving the current capacity of the semiconductor package structure 100
In some embodiments, as shown in fig. 2-6, the drive conductive layer 12 and the drive electrode of the power chip 20 are electrically connected by a first bond wire, and the drive conductive layer 12 and the drive terminal 40 are electrically connected by a second bond wire. The conductive layers and the terminals in the semiconductor package 100 may be electrically connected by a bonding wire connection method or a CLIP (copper sheet plus bonding wire) connection method.
For example, as shown in fig. 3, the drain power conductive layer is electrically connected to the power terminal 30 and the power chip 20, and the driving conductive layer 12 is electrically connected to the power chip 20 and the driving terminal 40 by bonding wires. As shown in fig. 4 and fig. 6, the power terminals 30 and the power chip 20, and the power terminals 30 and the drain power conductive layer may be directly connected by copper sheets, and the rest parts, such as the driving conductive layer 12, the power chip 20 and the driving terminals 40, are electrically connected by bonding wires, so that the internal structure of the semiconductor package structure 100 is more reasonable, and the production efficiency is improved.
Therefore, the driving conductive layer 12 and the power chip 20 and the driving conductive layer 12 and the driving terminal 40 are electrically connected through the bonding wires, so that the connection structure can be optimized, the first bonding wires and the second bonding wires are prevented from interfering with each other, and particularly for the semiconductor packaging structure 100 connected by using the CLIP connection mode, the space inside the semiconductor packaging structure 100 can be saved, the layout structure is optimized, the resistance and parasitic inductance introduced by packaging are reduced, and the current passing capability is improved.
In some embodiments, the substrate 10 further comprises: and a source power conductive layer provided at a distance from the drain power terminal 32, the source power conductive layer being electrically connected to the source 25 and the power terminal 30, respectively. That is, the substrate 10 further includes a source power conductive layer disposed adjacent to the source power terminal 31, and the source power terminal 31 is electrically connected to the source 25 of the power chip 20 through the source power conductive layer, so that heat generated by the power chip 20 due to direct electrical connection between the source power terminal 31 and the source 25 can be effectively avoided, and the heat dissipation capability of the power chip 20 is improved. At the same time, the electrical connection between the source power terminal 31 and the source 25 is facilitated, increasing the flexibility of the placement of the source power terminal 31 on the substrate 10.
Further, a source power conducting layer is provided between the drain power conducting layer 11 and the power terminal 30, the source power conducting layer being provided adjacent to the power terminal 30. Thus, the source power terminal 31 is disposed between the drain power conductive layer 11 and the power terminal 30, which facilitates connection of the power terminal 30 and the source power conductive layer to the drain power conductive layer 11, shortens the length of the bonding wire between the source power conductive layer and the source power terminal 31, and contributes to reduction of parasitic inductance and reduction of resistance of the source power terminal 31.
The application also provides a semiconductor power module, wherein the semiconductor power module comprises a semiconductor packaging structure with the same or similar technical characteristics.
The present application also provides an apparatus comprising a semiconductor package having the same or similar technical features as described above.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model.
In the description of the utility model, a "first feature" or "second feature" may include one or more of such features. In the description of the present utility model, "plurality" means two or more. In the description of the utility model, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by another feature therebetween. In the description of the utility model, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (29)
1. A semiconductor package structure, comprising:
The substrate comprises drain power conducting layers and driving conducting layers which are arranged at intervals;
The power chip is arranged on the drain power conducting layer, the drain of the power chip is electrically connected with the drain power conducting layer, and the driving electrode of the power chip is electrically connected with the driving conducting layer;
a plurality of power terminals electrically connected with the source electrode and the drain electrode of the power chip respectively;
And at least one driving terminal electrically connected with the driving conductive layer, wherein the driving terminal and the power terminal are respectively positioned on different sides of the substrate.
2. The semiconductor package according to claim 1, wherein the driving terminal and the power terminal are located on opposite sides of the substrate in the first direction, respectively.
3. The semiconductor package according to claim 1, wherein the drain power conductive layer and the driving conductive layer are sequentially arranged along a first direction.
4. The semiconductor package according to claim 1, wherein the driving terminal is located at a middle portion of the side of the substrate.
5. The semiconductor package according to any one of claims 1 to 4, wherein the driving conductive layer includes: a drive gate conductive layer extending in a second direction, the drive gate conductive layer disposed adjacent to the drive terminal;
The drive pole includes: and the driving grid electrode is electrically connected with the driving grid electrode conducting layer.
6. The semiconductor package according to claim 5, wherein the driving conductive layer comprises: a driving source electrode conductive layer extending in the second direction, the driving source electrode conductive layer being disposed adjacent to the driving terminal;
the drive pole includes: and the driving source electrode is electrically connected with the driving source electrode conducting layer.
7. The semiconductor package according to claim 6, wherein the driving source conductive layer and the driving gate conductive layer are parallel to each other.
8. The semiconductor package according to claim 6, wherein the driving source conductive layer and the driving gate conductive layer extend in a second direction, the power terminal and the driving terminal are arranged in a first direction, and the first direction and the second direction are perpendicular.
9. The semiconductor package according to claim 6, wherein the driving source conductive layer and the driving gate conductive layer are elongated.
10. The semiconductor package according to claim 6, wherein the power terminal comprises:
And the source electrode is positioned on the same side of the substrate.
11. The semiconductor package according to claim 10, wherein the drain power terminal is electrically connected to the drain power conductive layer.
12. The semiconductor package according to claim 10, wherein the source power terminal is electrically connected to a source of the power chip.
13. The semiconductor package according to claim 10, wherein the power terminals are electrically connected to the drain power conductive layer and the source of the power chip, respectively, by bonding wires.
14. The semiconductor package according to claim 10, wherein the source power terminal has a width W 1, the semiconductor package has a width L, and the W 1, L satisfy: w 1 is more than 0 and less than L/2; and/or
The width of the drain power terminal is W 2, the width of the semiconductor packaging structure is L, and the widths W 2 and L satisfy the following conditions: w 2 is more than 0 and less than L/2.
15. The semiconductor package according to claim 6, wherein the driving terminal comprises:
A source drive terminal and a gate drive terminal, both of which are located on the same side of the substrate.
16. The semiconductor package according to claim 15, wherein the source drive terminal is electrically connected to the drive source through the drive source conductive layer.
17. The semiconductor package according to claim 15, wherein the gate drive terminal is electrically connected to the drive gate through the drive gate conductive layer.
18. The semiconductor package according to claim 15, wherein widths of the source driving terminal and the gate driving terminal are each H, the H satisfying: h is more than or equal to 1mm and less than or equal to 2mm.
19. The semiconductor package according to claim 6, wherein the plurality of power chips are arranged at intervals along the second direction.
20. The semiconductor package according to claim 10, wherein the plurality of power chips are divided into a plurality of groups of power chip groups, each group of power chip groups including at least two of the power chips;
The drain power terminal comprises a plurality of drain power terminal parts, the plurality of drain power terminal parts are respectively positioned at two sides of the source power terminal, and the plurality of drain power terminal parts are electrically connected with the drain power conducting layer.
21. The semiconductor package according to claim 10, wherein the drain power terminal and the drain power conductive layer are electrically connected by a first connection tab.
22. The semiconductor package structure of claim 10, the source power terminal and the source being electrically connected by a second bond pad.
23. The semiconductor package according to claim 22, wherein the second connecting pad has at least one through hole formed therein, the through hole being located between two adjacent power chips.
24. The semiconductor package according to claim 23, wherein one end of two adjacent power chips adjacent to each other is exposed from the through hole.
25. The semiconductor package according to any one of claims 1 to 4, wherein the driving conductive layer and the driving electrode are electrically connected by a first bonding wire, and the driving conductive layer and the driving terminal are electrically connected by a second bonding wire.
26. The semiconductor package according to claim 10, wherein the substrate further comprises: and the source power conducting layer is arranged at intervals with the drain power terminal, and is electrically connected with the source and the power terminal respectively.
27. The semiconductor package according to claim 26, wherein the source power conductive layer is disposed between the drain power conductive layer and the power terminal.
28. A semiconductor power module comprising a semiconductor package according to any one of claims 1 to 27.
29. An apparatus comprising a semiconductor package structure, wherein the semiconductor package structure is the semiconductor package structure of any one of claims 1 to 27.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119181691A (en) * | 2024-11-25 | 2024-12-24 | 北京怀柔实验室 | Power Devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119181691A (en) * | 2024-11-25 | 2024-12-24 | 北京怀柔实验室 | Power Devices |
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