CN220173220U - Power-on and power-off control circuit and electronic equipment - Google Patents

Abstract

The utility model relates to a power-on and power-off control circuit and electronic equipment. The power-on and power-off control circuit can be connected with the power supply and the power management circuit and comprises a voltage monitoring circuit, a power-on and discharging circuit and a power-on time sequence control circuit. The power-on and power-off control circuit monitors the power interface through the voltage monitoring circuit, controls the power-on and power-off circuit to supply power to the power-on time sequence control circuit when the power interface is electrified, and provides a power-on enabling signal for the power management circuit when the power is supplied for a preset time period, so that the power-on time sequence of the power-on module is ensured to be stable and accurate; when the power interface is powered down, the power-on time sequence control circuit is discharged through the power-on and discharging circuit, so that an accurate and stable power-on enabling signal can be provided when the power is powered on next time; therefore, the power-on and power-off control circuit provides accurate, reliable and stable power-on time sequence when the electronic equipment is powered on every time.

Description

Power-on and power-off control circuit and electronic equipment

Technical Field

The utility model belongs to the technical field of power supply circuits, and particularly relates to a power-on and power-off control circuit and electronic equipment.

Background

At present, in order to ensure reliable operation of the chip, the power-on time sequence of the chip must be satisfied during power-on and power-off, otherwise, the chip may be started abnormally, and even irreversible damage may be caused to the device. It can be seen that the power-up sequence plays an important role in ensuring reliable operation of the hardware system, otherwise the stability of the product or chip is directly affected.

In the traditional power-on time sequence control circuit, power-on and power-off are controlled through a resistor-capacitor circuit or a control chip, and the resistor-capacitor circuit has the problems that the power-on time sequence requirement of a hardware system cannot be guaranteed when power-on and power-off are carried out, namely the problems that the rising edge and the falling edge are too slow, the time sequence control is inaccurate and the stability is low; the control chip is used for controlling the power on and power off, so that the problem of high cost exists.

Disclosure of Invention

The utility model aims to provide a power-on and power-off control circuit and electronic equipment, and aims to solve the problem that the traditional power-on time sequence control circuit is difficult to consider both performance and cost.

The first aspect of the embodiment of the utility model provides a power-on and power-off control circuit which is connected with a power interface and a power management circuit, wherein the power-on and power-off control circuit comprises a voltage monitoring circuit, a power-on and discharging circuit and a power-on time sequence control circuit: the voltage monitoring circuit is used for respectively outputting a power-on signal and a discharge signal to the power-on and discharge circuit when detecting the power-on and power-off of the power interface; the output end of the power-on and discharge circuit is connected with the power-on time sequence control circuit and is used for supplying power to the power-on time sequence control circuit when receiving a power-on signal and discharging the power-on time sequence control circuit when receiving a discharge signal; the power-on time sequence control circuit is connected with the power management circuit and is used for outputting a power-on enabling signal to the power management circuit after the power-on and discharging circuit supplies power for a preset time period so as to enable the power management circuit to supply power.

In one embodiment, the voltage monitoring circuit includes a first capacitor, a diode, and a first resistor; the first end of the first capacitor and the cathode of the diode are commonly connected with the power interface, the second end of the first capacitor is grounded, the anode of the diode and the first end of the first resistor are commonly connected with the controlled end of the power-on and discharging circuit, and the second end of the first resistor is grounded. In one embodiment, the power-on and power-off circuit comprises a power-on circuit and a power-off circuit, wherein an input end of the power-on circuit is connected with the power interface, a controlled end of the power-on circuit is connected with the voltage monitoring circuit, a controlled end of the power-off circuit is connected with the power-on circuit, an input end of the power-off circuit and the power-on time sequence control circuit are connected to an output end of the power-on circuit, and an output end of the power-off circuit is grounded.

In one embodiment, the power-on circuit includes a first switch, a second switch, and a second resistor; the first conducting end of the first switch is an input end of the switch unit, the second conducting end of the first switch is an output end of the switch unit, the first end of the second resistor and the first conducting end of the first switch are commonly connected to the power interface, the second end of the second resistor, the controlled end of the first switch and the first conducting end of the second switch are commonly connected, the second conducting end of the second switch is grounded, and the controlled end of the second switch is connected with the voltage monitoring circuit to receive the power-on signal. In one embodiment, the discharging circuit comprises a third switch and a third resistor; the first end of the third resistor is connected with the second conducting end of the first switch, the second end of the third resistor is connected with the first conducting end of the third switch, the second conducting end of the third switch is grounded, and the controlled end of the third switch, the second end of the second resistor, the controlled end of the first switch and the first conducting end of the second switch are commonly connected. In one embodiment, the first switch is configured to be turned on when the controlled terminal is at a low level and turned off when the controlled terminal is at a high level; the second switch and the third switch are configured to be turned off when the controlled terminal is at a low level and turned on when the controlled terminal is at a high level.

In one embodiment, the power-on time sequence control circuit includes a fourth switch, a fourth resistor, a fifth resistor and a second capacitor; the first end of the second capacitor and the first end of the fifth resistor are connected to the output end of the power-on and discharging circuit, the second end of the second capacitor, the first end of the fourth resistor and the controlled end of the fourth switch are commonly connected, the second end of the fourth resistor is grounded, the second end of the fifth resistor, the first conducting end of the fourth switch and the enabling end of the power management circuit are commonly connected, and the second conducting end of the fourth switch is grounded. In one embodiment, the power-on time sequence control circuits are multiple, the power-on time sequence control circuits are connected in parallel between the power-on and discharging circuits and the power management circuit, and preset durations corresponding to the power-on time sequence control circuits are different, so that the power management circuit can power on the power-on modules according to preset power-on time sequences. In one embodiment, the parameters of the second capacitor in each power-on timing control circuit are different.

A second aspect of an embodiment of the present utility model provides an electronic device, including: the power supply interface, the power-on and power-off control circuit, the power management circuit and the power module are as described above; the power-on and power-off control circuit is connected with the power interface and is used for outputting a power-on enabling signal when the power interface is powered on; the power management circuit is connected with the power interface and the power-on time sequence control circuit and is used for outputting a power supply signal when receiving a power-on enabling signal; the power utilization module is connected with the output end of the power management circuit.

Compared with the related art, the embodiment of the utility model has the beneficial effects that: the power-on and power-off control circuit monitors the power interface through the voltage monitoring circuit, controls the power-on and power-off circuit to supply power to the power-on time sequence control circuit when the power interface is electrified, and provides a power-on enabling signal for the power management circuit when the power is supplied for a preset time period, so that the rising edge is relatively quick, and the power-on time sequence of the power-on module is ensured to be stable and accurate; when the power interface is powered down, the power-on time sequence control circuit is discharged through the power-on and discharging circuit, so that the falling edge is also quicker, and an accurate and stable power-on enabling signal can be provided when the power-on is next time; and the power-on and power-off control circuit has lower cost.

Drawings

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the present utility model;

fig. 2 is a schematic diagram of a power-on/power-off control circuit according to an embodiment of the present utility model;

fig. 3 is a specific circuit diagram of a power-on/power-off control circuit according to another embodiment of the present utility model;

FIG. 4 is a circuit diagram of a power-on/power-off control circuit according to an embodiment of the present utility model;

FIG. 5 is a voltage waveform diagram corresponding to a power-on timing control circuit according to an embodiment of the present utility model;

fig. 6 is a voltage waveform diagram corresponding to a power-up timing control circuit according to an embodiment of the present utility model when power is down.

The above figures illustrate: 100. an electronic device; 10. a power-on and power-off control circuit; 101. a voltage monitoring circuit; 102. a power-up and discharge circuit; 1021. a power-on circuit; 1022. a discharge circuit; 103. a power-on time sequence control circuit; 1031. a first power-on timing control circuit; 1032. a second power-on timing control circuit; 1033. a third power-on timing control circuit; 20. a power interface; 30. a power management circuit; 40. an electricity utilization module; 200. and a power supply.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the present utility model, and for convenience of explanation, only the portions related to the embodiment are shown, which are described in detail below:

the electronic device 100 includes a power-on/power-off control circuit 10, a power interface 20, a power management circuit 30, and a power module 40. The power interface 20 is used for connecting a power supply 200, the input end and the output end of the power management circuit 30 are respectively connected with the power interface 20 and the power utilization module 40, the enabling end of the power management circuit 30 is connected with the power-on and power-off control circuit 10, the power-on and power-off control circuit 10 is connected with the power interface 20 and is used for sending a power-on enabling signal to the power management circuit 30 after the power interface 20 is powered on, and the power management circuit 30 is used for outputting a power supply signal when receiving the power-on enabling signal so as to supply power for the power utilization module 40. The power-on sequence of the power module 40 can be controlled by the power-on and power-off control circuit 10 to ensure the normal operation of the power module 40.

The power consumption module 40 may be multiple, and the power-on time sequences required by the multiple power consumption modules 40 are the same, partially the same or different, and the electronic device 100 may be a depth camera, a color camera, a mobile phone, an intelligent door lock, etc., for example, when the electronic device 100 is a depth camera, the power consumption module 40 may be any one of a depth computing chip, a laser emission module, a first infrared imaging module, a second infrared imaging module, a color imaging module, or a proximity sensor. In an embodiment, the electronic device 100 includes six power consumption modules 40, and the six power consumption modules 40 are a depth calculating chip, a laser emitting module, a first infrared imaging module, a second infrared imaging module, a color imaging module and a proximity sensor, respectively. The power-on sequence of the depth calculation chip, the laser emission module, the first infrared imaging module, the second infrared imaging module, the color imaging module and the proximity sensor can be controlled by the power-on and power-off control circuit 10, so that the working stability of the depth camera can be improved.

Fig. 2 is a schematic diagram of a power-on/power-off control circuit according to an embodiment of the present utility model, and for convenience of explanation, only a portion related to the embodiment is shown.

The power-on/off control circuit 10 is connected to the power interface 20 and the power management circuit 30, and the power-on/off control circuit 10 includes a voltage monitoring circuit 101, a power-on/off circuit 102, and a power-on timing control circuit 103. The input end of the voltage monitoring circuit 101 is connected with the power interface 20, the output end is connected with the power-on and discharging circuit 102, and the voltage monitoring circuit 101 is used for detecting the output voltage of the power interface 20 so as to judge power-on and power-off, and when detecting that the power supply 200 is powered on, the voltage monitoring circuit 101 outputs a power-on signal to the power-on and discharging circuit 102; when detecting that the power supply 200 is powered down, the voltage monitoring circuit 101 outputs a discharge signal to the power-up and discharge circuit 102. The output end of the power-on and discharging circuit 102 is connected with the power-on time sequence control circuit 103, the power-on and discharging circuit 102 is used for supplying power to the power-on time sequence control circuit 103 when receiving a power-on signal, and discharging the power-on time sequence control circuit 103 when receiving a discharging signal. The power-on timing control circuit 103 is connected to the power management circuit 30, and is configured to output a power-on enable signal to the power management circuit 30 after the power-on and discharging circuit 102 supplies power for a preset period of time, where the power-on enable signal is used to enable the power management circuit 30 to output a power supply signal.

The power-on of the power interface 20 means that the power interface 20 starts to output electric energy or the power supply voltage of the power interface 20 is greater than or equal to a voltage threshold, for example, the power supply 200 is connected to the power interface 20, and the power-off of the power interface 20 means that when the power interface 20 stops outputting electric energy or the power supply voltage of the power interface 20 is less than the voltage threshold, for example, the power supply 200 is disconnected from the power interface 20. The power management circuit 30 may be a circuit or chip.

The power-on and power-off control circuit 10 monitors the power interface 20 through the voltage monitoring circuit 101, when the power interface 20 is powered on, the power-on and power-off control circuit 103 is powered on through the power-on and power-off circuit 102, and when the power is supplied for a preset period of time, a power-on enabling signal is provided for the power management circuit 30 through the power-on time sequence control circuit 103, the rising edge is relatively rapid, and therefore the accuracy and stability of the power-on time sequence are guaranteed; when the power supply 200 is powered down, the power-on and discharging circuit 102 discharges the power-on time sequence control circuit 103, so that the rising edge is also relatively quick, an accurate and stable power-on enabling signal can be provided when the power is next powered up, and the cost of the power-on and power-off control circuit 10 is relatively low.

In one embodiment, as shown in fig. 3, the voltage monitoring circuit 101 includes a first capacitor C1, a diode D1, and a first resistor R1; the first end of the first capacitor C1 and the cathode of the diode D1 are commonly connected to the power supply 200, and the second end of the first capacitor C1 is grounded; the anode of the diode D1, the first terminal of the first resistor R1, and the controlled terminal of the power-on and discharge circuit 102 are commonly connected, and the second terminal of the first resistor R1 is grounded.

The diode D1 may be a voltage-stabilizing diode, the reverse breakdown voltage of the diode D1 may be the rated voltage of the power supply 200, when the power interface 20 is powered on and the power supply voltage reaches the rated voltage, the diode D1 is broken down, and the voltage monitoring circuit 101 may output a high-level signal (i.e. a power-on signal) to the controlled end of the power-on and power-off circuit 102. When the power supply voltage of the power interface 20 drops below the rated voltage, for example, when the power interface 20 is powered down, the diode D1 is out of the breakdown state, and the voltage monitoring circuit 101 outputs a low level signal (i.e., a discharge signal) to the controlled end of the power-up and discharge circuit 102. In other embodiments, the power-on signal may be a low-level signal, and the discharge signal may be a high-level signal, which may be specifically designed according to the requirements of the power-on and discharge circuit 102. The first capacitor C1 is used for filtering, noise reduction and voltage stabilization of the voltage output by the power interface 20.

In an embodiment, the voltage monitoring circuit 101 further includes a sixth resistor R6, where the sixth resistor R6 is connected in series between the anode of the diode D1 and the controlled terminal of the power-up and discharge circuit 102, for limiting the current transmitted to the controlled terminal of the power-up and discharge circuit 102 to protect the power-up and discharge circuit 102.

In an embodiment, as shown in fig. 3, the power-on and discharging circuit 102 includes a power-on circuit 1021 and a discharging circuit 1022, an input end of the power-on circuit 1021 is connected to the power interface 20, a controlled end of the power-on circuit 1021 is connected to the voltage monitoring circuit 101, a controlled end of the discharging circuit 1022 is connected to the power-on circuit 1021, an input end of the discharging circuit 1022 and the power-on timing control circuit 103 are commonly connected to an output end of the power-on circuit 1021, and an output end of the discharging circuit 1022 is grounded. When the power-on circuit 1021 receives the power-on signal, the power-on circuit 1021 may supply power to the power-on timing control circuit 103 based on the power supplied by the power interface 20, and when the power-on circuit 1021 receives the discharge signal, stop supplying power to the power-on timing control circuit 103 and control the discharge circuit 1022 to discharge the power-on timing control circuit 103.

In one embodiment, the power-up circuit 1021 includes a first switch Q1, a second switch Q2, and a second resistor R2. The first conducting end of the first switch Q1 is an input end of the power-on circuit 1021, the second conducting end of the first switch Q1 is an output end of the power-on circuit 1021, the first end of the second resistor R2 and the first conducting end of the first switch Q1 are commonly connected to the power interface 20, the second end of the second resistor R2, the controlled end of the first switch Q1 and the first conducting end of the second switch Q2 are commonly connected, the second conducting end of the second switch Q2 is grounded, and the controlled end of the second switch Q2 is connected to the voltage monitoring circuit 101 to receive the power-on signal.

In one embodiment, the discharge circuit 1022 includes a third switch Q3 and a third resistor R3. The first end of the third resistor R3 and the power-on time sequence control circuit 103 are commonly connected to the second conducting end of the first switch Q1, the second end of the third resistor R3 is connected to the first conducting end of the third switch Q3, the second conducting end of the third switch Q3 is grounded, and the controlled end of the third switch Q3 is connected to the controlled end of the first switch Q1.

The first switch Q1 is configured such that the first switch Q1 is turned on when the controlled terminal is at a low level, and the first switch Q1 is turned off when the controlled terminal is at a high level. The second switch Q2 and the third switch Q3 are configured to be turned on when the controlled terminal is at a high level and turned off when the controlled terminal is at a low level. When the voltage monitoring circuit 101 provides a high-level power-up signal for the controlled end of the second switch Q2, the second switch Q2 is turned on, and then the controlled end of the first switch Q1 is grounded, so that the first switch Q1 is turned on to further supply power to the power-up timing control circuit 103, and the controlled end of the third switch Q3 is grounded, and the third switch Q3 is turned off and does not discharge the power-up timing control circuit 103. When the voltage monitoring circuit 101 provides a low-level discharge signal for the controlled end of the second switch Q2, the second switch Q2 is turned off, the controlled end of the first switch Q1 is at a high level due to the presence of the second resistor R2, the first switch Q1 is turned off, the controlled end of the third switch Q3 is at a high level, and the third switch Q3 is turned on, so that the output end of the power-on and discharge circuit 102 is grounded, and the power-on time sequence control circuit 103 starts to discharge to control the discharge circuit 1022.

The third switch Q3 can quickly reduce the voltage at the output end of the power-on and discharging circuit 102 when the power supply 200 is powered down, and stop supplying power to the power-on time sequence control circuit 103, so as to achieve the effect of quickly closing the power-on time sequence control circuit 103 and discharging the power-on time sequence control circuit 103, so that an accurate power-on signal can be provided when the power is again powered on in a short time. The discharging speed of the power-on time sequence control circuit 103 is determined by the resistance value of the third resistor R3, the discharging speed of the power-on time sequence control circuit 103 is lower as the resistance value of the third resistor R3 is larger, and the discharging speed of the power-on time sequence control circuit 103 is higher as the resistance value of the third resistor R3 is smaller.

The first switch Q1 may be a PMOS transistor, and the second switch Q2 and the third switch Q3 may be NMOS transistors. The source electrode of the PMOS tube is a first conduction end, the drain electrode of the PMOS tube is a second conduction end, and the grid electrode of the PMOS tube is a controlled end. The drain electrode of the NMOS tube is a first conduction end, the source electrode of the NMOS tube is a second conduction end, and the grid electrode of the NMOS tube is a controlled end. In other embodiments, the first switch Q1 may be a P-type transistor, and the second switch Q2 and the third switch Q3 may be N-type transistors.

In one embodiment, as shown in fig. 3, the power-on timing control circuit 103 includes a fourth switch Q4, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2. The first end of the second capacitor C2 and the first end of the fifth resistor R5 are connected to the output end of the power-on and power-off circuit 102, the second end of the second capacitor C2, the first end of the fourth resistor R4 and the controlled end of the fourth switch Q4 are commonly connected, the second end of the fourth resistor R4 is grounded, the second end of the fifth resistor R5 and the first conductive end of the fourth switch Q4 are commonly connected to the enable end of the power management circuit 30, and the second conductive end of the fourth switch Q4 is grounded.

The fourth switch Q4 is configured to be turned on when the controlled terminal is at a high level and turned off when the controlled terminal is at a low level. For example, the fourth switch Q4 may be an N MOS transistor, the first conducting end of the fourth switch Q4 corresponds to the drain electrode of the N MOS transistor, the second conducting end of the fourth switch Q4 corresponds to the source electrode of the N MOS transistor, and the controlled end of the fourth switch Q4 corresponds to the gate electrode of the NMOS transistor. When the power-on and discharging circuit 102 supplies power to the power-on timing control circuit 103, the power-on and discharging circuit 102 charges the second capacitor C2 until the voltage on the second capacitor C2 reaches the turn-on threshold of the fourth switch Q4, so that the fourth switch Q4 is turned on, and outputs a power-on enable signal to the power management circuit 30. Compared with the signal of the voltage step-by-step change provided by the conventional RC circuit, the fourth switch Q4 can shape the power-on enabling signal after the delay of the second capacitor C2, so that the power-on time sequence control circuit 103 provides more accurate and reliable power-on time sequence.

In one embodiment, the power-on/power-off control circuit 10 includes a first power-on timing control circuit 1031, a second power-on timing control circuit 1032, and a third power-on timing control circuit 1033, as shown in fig. 4. The first power-up timing control circuit 1031, the second power-up timing control circuit 1032 and the third power-up timing control circuit 1033 are connected in parallel between the power-up and discharging circuit 102 and the power management circuit 30, and the preset durations corresponding to the first power-up timing control circuit 1031, the second power-up timing control circuit 1032 and the third power-up timing control circuit 1033 are different, so that the power management circuit 30 can supply power to the power utilization modules 40 according to different power supply timings.

The power-on and discharging circuit 102 may supply power to the first power-on timing control circuit 1031, the second power-on timing control circuit 1032 and the third power-on timing control circuit 1033 at the same time, but since the preset durations corresponding to the power-on timing control circuits are different, the times of outputting the power-on enable signals by the power-on timing control circuits are different, the power management circuit 30 may determine the power supply timing according to the received power-on enable signals, and supply power to the power-on modules 40 according to the power supply timing.

In one embodiment, as shown in fig. 4, the parameters of the fourth resistors R9 to R11 in the power-on timing control circuits are the same or different, and the parameters of the second capacitors C3 to C5 in the power-on timing control circuits are different. By controlling the parameters of the second capacitor and the fourth resistor according to the power supply timing, the sequence of the power supply enable signals output by the power supply timing control circuits can be controlled, and the power management circuit 30 can determine the power supply timing according to the sequence of the power supply enable signals received and supply power to the power utilization modules 40 according to the power supply timing. The larger the parameters of the second capacitor and the fourth resistor are, the longer the preset time length corresponding to the power-on time sequence control circuit is.

In the circuit of fig. 4, the capacitance of the capacitor C3 is smaller than the capacitance of the capacitor C4, and the capacitance of the capacitor C4 is smaller than the capacitance of the capacitor C5. As shown in fig. 5, a signal V1 is a voltage at an input terminal of the voltage monitoring circuit 101, and a signal V2, a signal V3 and a signal V4 are voltages at output terminals of the first power-up timing control circuit 1031, the second power-up timing control circuit 1032 and the third power-up timing control circuit 1033, respectively. After the input terminal of the voltage monitoring circuit 101 is powered on and a certain delay time, the signal V2, the signal V3 and the signal V4 sequentially and rapidly change to high level (i.e. each power-on time sequence control circuit outputs a corresponding power-on enabling signal respectively), and have accurate and stable rising edges, and when the power management circuit 30 receives the high level signal V2, the signal V3 and the signal V4, power supply signals are provided correspondingly respectively. As shown in fig. 6, when the power supply voltage is smaller than the rated voltage, that is, the power interface 20 is powered down, the voltage monitoring circuit 101 controls the power-on and power-off circuit 102 to discharge each power-on time sequence control circuit, and the signal V2, the signal V3 and the signal V4 are pulled down to low level rapidly, that is, the power-on enable signal is stopped to be output, so that the control is accurate.

The one power-on time sequence control circuit 103 shown in fig. 3 or the three power-on time sequence control circuits 103 shown in fig. 4 are only two examples, the number of the power-on time sequence control circuits 103 can be reasonably set according to the requirements of different power utilization modules 40 or multiple power utilization modules 40, for example, the number of the power-on time sequence control circuits 103 can be two, four, five, six or more, and the number is not limited.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present utility model. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.

Claims (10)

1. The power-on and power-off control circuit is characterized by being connected with a power interface and a power management circuit, and comprises a voltage monitoring circuit, a power-on and discharging circuit and a power-on time sequence control circuit;

the input end of the voltage monitoring circuit is connected with the power interface, and the output end of the voltage monitoring circuit is connected with the power-on and discharging circuit and is used for respectively outputting a power-on signal and a discharging signal to the power-on and discharging circuit when the power-on and power-off of the power interface are detected;

the output end of the power-on and discharge circuit is connected with the power-on time sequence control circuit and is used for supplying power to the power-on time sequence control circuit when receiving the power-on signal and discharging the power-on time sequence control circuit when receiving the discharge signal;

the power-on time sequence control circuit is connected with the power management circuit and is used for outputting a power-on enabling signal to the power management circuit after the power-on and discharging circuit supplies power for a preset time period so as to enable the power management circuit to supply power.

2. The power up and down control circuit of claim 1, wherein the voltage monitoring circuit comprises a first capacitor, a diode, and a first resistor;

the first end of the first capacitor and the cathode of the diode are connected with the power interface in a sharing way, the second end of the first capacitor is grounded, the anode of the diode and the first end of the first resistor are connected with the controlled end of the power-on and discharging circuit in a sharing way, and the second end of the first resistor is grounded.

3. The power-on and power-off control circuit according to claim 1, wherein the power-on and power-off control circuit comprises a power-on circuit and a power-off circuit, an input end of the power-on circuit is connected with the power interface, a controlled end of the power-on circuit is connected with the voltage monitoring circuit, a controlled end of the power-off circuit is connected with the power-on circuit, an input end of the power-off circuit and the power-on time sequence control circuit are connected with an output end of the power-on circuit in a common mode, and an output end of the power-off circuit is grounded.

4. The power-on and power-off control circuit of claim 3, wherein the power-on circuit comprises a first switch, a second switch, and a second resistor; the first end of the second resistor and the first conduction end of the first switch are connected to the power interface in a sharing mode, the second end of the second resistor, the controlled end of the first switch and the first conduction end of the second switch are connected in a sharing mode, the second conduction end of the second switch is grounded, and the controlled end of the second switch is connected with the voltage monitoring circuit to receive the power-on signal.

5. The power up and down control circuit of claim 4, wherein the discharge circuit comprises a third switch and a third resistor; the first end of the third resistor is connected with the second conducting end of the first switch, the second end of the third resistor is connected with the first conducting end of the third switch, the second conducting end of the third switch is grounded, and the controlled end of the third switch, the second end of the second resistor, the controlled end of the first switch and the first conducting end of the second switch are commonly connected.

6. The power up and down control circuit of claim 5, wherein the first switch is configured to be turned on when the controlled terminal is low and turned off when the controlled terminal is high; the second switch and the third switch are configured to be turned off when the controlled terminal is at a low level and turned on when the controlled terminal is at a high level.

7. The power-on/power-off control circuit according to any one of claims 1 to 6, wherein the power-on timing control circuit includes a fourth switch, a fourth resistor, a fifth resistor, and a second capacitor; the first end of the second capacitor and the first end of the fifth resistor are connected to the output end of the power-on and discharging circuit, the second end of the second capacitor, the first end of the fourth resistor and the controlled end of the fourth switch are commonly connected, the second end of the fourth resistor is grounded, the second end of the fifth resistor, the first conducting end of the fourth switch and the enabling end of the power management circuit are commonly connected, and the second conducting end of the fourth switch is grounded.

8. The power-on and power-off control circuit according to claim 7, wherein the power-on time sequence control circuits are plural, the power-on time sequence control circuits are connected in parallel between the power-on and power-off circuit and the power management circuit, and the preset time durations corresponding to the power-on time sequence control circuits are different, so that the power management circuit can power up the power-on modules according to the power-on time sequences.

9. The power up and down control circuit of claim 8, wherein parameters of said second capacitors in each of said power up timing control circuits are different.

10. An electronic device, comprising:

a power interface;

the power-on/off control circuit according to any one of claims 1-9, being connected to the power interface, for outputting a power-on enable signal when the power interface is powered on;

the power management circuit is connected with the power interface and the power-on time sequence control circuit and is used for outputting a power supply signal when receiving the power-on enabling signal;

and the power utilization module is connected with the output end of the power management circuit.