CN213365379U - Server mainboard and one-way server - Google Patents
Server mainboard and one-way server Download PDFInfo
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- CN213365379U CN213365379U CN202022754234.9U CN202022754234U CN213365379U CN 213365379 U CN213365379 U CN 213365379U CN 202022754234 U CN202022754234 U CN 202022754234U CN 213365379 U CN213365379 U CN 213365379U
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Abstract
The utility model provides a server mainboard. The server mainboard is provided with a CPU chip of a processor and a BMC chip of a substrate management controller, wherein the BMC chip is used for controlling the CPU chip, and the BMC chip is connected with the CPU chip through an LPC bus so as to transmit the starting operation state information of the CPU chip; the BMC chip is connected with the CPU chip through a USB bus so as to transmit control information of the remote management platform; the BMC chip is connected with the CPU chip through an SPI bus so as to realize BIOS firmware upgrading of the CPU chip. The utility model discloses a server mainboard can realize CPU's effective control.
Description
Technical Field
The utility model relates to a computer technology field especially relates to a server mainboard and one way server.
Background
The mainboard is the core of the server, and the performance of the mainboard directly determines the computing power of the server, so that it is important to select a CPU with excellent performance for the mainboard. The sea light CPU has wide application in the server mainboard.
With the technical development of the CPU chip design, more and more IO and the like are integrated on a single CPU chip, and the integration level of the server motherboard is higher and higher. And therefore state control of the CPU is also increasingly important. In order to improve the performance of the server motherboard, it is necessary to perform various effective controls on the operating state of the CPU chip.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a server mainboard and one way server realizes CPU's effective control through the multibus interconnection between BMC chip and the CPU chip.
In a first aspect, the present invention provides a server motherboard, the server motherboard is provided with a CPU chip and a BMC chip for controlling the CPU chip, wherein,
the BMC chip is connected with the CPU chip through an LPC bus so as to transmit the starting operation state information of the CPU chip;
the BMC chip is connected with the CPU chip through a USB bus so as to transmit control information of a remote management platform;
the BMC chip is connected with the CPU chip through an SPI bus so as to upgrade BIOS firmware of the CPU chip.
Optionally, the BMC chip is connected to a gigabit PHY chip, which is connected to a gigabit RJ45 interface for connecting a remote management platform through the gigabit RJ45 interface.
Optionally, an adjustable power module is arranged on the server motherboard,
the CPU chip is connected with the adjustable power supply module and is used for adjusting the power supply voltage and current of the adjustable power supply module in real time;
the BMC chip is connected with the adjustable power supply module and is used for monitoring the running state of the adjustable power supply module.
Optionally, a power control module is arranged on the server motherboard and is used for controlling the adjustable power module according to the instruction of the CPU chip.
Optionally, the processor chip has a plurality of sets of 16-way high-speed interfaces, wherein a set of 16-way high-speed interfaces is configured as a composite interface supporting multiple transport protocols.
Optionally, the high-speed interface of one of the 16-way sets is configured as a composite interface as follows:
the [0:1] lane is configured to support a first subinterface of SATA 2x and PCIe x 2;
[2] the lane is configured to support a second subinterface of SATA 1x and PCIe x 1;
[3] the lane is configured to support a third subinterface of SATA 1x and PCIe x 1;
the [4:7] lane is configured to support a fourth subinterface for PCIe x4, SATA 4x, and XGBE 4 x;
the [8:11] lane is configured to support the fifth subinterface of PCIe x 4;
the [12:15] lane is configured to support the sixth subinterface of PCIe x 4.
Optionally, the first sub-interface is connected to an output of a first multiplexing selector, a first input of the first multiplexing selector is connected to a first SATA connector and a second SATA connector, and a second input of the first multiplexing selector is connected to a first PCIe x16 slot;
the second sub-interface is connected to an output of a second mux selector, a first input of the second mux selector is connected to a third SATA connector, a second input of the second mux selector is connected to the first PCIe x16 slot;
the third sub-interface is connected to an output end of a third multiplexing selector, a first input end of the third multiplexing selector is connected to a fourth SATA connector, a second input end of the third multiplexing selector is connected to an output end of a fourth multiplexing selector, a first input end of the fourth multiplexing selector is connected to the first PCIe x16 slot, and a second input end of the fourth multiplexing selector is connected to the BMC chip;
the fourth sub-interface is connected to the first PCIe x16 slot;
the fifth sub-interface is connected to an M.2 connector;
the sixth sub-interface is connected to a gigabit network chip.
Optionally, the other high-speed interfaces except the high-speed interface configured as the composite interface are configured as interfaces supporting PCIe x16, and are respectively connected to PCIe x16 slots.
Optionally, the CPU chip further includes a plurality of memory channels, and each memory channel is connected to 2 DIMM slots.
In a second aspect, the present invention provides a one-way server, which comprises the above server motherboard.
The utility model provides a server mainboard and one-way server, through LPC bus, USB bus and SPI bus interconnection between BMC chip and the CPU chip, the LPC bus is used for conveying CPU's start-up running state information, and the USB bus is used for conveying remote management platform's control information, and the SPI bus is used for realizing the BIOS firmware upgrading of CPU chip. Through multi-bus interconnection, the effective control of the CPU is realized.
Drawings
Fig. 1 is a schematic diagram of a connection relationship between partial interfaces of a CPU on a server motherboard according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a connection relationship between partial interfaces of a CPU on a server motherboard according to an embodiment of the present invention;
fig. 3 is a schematic view of a connection relationship between a CPU and a BMC on a server motherboard according to an embodiment of the present invention;
fig. 4 is a schematic diagram of an overall structure of a server motherboard according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
An embodiment of the utility model provides a server motherboard is equipped with treater CPU chip and base plate Management Controller (BMC) chip on the server motherboard, and the CPU chip adopts Socket mounting means to install on the server motherboard.
Taking the marine light 5100CPU as an example, as shown in fig. 1, the CPU chip has 8 groups of high-speed interfaces with 16 channels, which are denoted as G0-3 and P0-3. Wherein the G0-3 interface is configured as a PCIe interface, and can only be used as PCIe on the server motherboard of this embodiment.
The P0-3 interface is a configurable interface, besides PCIe function, part of the path can be configured as SATA interface (such as [0:8] path), XGBE network interface (such as [4:7] path), PCIe adapter card needing to extrapolate corresponding function: PCIe gold finger directly connects SATA connector adapter card. Or the PCIe golden finger is connected with a network PHY chip, and is connected with a network RJ45 or a riser card of an SFP + interface through the PHY chip. Or PCIe gold finger directly connects the adapter card of the SFP + interface.
The P0 interface is used separately on the motherboard design, and is configured as a composite interface of a plurality of different transmission protocols through BIOS.
Specifically, the high-speed interface P0 is configured as defined below:
p0[0:1] is configured to support a first sub-interface of SATA 2x and PCIe x2, the first sub-interface being connected to an output of a first MUX selector 1, a first input of the first MUX selector 1 being connected to a first SATA connector SATA _ a and a second SATA connector SATA _ B, a second input of the first MUX selector 1 being connected to a first PCIe x16 slot PCIe x16 SlotA. P0[0:1] is switchably connected to SATA connectors (SATA _ A, SATA _ B) through MUX1(CPU GPIO control switch channel), and also can be switchably connected to PCIe x16 Slot A to be used as a PCIe x2 interface, and is used as a PCIe x8 interface together with other P0 channels.
P0[2] is configured as a second sub-interface supporting SATA 1x and PCIe x1, the second sub-interface being connected to an output of a second MUX selector 2, a first input of the second MUX selector 2 being connected to a third SATA connector SATA _ C, a second input of the second MUX selector MUX2 being connected to a first PCIe x16 slot PCIe x16 SlotA. P0[2] can be switchably connected to SATA connector (SATA _ C) through MUX2, and also can be switchably connected to PCIe x16 Slot A to be used as a PCIe x1 interface, and is combined with other P0 channels to be used as a PCIe x8 interface.
P0[3] is configured as a third sub-interface supporting SATA 1x and PCIe x1, the third sub-interface being connected to an output of a third MUX3, a first input of the third MUX3 being connected to a fourth SATA connector SATA _ D, a second input of the third MUX3 being connected to an output of a fourth MUX4, a first input of the fourth MUX4 being connected to a first PCIe x16 slot PCIe x16 SlotA, a second input of the fourth MUX4 being connected to a BMC chip. P0[3] is switchable to SATA connector (SATA _ D) and also to BMC through MUX3 as a PCIe x1 interface connection BMC. Or switching to the PCIe x16 Slot A to be used as a PCIe x1 interface, and combining with other P0 paths to be used as a PCIe x8 interface.
P0[4:7] is configured to support a fourth subinterface of PCIe x4, SATA 4x and XGBE 4x, which is connected to the first PCIe x16 slot. P0[4:7] is directly connected to PCIe x16 Slot A and can be configured as PCIe interface, SATA interface, XGBE network interface. If configured as PCIe, it is combined with other P0 paths and used as a PCIe x8 interface. When the PCIe adapter card is configured as a SATA or XGBE network interface, a PCIe adapter card with a corresponding function needs to be externally inserted on a PCIe x16 Slot A.
P0[8:11] is configured to support a fifth subinterface of PCIe x4, which connects to the M.2 connector, supporting M.2 storage disks.
P0[12:15] is configured to support a sixth subinterface of PCIe x4 connected to a gigabit network chip, such as an I350 AM2 network chip, supporting a 2 gigabit RJ45 interface. The BMC is also connected to the I350 AM2 through the NCSI, and the gigabit network of the CPU is shared, so that the management BMC can be accessed through the RJ45 connected to the I350 AM 2.
The 3 PCIe slots corresponding to the high-speed interface P1-3 support various expansion cards and can be configured as PCIe, SATA and XGBE network interfaces. Configured as a PCIe function, is used as a standard PCIe slot. When part of the path is configured as a SATA or XGBE network interface, a PCIe adapter card with corresponding functions needs to be externally inserted on a PCIe X16 Slot A.
In summary, the server motherboard is designed with the following interfaces:
4 SATA connectors for connecting standard SATA disk;
1 M.2 connector for connecting M.2 memory disc;
2 kilomega RJ45 interfaces supporting 2-channel kilomega electric port networks;
7 PCIe 4.0 slots: standard PCI card can be inserted, and U.2NVME disk can also be inserted.
In addition, as shown in fig. 2, the CPU chip includes 8 memory channels, each of which is connected to 2 DDR4 DIMM slots, and can plug up to 16 DDR4 DIMM memory banks. The CPU chip is connected with 5 USB interfaces, and 5 USB interfaces support the USB3.0 standard, wherein the USB CON A connector can connect the USB port to the panel interface of the front panel through a 20pin cable, which is convenient for users to use. In addition, the system also comprises a Type-C connector interface CON C. The CPU is also connected with 1 JTAG interface to support the real-time debugging of the CPU and position bug.
The BMC chip on the mainboard is responsible for system management and can control the CPU chip, and as shown in FIG. 3, the BMC chip and the CPU chip are interconnected through interfaces such as PCIe, LPC, USB, SPI and the like. The BMC chip is externally connected with a gigabit PHY chip, for example, RTL8211F, the gigabit PHY chip is externally connected with 1 gigabit RJ45 interface to serve as a remote management interface, and a remote management platform realizes management of a main board of a sunlight 5100CPU server through a gigabit network.
The specific interconnection relationship between BMC and CPU is as follows:
interconnection of SPI buses: the CPU BIOS may be toggled to BMC, or to the CPU via SPI SW (signal switch). When the BIOS firmware is upgraded, the BIOS firmware is switched to be connected to the BMC. And switching to the CPU when the CPU server is normally started up and operated. Therefore, CPU BIOS firmware can be upgraded through the remote management platform, namely the remote management platform sends a new BIOS to the BMC through a gigabit RJ45 interface of the BMC, the BMC writes a BIOS chip again, then the CPU is switched to through the SPI SW, and the CPU is started to use the new BIOS firmware.
Interconnection of LPC bus: the LPC bus interconnected between the BMC and the CPU is used for transmitting the starting operation state information of the CPU, and after the information is transmitted to the BMC, the information is displayed through an LED PORT80 connected with the BMC. And is also connected to the CPLD to inform the CLPD of the current starting running state of the CPU.
USB bus interconnection: the USB bus interconnected between the BMC and the CPU is used to implement a remote KVM (keyboard, video, mouse), that is, the remote management platform is connected to the BMC through a BMC gigabit RJ45 network port, and then connected to the CPU through a USB port of the BMC.
In addition, the BMC chip is connected with 1 COM interface and used for being externally connected with serial equipment. The BMC chip is connected with 1 VGA interface, and is used as a display interface of the mainboard and externally connected with display equipment. The BMC chip is connected with an LED display interface LED port80 to display the state of the CPU. The BMC chip is connected with a FAN interface FAN CON [1:8] to control the FAN in the server chassis. The BMC chip is connected with the SD card interface and stores server log information. The BMC chip is connected with the BMC FW Flash, and the BMC firmware BMC FW of the BMC system is stored in the BMC FW Flash.
Further, as shown in fig. 3, a dedicated power module is disposed on the server motherboard of this embodiment, and the power module is used to supply power to the CPU, and the BMC monitors the power module at the same time.
The power supply module comprises a power supply module and a power supply control module.
The power supply module comprises fixed power supply and CPU controllable power supply (adjustable power supply module).
The fixed power supply is the power supply of a device with an unadjustable power supply voltage, namely, only one voltage value exists after the enable is enabled. The part comprises standby dormant power supply, IO power supply and memory power supply. The CPU controllable power supply is realized by using a serial control bus power supply Voltage adjustable device (VR device) supporting the CPU integration, the CPU is connected with the VR device, and the CPU adjusts the power supply Voltage and current of the VR device in real time according to the running condition of the CPU, so that the environment is protected, and the energy is saved.
The power supply control module is realized by adopting a CPLD, and performs power-on and power-off control on the adjustable power supply module according to the CPU startup key and the indication input signal of the logic state (S3, S5), namely, the power can be supplied to the CPU by the corresponding VR device, and the power-on and power-off time sequence control is realized according to the requirement of the CPU.
In addition, the output voltage of a plurality of power supply devices is monitored through the ADC module integrated with the BMC, the power supply operation condition is reported, and problem location and maintenance are facilitated.
By combining the above fig. 1 to fig. 3, a schematic diagram of the overall structure of the server motherboard shown in fig. 4 can be obtained.
The embodiment of the utility model provides a still provide a single server, single server includes above-mentioned server mainboard.
The embodiment of the utility model provides a server mainboard and one-way server, through LPC bus, USB bus and SPI bus interconnection between BMC chip and the CPU chip, the LPC bus is used for conveying CPU's start-up running state information, and the USB bus is used for conveying remote management platform's control information, and the SPI bus is used for realizing the BIOS firmware upgrade of CPU chip. Through multi-bus interconnection, the effective control of the CPU is realized.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A server mainboard is characterized in that a processor CPU chip and a baseboard management controller BMC chip are arranged on the server mainboard, the BMC chip is used for controlling the CPU chip, wherein,
the BMC chip is connected with the CPU chip through an LPC bus so as to transmit the starting operation state information of the CPU chip;
the BMC chip is connected with the CPU chip through a USB bus so as to transmit control information of a remote management platform;
the BMC chip is connected with the CPU chip through an SPI bus so as to upgrade BIOS firmware of the CPU chip.
2. The server motherboard of claim 1 wherein the BMC chip is connected to a gigabit PHY chip that is connected to a gigabit RJ45 interface for connection to a remote management platform via the gigabit RJ45 interface.
3. The server motherboard of claim 1 wherein the server motherboard has an adjustable power module thereon,
the CPU chip is connected with the adjustable power supply module and is used for adjusting the power supply voltage and current of the adjustable power supply module in real time;
the BMC chip is connected with the adjustable power supply module and is used for monitoring the running state of the adjustable power supply module.
4. The server motherboard of claim 3, wherein the server motherboard is provided with a power control module for controlling the adjustable power module according to an instruction of the CPU chip.
5. The server motherboard of claim 1 wherein the processor chip has a plurality of sets of 16-lane high speed interfaces, wherein a set of 16-lane high speed interfaces is configured as a composite interface that supports multiple transport protocols.
6. The server motherboard of claim 5 wherein a set of 16-way high-speed interfaces are configured as a composite interface as follows:
the [0:1] lane is configured to support a first subinterface of SATA 2x and PCIe x 2;
[2] the lane is configured to support a second subinterface of SATA 1x and PCIe x 1;
[3] the lane is configured to support a third subinterface of SATA 1x and PCIe x 1;
the [4:7] lane is configured to support a fourth subinterface for PCIe x4, SATA 4x, and XGBE 4 x;
the [8:11] lane is configured to support the fifth subinterface of PCIe x 4;
the [12:15] lane is configured to support the sixth subinterface of PCIe x 4.
7. Server board as in claim 6,
the first sub-interface is connected to an output of a first multiplexing selector, a first input of the first multiplexing selector is connected to a first SATA connector and a second SATA connector, and a second input of the first multiplexing selector is connected to a first PCIe x16 slot;
the second sub-interface is connected to an output of a second mux selector, a first input of the second mux selector is connected to a third SATA connector, a second input of the second mux selector is connected to the first PCIe x16 slot;
the third sub-interface is connected to an output end of a third multiplexing selector, a first input end of the third multiplexing selector is connected to a fourth SATA connector, a second input end of the third multiplexing selector is connected to an output end of a fourth multiplexing selector, a first input end of the fourth multiplexing selector is connected to the first PCIe x16 slot, and a second input end of the fourth multiplexing selector is connected to the BMC chip;
the fourth sub-interface is connected to the first PCIe x16 slot;
the fifth sub-interface is connected to an M.2 connector;
the sixth sub-interface is connected to a gigabit network chip.
8. The server motherboard of claim 5 wherein the remaining high-speed interfaces other than the high-speed interface configured as a composite interface are configured to support PCIe x16 interfaces, respectively connected to PCIe x16 slots.
9. The server motherboard of claim 1 wherein the CPU chip further comprises a plurality of memory channels, each memory channel connected to 2 DIMM slots.
10. A one-way server, characterized in that it comprises a server motherboard according to any of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022754234.9U CN213365379U (en) | 2020-11-25 | 2020-11-25 | Server mainboard and one-way server |
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| CN202022754234.9U CN213365379U (en) | 2020-11-25 | 2020-11-25 | Server mainboard and one-way server |
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| CN213365379U true CN213365379U (en) | 2021-06-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114676091A (en) * | 2022-04-12 | 2022-06-28 | 北京百度网讯科技有限公司 | Safety management board, server board card assembly and server |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114676091A (en) * | 2022-04-12 | 2022-06-28 | 北京百度网讯科技有限公司 | Safety management board, server board card assembly and server |
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