CN212542410U - Fan-out type wafer level packaging structure - Google Patents
Fan-out type wafer level packaging structure Download PDFInfo
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- CN212542410U CN212542410U CN202021943526.0U CN202021943526U CN212542410U CN 212542410 U CN212542410 U CN 212542410U CN 202021943526 U CN202021943526 U CN 202021943526U CN 212542410 U CN212542410 U CN 212542410U
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The utility model provides a fan-out type wafer level packaging structure, this structure includes: the semiconductor chip array comprises more than two semiconductor chips with welding pads, wherein the semiconductor chips are arranged into a fan-out wafer array, and each semiconductor chip is provided with an initial position; the plastic packaging layer covers the surface of the semiconductor chip and among the semiconductor chips, each semiconductor chip has a respective offset position after plastic packaging, and the offset position has an offset distance relative to the initial position; the rewiring layer is formed on the semiconductor chips so as to realize interconnection among the semiconductor chips, and at least comprises a first rewiring layer which is formed on the surface of the semiconductor chips and is aligned and connected with the welding pads of the semiconductor chips; and the metal bump is formed on the rewiring layer. The fan-out wafer level packaging structure can realize effective alignment of the semiconductor chip and the rewiring layer, and improve the yield of wafer packaging.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor package, especially, relate to a fan-out type wafer level packaging structure.
Background
With the rapid development of the integrated circuit manufacturing industry, people have increasingly demanded the packaging technology of the integrated circuit, and the existing packaging technology includes Ball Grid Array (BGA), Chip Size Package (CSP), Wafer Level Package (WLP), three-dimensional package (3D), System In Package (SiP), and the like. Among them, Wafer Level Packaging (WLP) is increasingly being adopted by most semiconductor manufacturers for its excellent advantages, all or most of its process steps being performed on a silicon wafer having a pre-process completed, and finally the wafer being directly cut into individual devices. Wafer Level Packaging (WLP) has its unique advantages: firstly, the packaging processing efficiency is high, and a plurality of wafers can be processed simultaneously; secondly, the packaging method has the advantages of flip chip packaging, namely light, thin, short and small; compared with the previous process, only two processes of pin Rewiring (RDL) and bump manufacturing are added, and the rest processes are all traditional processes; and fourthly, the repeated tests in the traditional packaging are reduced. Therefore, various large IC packaging companies in the world invest in research, development and production of such WLPs.
The fan-out type wafer level package has a high degree of attention among manufacturers such as mobile device manufacturers due to its advantages such as miniaturization, low cost, and high integration. Fan-out wafer level packaging is currently best suited for the demanding mobile/wireless market and is also strongly attractive for other markets where high performance and small size are of concern.
The existing fan-out wafer level packaging process generally comprises the steps of firstly pasting a semiconductor chip on a bonding layer of a supporting substrate, then carrying out plastic packaging by adopting a plastic packaging material, wherein the plastic packaging material is heated to be in a liquid state in the plastic packaging process, and carrying out pressing in a high-temperature environment, the warping of a wafer, which is generally upward warping (as shown in figure 1), when the whole wafer is warped, a plurality of semiconductor chips on the wafer can drift towards different directions to different degrees, so that a bonding pad on the semiconductor chip can deviate from the original position on the wafer, when the whole wafer is warped upwards, the semiconductor chip positioned at the edge of the wafer and the semiconductor chip positioned in the middle of the wafer can drift, the offset of the semiconductor chip positioned at the edge is larger than that of the semiconductor chip positioned at the center, and when the semiconductor chip drifts upwards, the subsequent packaging process can be seriously examined, for example, when a redistribution layer (RDL) is formed subsequently, due to drift of a semiconductor chip, when a dielectric layer of the redistribution layer is formed by photolithography, a photolithography pattern cannot be aligned with a pad of the semiconductor chip precisely, and alignment accuracy of the whole redistribution layer is reduced, thereby affecting yield of wafer packaging.
SUMMERY OF THE UTILITY MODEL
In view of the above prior art's shortcoming, the utility model aims to provide a fan-out type wafer level packaging structure for the wafer takes place warpage and semiconductor chip and produces the drift after solving fan-out type wafer level packaging among the prior art and encapsulating semiconductor chip, has improved the degree of difficulty of follow-up packaging technology, thereby influences the problem of the yield etc. of wafer packaging.
To achieve the above and other related objects, the present invention provides a fan-out wafer level package structure, comprising:
the semiconductor chip structure comprises more than two semiconductor chips with welding pads, wherein the semiconductor chips are arranged into a fan-out wafer array, and each semiconductor chip is provided with an initial position;
the plastic package layer covers the surfaces of the semiconductor chips and among the semiconductor chips, each semiconductor chip is provided with a respective offset position after plastic package, and the offset position has an offset distance relative to the initial position;
the rewiring layer is formed on the semiconductor chips so as to realize interconnection among the semiconductor chips, and at least comprises a first rewiring layer which is formed on the surface of the semiconductor chips and is aligned and connected with the welding pads of the semiconductor chips;
and the metal bump is formed on the rewiring layer.
Optionally, the redistribution layer includes a patterned dielectric layer and a patterned metal routing layer.
Optionally, the material of the patterned dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the patterned metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the material of the molding layer includes one of polyimide, silicone, and epoxy resin.
As described above, the utility model discloses a fan-out type wafer level packaging structure, when forming the first layer rewiring layer, through the mode of drawing the unit, divide fan-out type wafer array into a plurality of etching units, carry out the etching windowing to every etching unit one by one, with the through-hole that forms naked semiconductor chip bonding pad, all readjust the photoetching exposure direction in the photoetching technology when etching the windowing at every turn, be equivalent to and once aim at the exposure and decompose into alignment exposure many times, alignment exposure direction is adjusted according to the skew distance and the skew direction of its semiconductor chip of etching unit that belongs to every alignment exposure, the alignment precision of the photoetching technology when forming the rewiring layer has effectively been improved, can effectively improve the alignment precision of the rewiring layer of follow-up formation on the basis of the photoetching alignment effect of this high accuracy, thereby effectively improve the yield of wafer encapsulation; the method can be realized only by arranging the light shielding structure on the photoetching photomask, and is simple and feasible and high in operability.
Drawings
Fig. 1 is a perspective view illustrating warpage and drift of a conventional fan-out wafer level package after a semiconductor chip is molded.
Fig. 2 to 17 are schematic cross-sectional structural diagrams of the steps of the packaging method of the fan-out wafer level package structure according to the present invention.
Description of the element reference numerals
100 wafer
200 semiconductor chip
201 pad
202 bonding layer
203 fan-out wafer array
204 semiconductor chip unit
205 plastic packaging layer
206 dielectric layer
207 dielectric layer etching unit
208 photoresist layer
209 photomask with shielding structure
210 through hole
211 patterned dielectric layer
212 patterned metal routing layer
213 first rewiring layer
214 second rewiring layer
215 rewiring layer
216 metal bump
217 supporting substrate
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 2 to 17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
As shown in fig. 1, in the conventional fan-out wafer level packaging process, after a semiconductor chip is subjected to plastic package, the whole wafer is warped, and the semiconductor chip is drifted towards various directions to different degrees, so that a bonding pad on the semiconductor chip is deviated from an original position on the wafer, which provides a severe test for a later stage process of the fan-out wafer level packaging, and leads to a reduction in the yield of wafer packaging.
The utility model discloses people find above-mentioned problem, based on this problem from each link detailed analysis of encapsulation various factors, synthesize the packaging method who provides a fan-out type wafer level packaging structure. The packaging method starts from the post-stage process after the semiconductor chip is subjected to plastic packaging, when a first-layer rewiring layer is formed, a fan-out type wafer array is divided into a plurality of etching units in a unit-scribing mode, each etching unit is subjected to etching windowing one by one to form a through hole exposing a welding pad of the semiconductor chip, the photoetching exposure direction in the photoetching process is readjusted when the etching windowing is carried out each time, namely, one-time alignment exposure is decomposed into multiple-time alignment exposure, the exposure direction is adjusted according to the offset distance and the offset direction of the semiconductor chip of the etching unit where the alignment exposure is located each time, the alignment precision of the photoetching process when the rewiring layer is formed is effectively improved, the alignment precision of the subsequently formed rewiring layer can be effectively improved on the basis of the high-precision photoetching effect, and the yield of wafer packaging is effectively improved; the method can be realized only by arranging the light shielding structure on the photoetching photomask, and is simple and feasible and high in operability.
As shown in fig. 2 to 17, the encapsulation method includes:
as shown in fig. 2 and fig. 3, step 1) is performed first to provide two or more semiconductor chips 200 having bonding pads 201.
The semiconductor chip 200 may be any conventional semiconductor chip suitable for packaging, may be an independent functional chip, such as a memory chip, a circuit chip, etc., or may be an integrated functional chip, such as an APU chip, a GPU chip, etc., without limitation. The material of the pad 201 in the semiconductor chip 200 includes metal aluminum, which is an aluminum pad. When the bonding pad 201 is manufactured, in order to improve the electrical property of the bonding pad and the adhesion property with the semiconductor chip 200, an adhesion layer may be further formed under the bonding pad 201, and an anti-reflection layer may be formed on the bonding pad 201.
As shown in fig. 2 and fig. 3, step 2) is then performed to adhere the semiconductor chips 200 to the adhesive layer 202, so as to form a fan-out wafer array 203, where the fan-out wafer array 203 is divided into two or more semiconductor chip units 204, and each of the semiconductor chips 200 has its own initial position.
It should be noted that, based on the requirements of packaging efficiency, packaging size, etc., a plurality of semiconductor chips 200 are generally bonded to the fan-out wafer array 203, and in most cases, more than two semiconductor chips 200 are bonded, and the more semiconductor chips 200 are bonded, the more the effect achieved by this embodiment is obvious. The number of pads 201 provided on the semiconductor chip 200 is not limited to 2 as shown in the figure, and the specific number is set according to the specific semiconductor chip 200.
As an example, the number of the semiconductor chips 200 in each of the semiconductor chip units 204 may be determined according to the maximum offset distance of the semiconductor chips 200 in the semiconductor chip units 204 after the subsequent semiconductor chips are molded. The number of the semiconductor chip units 204 divided by the fan-out wafer array 203 is two or more, that is, two or more, and the effect achieved by the present embodiment is more obvious as the number is larger, in the present embodiment, for convenience of understanding, the semiconductor chips 200 arranged in a row are one semiconductor chip unit 204, so the semiconductor chip unit 204 in the cross-sectional view can only display one semiconductor chip 200, and two semiconductor chip units 204 arranged in this way are illustrated as an example in the figure.
As shown in fig. 2, the semiconductor chip 200 is bonded only to the adhesive layer 202, forming the fan-out wafer array 203. The method is low in cost, but warpage and drift are easy to occur after subsequent plastic packaging. The adhesive layer 202 may be a material such as an adhesive tape, a UV adhesive formed by spin coating, or an epoxy resin, and in this embodiment, the adhesive layer 202 is a UV adhesive formed by spin coating, and the adhesion of the UV adhesive is reduced by ultraviolet light irradiation.
As shown in fig. 3, the adhesive layer 202 is illustratively bonded to a support substrate 217, and the fan-out wafer array 203 is formed through the support substrate 217. The supporting substrate 217 may be made of glass, ceramic, metal, polymer, or the like, in this embodiment, the supporting substrate 217 includes one of glass, transparent semiconductor material, and transparent polymer, so that the above-mentioned UV adhesive can be exposed from the back side of the supporting substrate 217, thereby greatly simplifying the subsequent stripping process.
When the semiconductor chip 200 is adhered to the adhesive layer 202, the side of the semiconductor chip 200 where the bonding pad 201 is formed is adhered to the adhesive layer, and then the semiconductor chip is inverted after the adhesive layer is removed and before a rewiring layer is formed, so that the rewiring layer is formed on the semiconductor chip.
As shown in fig. 4, step 3) is then performed to package the semiconductor chips 200 with a molding layer 205, each of the semiconductor chips 200 having a respective offset position having an offset distance from the initial position. During plastic packaging, the molding material is heated to a liquid state, and the bonding is performed in a high temperature environment, since all the semiconductor chips 200 are a wafer array formed by re-bonding, warpage is generated under the pressure, the semiconductor chips 200 will drift, that is, the offset position of the semiconductor chips 200 after the molding in the wafer array will generate an offset distance with respect to the position (initial position) of the semiconductor chips 200 in the wafer array, and since the positions of the semiconductor chips 200 in the wafer array are different, the offset directions and offset degrees of the semiconductor chips are also different, and accordingly, the bonding pads on the semiconductor chips will also offset.
As an example, the material of the molding layer 205 includes one of polyimide, silicone, and epoxy. Wherein, the molding layer 205 is formed with opaque material by adding additives.
As an example, the process for plastic packaging the semiconductor chip 200 includes: one of an injection molding process, a compression molding process, a printing process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process. In this embodiment, each semiconductor chip 200 is plastic-packaged by an injection molding process, and the plastic-packaging layer 205 is opaque silica gel.
As shown in fig. 5 to 13, step 4) is performed to remove the adhesive layer 202 (as shown in fig. 5) and form a redistribution layer 215 (as shown in fig. 13) on the semiconductor chips 200 to implement interconnection between the semiconductor chips 200; the redistribution layer 215 includes at least one first redistribution layer 213, and a method of forming the first redistribution layer 213 includes: forming a dielectric layer 206 on the semiconductor chip 200; taking the area corresponding to each semiconductor chip unit 204 as a dielectric layer etching unit 207, correspondingly dividing the dielectric layer 206 into more than two dielectric layer etching units 207, and etching all the dielectric layer etching units 207 one by adopting a photolithography process (as shown in fig. 8 to 10) to form through holes 210 exposing the pads 201 of each semiconductor chip 200 in the dielectric layer 206, wherein the photolithography exposure direction of the photolithography process is readjusted each time the dielectric layer etching unit 207 is etched; a patterned metal wiring layer 212 (shown in fig. 11) corresponding to the via hole 210 is formed in the via hole 210 and on the dielectric layer 206.
When the first rewiring layer 213 is formed, the fan-out wafer array 203 is divided into a plurality of exposure etching units in a scribing mode, each dielectric layer etching unit 207 unit is etched and windowed one by one to form a through hole exposing a semiconductor chip welding pad, the photoetching exposure direction in the photoetching process is readjusted when each time the window is etched, namely, one-time alignment exposure is decomposed into multiple-time alignment exposure, the exposure direction is adjusted according to the offset distance and the offset direction of the semiconductor chip of the etching unit where the alignment exposure is positioned, the alignment precision of the photoetching process when the rewiring layer is formed is effectively improved, and the alignment precision of the subsequently formed rewiring layer can be effectively improved on the basis of the high-precision photoetching alignment effect, so that the wafer packaging yield is effectively improved; the method can be realized only by arranging the light shielding structure on the photoetching photomask, and is simple and feasible and high in operability.
When the fan-out wafer array 203 is formed by the adhesive layer 202 and the support substrate 217, the support substrate 217 is removed simultaneously with the removal of the adhesive layer 202.
As shown in fig. 6 to 11, as an example, when the material of the dielectric layer 206 is selected to include one or a combination of two or more of epoxy resin, silicone, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, the method for forming the first redistribution layer 213 includes:
as shown in fig. 6, a dielectric layer 206 is formed on the semiconductor chip 200. The dielectric layer 206 may be formed by a chemical vapor deposition process or a physical vapor deposition process;
as shown in fig. 7, a photoresist layer 208 is then coated on the dielectric layer 206;
as shown in fig. 8, the photoresist layer 208 is exposed by using a mask 209 having a shielding structure, such that the photoresist layer 208 on the left dielectric layer etching unit 207 is exposed to form a corresponding etching window, and then the dielectric layer 206 is etched by using an etching process through the etching window to form a through hole 210 in the left dielectric layer etching unit 207, wherein the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the left semiconductor chip unit 204;
as shown in fig. 9, the relative direction between the mask 209 having the shielding structure and the dielectric layer etching unit 207 is adjusted, and then exposing the photoresist layer 208 by using a photomask 209 with a shielding structure, so that the photoresist layer 208 on the right dielectric layer etching unit 207 is exposed, a corresponding etching window is formed, then, the dielectric layer 206 is etched through the etching window by using an etching process to form a via hole 210 in the right dielectric layer etching unit 207, the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the right semiconductor chip unit 204, which is exemplified by two dielectric layer etching units 207 in this example, and actually there may be more than two dielectric layer etching units 207, and this step is continued until the dielectric layer 206 is completely patterned to form a patterned dielectric layer 211 (as shown in fig. 10);
as shown in fig. 11, a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or a chemical plating process is finally adopted to form a metal wiring layer in the through hole 210 and on the surface of the patterned dielectric layer 211, and the metal wiring layer is etched to form a patterned metal wiring layer 212. The material of the metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
As shown in fig. 11 to 14, as an example, when the material of the dielectric layer 206 is selected to include one or a combination of two or more of PI and PBO, the method for forming the first redistribution layer 213 includes:
as shown in fig. 12, a dielectric layer 206 is formed on the semiconductor chip 200;
as shown in fig. 13, a photolithography process is directly performed on the dielectric layer 206, specifically, a mask 209 having a shielding structure is used to expose the dielectric layer 206, so that the left dielectric layer etching unit 207 is exposed to form a through hole 210 in the left dielectric layer etching unit 207, and the through hole 210 exposes a pad 201 on the semiconductor chip 200 in the left semiconductor chip unit 204;
as shown in fig. 14, then, adjusting a relative direction between the mask 209 having the shielding structure and the dielectric layer etching unit 207, and then exposing the dielectric layer 206 by using the mask 209 having the shielding structure, so as to form a through hole 210 in the dielectric layer etching unit 207 on the right, where the through hole 210 exposes the pad 201 on the semiconductor chip 200 in the semiconductor chip unit 204 on the right, in this example, two dielectric layer etching units 207 are taken as an example for illustration, and actually there may be more than two dielectric layer etching units 207, and this step is continued until the dielectric layer 206 is completely patterned, so as to form a patterned dielectric layer 211 (as shown in fig. 10);
as shown in fig. 11, a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or a chemical plating process is finally adopted to form a metal wiring layer in the through hole 210 and on the surface of the patterned dielectric layer 211, and the metal wiring layer is etched to form a patterned metal wiring layer 212. The material of the metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
As shown in fig. 15 and 16, the redistribution layer 215 further includes at least one second redistribution layer 214 formed on the first redistribution layer 213, and the method of forming the second redistribution layer 214 includes: forming the dielectric layer 206 on the surface of the upper redistribution layer 213; etching the dielectric layer 206 by using a conventional photolithography process and an etching process to form a patterned dielectric layer 211 (as shown in fig. 15), so as to form a through hole exposing the upper patterned metal wiring layer 212 in the patterned dielectric layer 211; a patterned metal wiring layer 212 corresponding to the via hole is formed in the via hole and on the patterned dielectric layer 211 (as shown in fig. 16).
As shown in fig. 17, step 5) is finally performed to form a metal bump 216 on the redistribution layer 215.
By way of example, the metal bump 216 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball, or the metal bump 216 includes a metal pillar and a solder ball formed on the metal pillar, and preferably, the metal pillar is a copper pillar or a nickel pillar. In the present embodiment, the metal bump 216 is a gold-tin solder ball, and the manufacturing steps thereof include: firstly, forming a gold-tin layer on the surface of the rewiring layer 215, then refluxing the gold-tin layer into a spherical shape by adopting a high-temperature refluxing process, and cooling to form a gold-tin solder ball; or forming a gold-tin solder ball by adopting a ball planting process.
As shown in fig. 17, this embodiment further provides a fan-out wafer level package structure, which can be prepared by the method for preparing the fan-out wafer level package structure according to the above embodiment. For the beneficial effects that the fan-out wafer level package structure can achieve, please refer to the preparation method of the above embodiment, which is not described further below, and the package structure includes:
more than two semiconductor chips 200 with welding pads 201, wherein the semiconductor chips 200 are arranged into a fan-out type wafer array 203, and each semiconductor chip 200 has a respective initial position;
a plastic sealing layer 205 covering the surface of the semiconductor chip 200 and between the semiconductor chips 200, each semiconductor chip 200 having a respective offset position after plastic sealing, the offset position having an offset distance with respect to the initial position;
a redistribution layer 215 formed on the semiconductor chip 200 to realize interconnection between the semiconductor chips 200, wherein the redistribution layer 215 includes at least one first redistribution layer 213, and the first redistribution layer 213 is formed on the surface of the semiconductor chip 200 and connected to the pad 201 of the semiconductor chip 200 in alignment;
and a metal bump 216 formed on the redistribution layer 215.
By way of example, the redistribution layer 215 includes a patterned dielectric layer 211 and a patterned metal routing layer 212. Preferably, the material of the patterned dielectric layer 211 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the patterned metal wiring layer 212 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
As an example, the material of the molding layer 205 includes one of polyimide, silicone, and epoxy.
In summary, the present embodiment provides a fan-out wafer level package structure and a packaging method thereof, wherein when forming a first redistribution layer, dividing the fan-out wafer array into multiple etching units by scribing unit, etching each etching unit one by one to form via holes for exposing the bonding pads of the semiconductor chip, readjusting the lithography exposure direction in the lithography process when etching the window every time, which is equivalent to decomposing one-time alignment exposure into multiple-time alignment exposure, adjusting the exposure direction according to the offset distance and the offset direction of the semiconductor chip of the etching unit where the alignment exposure is located every time, effectively improving the alignment precision of the lithography process when forming the rewiring layer, based on the high-precision photoetching alignment effect, the alignment precision of a subsequently formed rewiring layer can be effectively improved, so that the yield of wafer packaging is effectively improved; the method can be realized only by arranging the light shielding structure on the photoetching photomask, and is simple and feasible and high in operability. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (4)
1. A fan-out wafer level package structure, comprising:
the semiconductor chip structure comprises more than two semiconductor chips with welding pads, wherein the semiconductor chips are arranged into a fan-out wafer array, and each semiconductor chip is provided with an initial position;
the plastic package layer covers the surfaces of the semiconductor chips and among the semiconductor chips, each semiconductor chip is provided with a respective offset position after plastic package, and the offset position has an offset distance relative to the initial position;
the rewiring layer is formed on the semiconductor chips so as to realize interconnection among the semiconductor chips, and at least comprises a first rewiring layer which is formed on the surface of the semiconductor chips and is aligned and connected with the welding pads of the semiconductor chips;
and the metal bump is formed on the rewiring layer.
2. The fan-out wafer level package structure of claim 1, wherein: the rewiring layer comprises a graphical dielectric layer and a graphical metal wiring layer.
3. The fan-out wafer level package structure of claim 2, wherein: the material of the graphical dielectric layer comprises one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass, and the material of the graphical metal wiring layer comprises one of copper, aluminum, nickel, gold, silver and titanium.
4. The fan-out wafer level package structure of claim 1, wherein: the plastic packaging layer is made of one of polyimide, silica gel and epoxy resin.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021943526.0U CN212542410U (en) | 2020-09-08 | 2020-09-08 | Fan-out type wafer level packaging structure |
| US17/207,368 US11380649B2 (en) | 2020-09-08 | 2021-03-19 | Fan-out wafer-level packaging structure and method packaging the same |
| US17/830,290 US11652085B2 (en) | 2020-09-08 | 2022-06-01 | Fan-out wafer-level packaging structure and method packaging the same |
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| CN202021943526.0U CN212542410U (en) | 2020-09-08 | 2020-09-08 | Fan-out type wafer level packaging structure |
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| CN114156188A (en) * | 2020-09-08 | 2022-03-08 | 盛合晶微半导体(江阴)有限公司 | Fan-out type wafer level packaging structure and packaging method |
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| CN114156188A (en) * | 2020-09-08 | 2022-03-08 | 盛合晶微半导体(江阴)有限公司 | Fan-out type wafer level packaging structure and packaging method |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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