CN212434213U - Pre-charging circuit of common-anode LED display screen driving chip - Google Patents
Pre-charging circuit of common-anode LED display screen driving chip Download PDFInfo
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- CN212434213U CN212434213U CN202021588952.7U CN202021588952U CN212434213U CN 212434213 U CN212434213 U CN 212434213U CN 202021588952 U CN202021588952 U CN 202021588952U CN 212434213 U CN212434213 U CN 212434213U
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Abstract
The utility model discloses a be total to positive LED display screen driver chip's pre-charge circuit, include: an input terminal for inputting a precharge pull-UP signal UP1, a precharge pull-UP signal UP2, and a precharge pull-down signal DN; the output end is connected with the resistor R0 in series and used for outputting the electric potential; the first operational amplifier is coupled with a second PMOS (P-channel metal oxide semiconductor) transistor and a third PMOS transistor, and inputs a pre-charge pull-UP signal UP1 and a pre-charge pull-UP signal UP2 through the second PMOS transistor and the third PMOS transistor; the second operational amplifier is coupled with a seventh NMOS tube and inputs a precharge pull-down signal DN through the seventh NMOS tube; the values of the precharge pull-UP signals UP1 and UP2 and the precharge pull-down signal DN input by the configuration input end are amplified by the first operational amplifier and the second operational amplifier to configure the potential value output by the output end. The utility model has the advantages of improve the display effect of LED display screen, effectively improve lower ghost, the first line that appear in the LED display screen dark partially, height grey coupling and the phenomenon of striding the board colour difference.
Description
Technical Field
The utility model belongs to the technical field of the integrated circuit technique and specifically relates to a totally positive LED display screen driver chip's pre-charge circuit is related to.
Background
The LED display screen is an electronic display screen formed by LED lattices, the display content forms of the screen, such as characters, animations, pictures and videos, are changed in time by the red and green lamp beads which are turned on and off, and the display control of the components is carried out through a modular structure. Mainly comprises a display module, a control system and a power supply system. The display module is a screen consisting of LED lamp dot arrays and emits light; the control system realizes the conversion of the content displayed on the screen under the on-off condition in the regulation area; the power supply system converts the input voltage and current to meet the requirement of the display screen. The LED display screen is in scanning display, scanning line lines are respectively driven by the system at different time, and when the next line is driven, the phenomenon that the previous line appears dark and bright is called ghost. And the LED display screen also has the problems of poor display such as dark first line, high-low gray coupling, cross-board chromatic aberration and the like.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a total positive LED display screen driver chip's pre-charge circuit, through the pre-charge pull-up signal and the pre-charge pull-down signal of configuration input, the size of control output potential value improves the display effect of LED display screen, effectively improves the phenomenon of lower ghost, first line dark on the side, height grey coupling and the cross board colour difference that appear in the LED display screen.
In order to solve the technical problem, the utility model provides a technical scheme is: a precharge circuit of a common-anode LED display screen driving chip comprises:
an input terminal for inputting a precharge pull-UP signal UP1, a precharge pull-UP signal UP2, and a precharge pull-down signal DN;
the output end is connected with the resistor R0 in series and used for outputting the electric potential;
the first operational amplifier is coupled with a second PMOS (P-channel metal oxide semiconductor) transistor and a third PMOS transistor, and inputs a pre-charge pull-UP signal UP1 and a pre-charge pull-UP signal UP2 through the second PMOS transistor and the third PMOS transistor;
the second operational amplifier is coupled with a seventh NMOS tube and inputs a precharge pull-down signal DN through the seventh NMOS tube;
the values of the precharge pull-UP signals UP1 and UP2 and the precharge pull-down signal DN input by the configuration input end are amplified by the first operational amplifier and the second operational amplifier to configure the potential value output by the output end.
The above technical scheme is adopted in the utility model, input precharge pull-UP signal UP1, UP2 and precharge pull-down signal DN, through first, second operational amplifier fortune put the back, can dispose the not output potential value of equidimension, show through this potential value drive LED display screen, can improve the display effect of LED display screen to improve the lower ghost phenomenon that appears in the LED display screen.
In the precharge circuit of the common-anode LED display screen driving chip, the first operational amplifier comprises a zero-number PMOS tube, a first PMOS tube, a zero-number NMOS tube, a first NMOS tube and a fourth NMOS tube; the zero NMOS tube is connected with a zero PMOS tube and a second PMOS tube in a circuit mode, the first NMOS tube is connected with a first PMOS tube in a circuit mode, the fourth NMOS tube is connected with the zero NMOS tube and the first NMOS tube in a circuit mode through a second NMOS tube, the first NMOS tube is connected with a resistor R0, and a pre-charging pull-UP signal UP1 is input into a grid electrode of the second NMOS tube.
In the precharge circuit of the common anode LED display screen driving chip, the gate of the third PMOS transistor inverts the precharge pull-UP signal UP2 through the first inverter.
In the precharge circuit of the common-anode LED display screen driving chip, the second operational amplifier includes a fourth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the fourth PMOS tube is connected to the seventh PMOS tube and the eighth PMOS tube through a sixth PMOS tube line, the fifth NMOS tube is connected with the seventh PMOS tube through a line, the sixth NMOS tube is connected with the eighth PMOS tube and the fifth NMOS tube through a line, the sixth NMOS tube is connected with the seventh NMOS tube through a line, and the seventh PMOS tube is connected with the resistor R0.
In the precharge circuit of the common-anode LED display screen driving chip, the gate of the seventh NMOS tube negates the precharge pull-down signal DN through the second inverter.
In the precharge circuit of the common-anode LED display screen driving chip, a precharge first reference potential VR1 is input to the grid electrode of the zero NMOS tube.
In the precharge circuit of the common anode LED display screen driving chip, a precharge second reference potential VR2 is input to the gate of the eighth PMOS transistor.
In the precharge circuit of the common-anode LED display screen driving chip, the fourth NMOS tube is connected with the third NMOS tube, and the bias current IB1 is input by signals of the grid electrode of the fourth NMOS tube and the grid electrode and the drain electrode of the third NMOS tube.
In the precharge circuit of the common anode LED display screen driving chip, the fourth PMOS transistor is connected to a fifth PMOS transistor, and a bias current IB2 is input to signals of a gate of the fourth PMOS transistor and signals of a gate and a drain of the fifth PMOS transistor.
The utility model discloses the beneficial effect who gains is: the circuit is integrated in each constant current source output channel, when the constant current source output is started, the circuit is in a closed state (UP1 is 0, UP2 is 0, and DN is 0), and by controlling the time sequence of UP1, UP2 and DN, the circuit has the following working states and functions:
1. UP1 is 0, UP2 is 0, DN is 0, the circuit is in off state.
2. Before line feed is displayed, after a constant current channel is closed, UP1 is set to be 1, UP2 is set to be 0, DN is set to be 0, an OUT end is charged to VR1 potential by the circuit, and then the circuit has the function of improving ghost shadow of an LED display screen.
3. After the line is displayed and before the constant current channel is opened, UP1 is 1, UP2 is 0, DN is 0, the OUT end is charged to VR1 potential, and the circuit has the function of improving the first line of the LED display screen to be dark.
4. Configure timing appropriate for UP1, UP2, and DN: the circuit is characterized in that UP1 is configured to be 0, UP2 is 1, DN is 0, OUT potential is charged to VDD, UP1 is configured to be 0, UP2 is 0, DN is 1, OUT end potential is charged to VR2 potential, and therefore the potential of a channel can simulate the process of lighting a lamp bead on a display module.
Drawings
Fig. 1 is a circuit structure diagram of an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, the utility model relates to a be positive LED display screen driver chip's pre-charge circuit altogether, include:
an input terminal for inputting a precharge pull-UP signal UP1, a precharge pull-UP signal UP2, and a precharge pull-down signal DN;
the output end is connected with the resistor R0 in series and used for outputting the electric potential;
the first operational amplifier is coupled with a second PMOS (P-channel metal oxide semiconductor) transistor and a third PMOS transistor, and inputs a pre-charge pull-UP signal UP1 and a pre-charge pull-UP signal UP2 through the second PMOS transistor and the third PMOS transistor;
the second operational amplifier is coupled with a seventh NMOS tube and inputs a precharge pull-down signal DN through the seventh NMOS tube;
the values of the precharge pull-UP signals UP1 and UP2 and the precharge pull-down signal DN input by the configuration input end are amplified by the first operational amplifier and the second operational amplifier to configure the potential value output by the output end.
Further, the first operational amplifier comprises a zero-number PMOS transistor NM0, a first PMOS transistor PM1, a zero-number NMOS transistor NM0, a first NMOS transistor NM1 and a fourth NMOS transistor NM 4; the grid electrodes of the zero PMOS pipe PM0 and the first PMOS pipe PM1 are connected with drain electrode circuits of the zero PMOS pipe PM0, the zero NMOS pipe NM0 and the second PMOS pipe PM 2; the drain electrode of the first PMOS pipe PM1 is in line connection with the drain electrode and the grid electrode of the first NMOS pipe NM1 and the resistor R0; the source electrodes of the zero-number NMOS transistor NM0 and the first NMOS transistor NM1 are connected with the fourth NMOS transistor NM4 through the second NMOS transistor NM 2; the gate of the second PMOS transistor PM2 and the gate of the second NMOS transistor NM2 receive the pre-charge pull-UP signal UP1, and the gate of the third PMOS transistor PM3 receive the pre-charge pull-UP signal UP 2. The gate of the third PMOS transistor PM3 inverts the precharge pull-UP signal UP2 through the first inverter INV 1.
Further, the second operational amplifier comprises a fourth PMOS transistor PM4, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM 6; the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor PM6, the drain of the sixth PMOS transistor PM6 is connected to the sources of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8, the drains of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are connected to the drains and gates of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6, the drain of the sixth NMOS transistor NM6 and the drain of the eighth PMOS transistor PM8 are connected to the drain of the seventh NMOS transistor NM7, and the gate of the seventh PMOS transistor PM7 is connected to the resistor R0. The gate of the seventh NMOS transistor inverts the precharge pull-down signal DN through the second inverter INV 2.
Further, the gate of the zero NMOS transistor is inputted with a pre-charged first reference potential VR 1. The gate input of the eighth PMOS transistor is precharged with a second reference potential VR 2.
The fourth NMOS transistor NM4 is connected to the third NMOS transistor NM3, and a bias current IB1 is inputted to the gate of the fourth NMOS transistor and the gate and drain signals of the third NMOS transistor.
The fourth PMOS transistor PM4 is connected to a fifth PMOS transistor PM5 through a line, and a bias current IB2 is inputted to the gate of the fourth PMOS transistor PM4 and the gate and drain of the fifth PMOS transistor PM 5.
The source electrodes of the second PMOS transistor PM2, the zero PMOS transistor PM0, the first PMOS transistor PM1, the third PMOS transistor PM3, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are connected with the VDD end of the input power supply; the sources of the third, fourth, fifth, sixth, and seventh NMOS transistors NM3, NM4, NM5, NM6, and NM7 are connected to the ground GND of the input power.
The circuit is integrated in each constant current source output channel, when the constant current source output is started, the circuit is in a closed state, and values of pre-charging pull-UP signals UP1 and UP2 and pre-charging pull-down signal DN are as follows: UP 1-0, UP 2-0 and DN-0, and by controlling the time sequence of UP1, UP2 and DN, the circuit is in different working states and has different functions.
The values of UP1, UP2 and DN are 0 and 1, and the precharge pull-UP signal and the precharge pull-down signal are highly effective in the circuit, and the circuit configures the values of the precharge pull-UP signal and the precharge pull-down signal, further configures the potential value of the output end, and presents different display effects when driving the LED display screen to display.
1. When UP1 is 0, UP2 is 0, and DN is 0, the circuit is in off state.
2. Before line feed is displayed, after a constant current channel is closed, UP1 is set to be 1, UP2 is set to be 0, DN is set to be 0, the potential of an output end is clamped to VR1 by a first operational amplifier, namely, the circuit charges the potential of the output end to VR1 potential, and at the moment, the circuit has the function of improving ghost shadow of an LED display screen.
3. After line feed is displayed, after a constant current channel is closed, UP1 is set to be 1, UP2 is set to be 0, DN is set to be 0, the first operational amplifier clamps the potential of an output end to VR1, namely, the circuit charges the potential of the output end to VR1 potential, and at the moment, the circuit has the function of improving the first line of the LED display screen to be dark.
4. The circuit is characterized in that UP1 is configured to be 0, UP2 is 1, DN is 0, the output end potential is charged to VDD, UP1 is configured to be 0, UP2 is 0, DN is 1, the output end potential is charged to VR2, the potential of a constant current channel simulates the process of lighting a lamp bead on a display module, and the circuit has the function of improving high-low gray coupling and cross-board color difference in an LED display screen.
In summary, the present invention has been made to practical samples according to the description and the drawings, and after a plurality of use tests, the utility model can be proved to achieve the expected purpose, and the practical value is undoubted. The above-mentioned embodiments are only used to conveniently illustrate the present invention, and are not to the limit of the present invention in any form, and any person who knows commonly in the technical field has, if not in the scope of the technical features of the present invention, utilize the present invention to make the equivalent embodiment of local change or modification, and not to break away from the technical features of the present invention, and all still belong to the technical features of the present invention.
Claims (9)
1. A precharge circuit of a common-anode LED display screen driving chip is characterized by comprising:
an input terminal for inputting a precharge pull-UP signal UP1, a precharge pull-UP signal UP2, and a precharge pull-down signal DN;
the output end is connected with the resistor R0 in series and used for outputting the electric potential;
the first operational amplifier is coupled with a second PMOS (P-channel metal oxide semiconductor) transistor and a third PMOS transistor, and inputs a pre-charge pull-UP signal UP1 and a pre-charge pull-UP signal UP2 through the second PMOS transistor and the third PMOS transistor;
the second operational amplifier is coupled with a seventh NMOS tube and inputs a precharge pull-down signal DN through the seventh NMOS tube;
the values of the precharge pull-UP signals UP1 and UP2 and the precharge pull-down signal DN input by the configuration input end are amplified by the first operational amplifier and the second operational amplifier to configure the potential value output by the output end.
2. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 1, characterized in that: the first operational amplifier comprises a zero-number PMOS tube, a first PMOS tube, a zero-number NMOS tube, a first NMOS tube and a fourth NMOS tube; the zero NMOS tube is connected with a zero PMOS tube and a second PMOS tube in a circuit mode, the first NMOS tube is connected with a first PMOS tube in a circuit mode, the fourth NMOS tube is connected with the zero NMOS tube and the first NMOS tube in a circuit mode through a second NMOS tube, the first NMOS tube is connected with a resistor R0, and a pre-charging pull-UP signal UP1 is input into a grid electrode of the second NMOS tube.
3. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 1, characterized in that: the gate of the third PMOS transistor inverts the pre-charge pull-UP signal UP2 through the first inverter.
4. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 1, characterized in that: the second operational amplifier comprises a fourth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; the fourth PMOS tube is connected to the seventh PMOS tube and the eighth PMOS tube through a sixth PMOS tube line, the fifth NMOS tube is connected with the seventh PMOS tube through a line, the sixth NMOS tube is connected with the eighth PMOS tube and the fifth NMOS tube through a line, the sixth NMOS tube is connected with the seventh NMOS tube through a line, and the seventh PMOS tube is connected with the resistor R0.
5. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 4, wherein: and the grid electrode of the seventh NMOS tube inverts the precharge pull-down signal DN through a second phase inverter.
6. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 2, characterized in that: the gate input of the zero NMOS tube is pre-charged with a first reference potential VR 1.
7. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 4, wherein: the grid electrode of the eighth PMOS tube is input with a pre-charging second reference potential VR 2.
8. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 2, characterized in that: the fourth NMOS pipe line is connected with a third NMOS pipe, and the signals of the grid electrode of the fourth NMOS and the grid electrode and the drain electrode of the third NMOS pipe are input with a bias current IB 1.
9. The pre-charging circuit of the co-anode LED display screen driving chip according to claim 4, wherein: the fourth PMOS tube circuit is connected with a fifth PMOS tube, and the signals of the grid electrode of the fourth PMOS tube and the grid electrode and the drain electrode of the fifth PMOS tube are input with a bias current IB 2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021588952.7U CN212434213U (en) | 2020-08-03 | 2020-08-03 | Pre-charging circuit of common-anode LED display screen driving chip |
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| CN202021588952.7U CN212434213U (en) | 2020-08-03 | 2020-08-03 | Pre-charging circuit of common-anode LED display screen driving chip |
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| CN212434213U true CN212434213U (en) | 2021-01-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785204A (en) * | 2020-08-03 | 2020-10-16 | 四川遂宁市利普芯微电子有限公司 | Pre-charging circuit of common-anode LED display screen driving chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785204A (en) * | 2020-08-03 | 2020-10-16 | 四川遂宁市利普芯微电子有限公司 | Pre-charging circuit of common-anode LED display screen driving chip |
| CN111785204B (en) * | 2020-08-03 | 2023-08-25 | 四川遂宁市利普芯微电子有限公司 | Pre-charging circuit of common-anode LED display screen driving chip |
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Effective date of registration: 20221208 Address after: 1901, Floor 19, Unit 2, Building 4, No. 71, Hele 1st Street, Chengdu, Sichuan 610041 Patentee after: Chengdu Lipson Microelectronics Co.,Ltd. Address before: No.66, Feilong Road, Suining Economic Development Zone, Sichuan 629000 Patentee before: Sichuan Suining Lipuxin Microelectronic Co.,Ltd. |