CN212278294U - Video processing apparatus - Google Patents
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- CN212278294U CN212278294U CN202021246399.9U CN202021246399U CN212278294U CN 212278294 U CN212278294 U CN 212278294U CN 202021246399 U CN202021246399 U CN 202021246399U CN 212278294 U CN212278294 U CN 212278294U
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Abstract
The embodiment of the utility model provides a video processing equipment. The video processing apparatus includes, for example: a first embedded processor; the second embedded processor is electrically connected with the first embedded processor; the programmable logic device is electrically connected with the first embedded processor and the second embedded processor; a clock signal unit electrically connecting the programmable logic device and one of the first embedded processor and the second embedded processor; the synchronous signal generating unit is electrically connected with the programmable logic device; the input interface unit is electrically connected with the second embedded processor and the programmable logic device; and the output interface unit is electrically connected with the second embedded processor and the programmable logic device. The embodiment realizes the system function of the video processing equipment, simplifies the hardware architecture design and reduces the complexity of the hardware design.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a video processing equipment.
Background
In a video processing device (e.g., a video processor, a controller, a switcher, etc.), a single processor is generally used to implement functions of system interaction, input/output interface management, and response chip configuration of the entire device. With the increasing functions and the increasing complexity of video processing equipment, the hardware design difficulty is increased and the requirements are difficult to meet when the functions of system interaction, input and output and the like are realized through a single processor.
Therefore, how to reduce the hardware design difficulty of the video processing device becomes a problem to be solved urgently.
SUMMERY OF THE UTILITY MODEL
Therefore, for overcoming at least some defects and not enough among the prior art, the embodiment of the utility model provides a video processing device to reduce video processing device's the hardware design degree of difficulty, realize more functions of video processing device.
In one aspect, an embodiment of the present invention provides a video processing apparatus, including: a first embedded processor; the second embedded processor is electrically connected with the first embedded processor; the programmable logic device is electrically connected with the first embedded processor and the second embedded processor; a clock signal unit electrically connecting the programmable logic device and one of the first embedded processor and the second embedded processor; the synchronous signal generating unit is electrically connected with the programmable logic device; the input interface unit is electrically connected with the second embedded processor and the programmable logic device; and the output interface unit is electrically connected with the second embedded processor and the programmable logic device.
The video processing device of the embodiment is provided with the first embedded processor and the second embedded processor, the first embedded processor is connected with the programmable logic device, the clock signal unit is connected with one of the first embedded processor and the second embedded processor, the second embedded processor is electrically connected with the input interface unit and the output interface unit, and the first embedded processor and the second embedded processor jointly realize the control of the whole system. For example, the system function of the video processing equipment is realized by controlling the system interaction through the first embedded processor and controlling the input and output interface units through the second embedded processor, the hardware architecture design is simplified, and the hardware design complexity is reduced.
In an embodiment of the present invention, the first embedded processor is connected to the programmable logic device through a gigabit network bus, a serial peripheral interface bus, a first serial interface bus and a first I/O bus, and the second embedded processor is connected to the programmable logic device through a second serial interface bus and a second I/O bus.
In an embodiment of the present invention, the video processing apparatus further includes: the first embedded processor, the second embedded processor, the programmable logic device and the clock signal unit are arranged on the main board card; the synchronous signal generating unit is arranged on the synchronous signal generating daughter card, and the synchronous signal generating daughter card is electrically connected with the main board card through a connector assembly; the input interface unit is arranged on the input sub-card, and the input sub-card is electrically connected with the main board card through a connector; and the output interface unit is arranged on the output daughter card, and the output daughter card is electrically connected with the main board card through a connector assembly.
In one embodiment of the present invention, the first embedded processor is an ARM processor, and the second embedded processor is a micro control unit; or the first embedded processor is an ARM processor, and the second embedded processor is an ARM processor; or the first embedded processor is a micro control unit, and the second embedded processor is a micro control unit.
In an embodiment of the present invention, the clock signal unit includes at least one clock chip, and the at least one clock chip electrically connects the programmable logic device and the first embedded processor.
In an embodiment of the present invention, the video processing apparatus further includes: and the heat dissipation unit is electrically connected with the first embedded processor or the second embedded processor.
In an embodiment of the present invention, the video processing apparatus further includes: the display screen unit is electrically connected with the first embedded processor; and/or a control key unit electrically connected with the first embedded processor.
In an embodiment of the present invention, the video processing apparatus further includes: and the audio decoding chip is electrically connected with the input interface unit, the programmable logic device and the first embedded processor.
In an embodiment of the present invention, the video processing apparatus further includes: and the heat dissipation unit is electrically connected with the first embedded processor.
In an embodiment of the present invention, the video processing apparatus further includes: and the optical probe is electrically connected with the second embedded processor.
On the other hand, the embodiment of the utility model provides a video processing device, include: a first embedded processor; the second embedded processor is electrically connected with the first embedded processor; the programmable logic device is electrically connected with the first embedded processor and the second embedded processor; the clock signal unit is electrically connected with the programmable logic device; the synchronous signal unit is electrically connected with the programmable logic device; the input interface unit is electrically connected with the second embedded processor and the programmable logic device; the output interface unit is electrically connected with the second embedded processor and the programmable logic device; the display screen unit is electrically connected with the first embedded processor; the control key unit is electrically connected with the first embedded processor; the audio decoding chip is electrically connected with the input interface unit, the programmable logic device and the first embedded processor; the heat dissipation unit is electrically connected with the first embedded processor; and the optical probe is electrically connected with the second embedded processor.
The video processing device of the embodiment is provided with the first embedded processor and the second embedded processor, the first embedded processor is connected with the programmable logic device and the clock signal unit, and the second embedded processor is electrically connected with the input interface unit and the output interface unit, so that the system interaction is controlled through the first embedded processor, the input interface unit and the output interface unit are controlled through the second embedded processor, the system function of the video processing device is realized, the hardware architecture design is simplified, and the hardware design complexity is reduced.
In view of the above, the above technical features of the present invention can have one or more of the following advantages: the video processing device of the embodiment is provided with the first embedded processor and the second embedded processor, the first embedded processor is connected with the programmable logic device, the clock signal unit is connected with one of the first embedded processor and the second embedded processor, the second embedded processor is electrically connected with the input interface unit and the output interface unit, and the first embedded processor and the second embedded processor jointly realize the control of the whole system. For example, the system function of the video processing equipment is realized by controlling the system interaction through the first embedded processor and controlling the input and output interface units through the second embedded processor, the hardware architecture design is simplified, and the hardware design complexity is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a video processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram of a circuit connection of a second embedded processor.
Fig. 3 is a schematic circuit diagram of a video processing apparatus according to a first embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a video processing apparatus according to a first embodiment of the present invention.
Fig. 5 is a schematic diagram of another circuit structure of the video processing apparatus according to the first embodiment of the present invention.
Fig. 6 is a schematic diagram of another circuit structure of the video processing apparatus according to the first embodiment of the present invention.
Fig. 7 is a schematic circuit diagram of a video processing apparatus according to a first embodiment of the present invention.
Fig. 8 is a schematic circuit diagram of a video processing apparatus according to a second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1 and fig. 2, an embodiment of the present invention provides a video processing apparatus 100, including: a first embedded processor 110, a second embedded processor 120, a programmable logic device 130, a clock signal unit 140, a synchronization signal generation unit 150, an input interface unit 160, and an output interface unit 170.
Specifically, the first embedded processor 110 is electrically connected to the second embedded processor 120, the programmable logic device 130 is electrically connected to the first embedded processor 110 and the second embedded processor 120, the clock signal unit 140 is electrically connected to one of the first embedded processor 110 and the second embedded processor 120 and the programmable logic device 130 (only the clock signal unit 140 is shown in the figure to be electrically connected to the first embedded processor 110 and the programmable logic device 130), the synchronization signal generation unit 150 is electrically connected to the programmable logic device 130, the input interface unit 160 is electrically connected to the second embedded processor 120 and the programmable logic device 130, and the output interface unit 170 is electrically connected to the second embedded processor 120 and the programmable logic device 130. The first embedded processor 110 and the programmable logic device 130 may be connected via a gigabit bus, a Serial Peripheral Interface (SPI) bus, a first Serial Interface bus, and a first I/O (input/output) bus, and the second embedded processor 120 and the programmable logic device 130 may be connected via a second Serial Interface bus and a second I/O bus, for example. Specifically, the first embedded processor 110 and the programmable logic device 130 may be wired and connected through a PCB (Printed Circuit Board) through a plurality of sets of pins, for example, the plurality of sets of pins may be used for gigabit ethernet communication, serial peripheral interface communication, serial interface communication, and I/O communication, respectively, the gigabit ethernet communication may greatly increase the communication rate between the first embedded processor 110 and the programmable logic device 130, and the first embedded processor 110 may load a program on the editable logic device 130 through the serial peripheral interface; the second embedded processor 120 and the programmable logic device 130 may be wired, for example, via a PCB (Printed Circuit Board) via multiple sets of pins, which may be used for serial interface communication and I/O communication, respectively; of course, the second embedded processor 120 and the programmable logic device 130 may also be connected through a serial peripheral interface bus to load a program, which is not limited to this embodiment of the present invention.
As described above, the video processing apparatus 100 may further include, for example, a main board card, a synchronization signal generation daughter card, an input daughter card, and an output daughter card. The first embedded processor 110, the second embedded processor 120, the programmable logic device 130 and the clock signal unit 140 are arranged on the main board card; the synchronization signal generating unit 150 is disposed on a synchronization signal generating daughter card, and the synchronization signal generating daughter card may be electrically connected to the main board card, for example, through a connector; the input interface unit 160 is disposed on an input daughter card, which may be electrically connected to the main board card, for example, through a connector; the output interface unit 170 is provided on an output daughter card that may be electrically connected to the host card, for example, by a connector. Through the arrangement of the daughter card, the daughter card can be flexibly replaced according to the requirement of the video processing device 10, the hardware design is simplified, and the flexibility of the video processing device 10 is improved. Of course, the synchronization signal generating unit 150, the input interface unit 160, and the output interface unit 180 may also be directly disposed on the main board, and the embodiment of the invention is not limited thereto.
As mentioned above, the first embedded processor 110 may be, for example, an arm (advanced RISC machines) processor, or may also be, for example, an MCU (Micro Control Unit), the first embedded processor 110 is a core Control processor and mainly performs internal and external interaction functions of the video processing device 100, such as network communication, program loading, Control, human-computer interaction, and the like, the second embedded processor 120 may be, for example, an arm (advanced RISC machines) processor, or may also be, for example, an MCU (Micro Control Unit), the second embedded processor 120 is an assist processor and is mainly used to assist the first embedded processor 110 and improve reliability of Control. Specifically, the first embedded processor 110 may be an ARM processor, the second embedded processor 120 may be an MCU, the first embedded processor 110 may be an ARM processor, the second embedded processor 120 may be an ARM processor, the first embedded processor 110 may be an MCU, the second embedded processor 120 may be an MCU, the ARM processor may specifically employ, for example, an RK3128 chip, an RK3368 chip, an RK3399 chip, and the MCU may, for example, employ a GD32F103 series chip, or an STM32F103 series chip, which is, of course, described here by way of example only. The Programmable logic device 130 may be, for example, an FPGA (Field Programmable Gate Array), and may be, for example, a Kinetx-7 series FPGA chip of Xilinx corporation such as XC7K160T chip, or XC7K325T chip or XC7K410T chip.
Referring to fig. 3, the clock signal unit 140 may include at least one clock chip 141, for example, and may also include a plurality of clock chips 141 (only one is shown as an illustration), where the plurality of clock chips 141 are electrically connected to the programmable logic device 130 and the first embedded processor 110, respectively, and the clock chip 141 may be an IDT6965 chip, for example. The synchronization signal generating unit 150 may be, for example, a chip for generating a synchronization signal, and may select, for example, a THS7373 chip, which is not limited to this embodiment of the present invention. The input Interface unit 160 may for example include an input Interface, which may for example be connected to an input Interface chip, which may for example be connected to the second embedded processor 120 and the programmable logic device 130, and the second embedded processor 120 may for example be configured with an I2C (Inter-Integrated Circuit) Interface, which may for example be a Video source input Interface, in particular for example a VGA (Video Graphics Array) Interface, SDI (serial digital Interface), HDMI (High Definition Multimedia Interface), or other Video Interface capable of providing Video signals or virtual Video signals. The output interface unit 170 may for example comprise an output interface, which may for example be connected to an output interface chip, which may for example be connected to the second embedded processor 120 and the programmable logic device 130, which may for example be configured by the second embedded processor 120, for example via an I2C (Inter-Integrated Circuit, two-wire serial bus), and an output interface, which may for example be an ethernet interface, and in particular may for example be an RJ45 interface. Of course, the number and the type of the input interface unit 160 and the output interface unit 170 can be multiple, and the setting can be according to the actual requirement, and the embodiment of the present invention is not limited thereto.
Referring to fig. 4, the video processing apparatus 100 further includes a display screen unit 180 and/or a control key unit 190. The video processing apparatus 100 shown in the figure includes a display screen unit 180 and a control key unit 190, and in practical applications, the video processing apparatus may also include the display screen unit 180 or the control key unit 190, which is not limited thereto. Specifically, the video processing apparatus 100 may include, for example, a control panel on which the display screen unit 180 and the control key unit 190 are disposed to implement a human-computer interaction function. The display screen unit 180 is electrically connected to the first embedded processor 110, and the control key unit 190 is electrically connected to the first embedded processor 110, that is, the first embedded processor 110 controls the human-computer interaction function. The display screen unit 180 may include, for example, a liquid crystal display screen and a display screen driving chip, the display screen driving chip may adopt, for example, a chip ST7789V, and the first embedded processor 110 may load, for example, a Serial Peripheral Interface (SPI) to display an image, so as to complete display of the image on the liquid crystal display screen of the display screen unit 180; the interaction of the first embedded processor 110 with the control key unit 190 may be implemented through an IO extension chip, for example, through an I2C communication protocol and an interrupt signal to implement the response of the control key unit 190.
Referring to fig. 5, the video processing device 100 further includes an audio decoding chip 200, and the audio decoding chip 200 may be electrically connected to the input interface unit 160, the programmable logic device 130, and the first embedded processor 110, for example. The first embedded processor 110 controls the audio decoding chip 200 to decode and convert the audio source input by the input interface unit 160 and transmit the audio source to the programmable logic device 130, and the audio decoding chip 200 may be, for example, an ES8316 chip, although the present invention is not limited thereto.
Referring to fig. 6, the video processing device 100 further includes a heat dissipation unit 210, and the heat dissipation unit 210 is electrically connected to the first embedded processor 110. The heat dissipation unit 210 may include a fan, for example, the first embedded processor 110 controls a fan signal, and may implement functions of controlling the fan and adjusting a rotation speed, for example, through Pulse Width Modulation (PWM).
Referring to fig. 7, the video processing device 100 further comprises a light probe 220, the light probe 220 is electrically connected to the second embedded processor 120, and the second embedded processor 120 can control the light probe 220 to collect external light intensity conditions, for example.
To sum up, the embodiment of the utility model provides a through setting up first embedded processor and the embedded treater of second, programmable logic device is connected to first embedded treater, and one of first embedded treater and the embedded treater of second is connected to the clock signal unit, and input interface unit and output interface unit are connected to the embedded treater electricity of second, and the control to entire system is realized jointly to first embedded treater and the embedded treater of second. For example, the first embedded processor controls system interaction, and the second embedded processor controls the input interface unit and the output interface unit, so that the hardware architecture design is simplified, and the hardware design complexity is reduced.
[ second embodiment ]
Referring to fig. 8, an embodiment of the present invention provides a video processing apparatus 10, including: the system comprises a first embedded processor 110, a second embedded processor 120, a programmable logic device 130, a clock signal unit 140, a synchronous signal generating unit 150, an input interface unit 160, an output interface unit 170, a display screen unit 180, a control key unit 190, an audio decoding chip 200, a heat dissipation unit 210 and an optical probe 220.
Specifically, the first embedded processor 110 is electrically connected to the second embedded processor 120, the programmable logic device 130 is electrically connected to the first embedded processor 110 and the second embedded processor 120, the clock signal unit 140 is electrically connected to the programmable logic device 130 and the first embedded processor 110, the synchronization signal generating unit 150 is electrically connected to the programmable logic device 130, the input interface unit 160 is electrically connected to the second embedded processor 120 and the programmable logic device 130, and the output interface unit 170 is electrically connected to the second embedded processor 120 and the programmable logic device 130; the display screen unit 180 is electrically connected to the first embedded processor 110, and the control key unit 190 is electrically connected to the first embedded processor 110; the audio decoding chip 200 may, for example, be electrically connected to the input interface unit 160, the programmable logic device 130, and the first embedded processor 110; the heat dissipation unit 210 is electrically connected to the first embedded processor 110; the optical probe 220 is electrically connected to the second embedded processor 120.
As mentioned above, the first embedded processor 110 may be, for example, an arm (advanced RISC machines) processor, or may also be, for example, an MCU (Micro Control Unit), the first embedded processor 110 is a core Control processor and mainly performs internal and external interaction functions of the video processing device 100, such as network communication, program loading, Control, human-computer interaction, and the like, the second embedded processor 120 may be, for example, an arm (advanced RISC machines) processor, or may also be, for example, an MCU (Micro Control Unit), the second embedded processor 120 is an assist processor and is mainly used to assist the first embedded processor 110 and improve reliability of Control. Specifically, the first embedded processor 110 may be an ARM processor, the second embedded processor 120 may be an MCU, the first embedded processor 110 may be an ARM processor, the second embedded processor 120 may be an ARM processor, the first embedded processor 110 may be an MCU, the second embedded processor 120 may be an MCU, the ARM processor may specifically employ, for example, an RK3128 chip, an RK3368 chip, an RK3399 chip, and the MCU may, for example, employ a GD32F103 series chip, or an STM32F103 series chip, which is, of course, described here by way of example only. The Programmable logic device 130 may be, for example, an FPGA (Field Programmable Gate Array), and may be, for example, a Kinetx-7 series FPGA chip of Xilinx corporation such as XC7K160T chip, or XC7K325T chip or XC7K410T chip. The input Interface unit 160 may for example include an input Interface, which may for example be connected to an input Interface chip, which may for example be connected to the second embedded processor 120 and the programmable logic device 130, and the second embedded processor 120 may for example be configured with an I2C (Inter-Integrated Circuit) Interface, which may for example be a Video source input Interface, in particular for example a VGA (Video Graphics Array) Interface, SDI (serial digital Interface), HDMI (High Definition Multimedia Interface), or other Video Interface capable of providing Video signals or virtual Video signals. The output interface unit 170 may for example comprise an output interface, which may for example be connected to an output interface chip, which may for example be connected to the second embedded processor 120 and the programmable logic device 130, which may for example be configured by the second embedded processor 120, for example via an I2C (Inter-Integrated Circuit, two-wire serial bus), and an output interface, which may for example be an ethernet interface, and in particular may for example be an RJ45 interface. Of course, the number and the type of the input interface unit 160 and the output interface unit 170 can be multiple, and the setting can be according to the actual requirement, and the embodiment of the present invention is not limited thereto.
To sum up, the embodiment of the utility model provides a through setting up first embedded treater and the embedded treater of second, programmable logic device and clock signal unit are connected to first embedded treater, and input interface unit and output interface unit are connected to the embedded treater electricity of second to through first embedded treater control system interaction, through the embedded treater control input output interface unit of second, realized video processing equipment's system function, simplified the hardware architecture design, reduced the hardware design complexity.
In addition, it should be understood that the foregoing embodiments are merely exemplary of the present invention, and the technical solutions of the embodiments can be arbitrarily combined and collocated without conflict between technical features and structures, and not departing from the purpose of the present invention.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. A video processing apparatus, comprising:
a first embedded processor;
the second embedded processor is electrically connected with the first embedded processor;
the programmable logic device is electrically connected with the first embedded processor and the second embedded processor;
a clock signal unit electrically connecting the programmable logic device and one of the first embedded processor and the second embedded processor;
the synchronous signal generating unit is electrically connected with the programmable logic device;
the input interface unit is electrically connected with the second embedded processor and the programmable logic device;
and the output interface unit is electrically connected with the second embedded processor and the programmable logic device.
2. The video processing device of claim 1, wherein the first embedded processor is coupled to the programmable logic device via a gigabit network bus, a serial peripheral interface bus, a first serial interface bus, and a first I/O bus, and wherein the second embedded processor is coupled to the programmable logic device via a second serial interface bus and a second I/O bus.
3. The video processing device of claim 1, further comprising:
the first embedded processor, the second embedded processor, the programmable logic device and the clock signal unit are arranged on the main board card;
the synchronous signal generating unit is arranged on the synchronous signal generating daughter card, and the synchronous signal generating daughter card is electrically connected with the main board card through a connector assembly;
the input interface unit is arranged on the input sub-card, and the input sub-card is electrically connected with the main board card through a connector; and
and the output interface unit is arranged on the output daughter card, and the output daughter card is electrically connected with the main board card through a connector assembly.
4. The video processing device of claim 1,
the first embedded processor is an ARM processor, and the second embedded processor is a micro control unit; or
The first embedded processor is an ARM processor, and the second embedded processor is an ARM processor; or
The first embedded processor is a micro control unit, and the second embedded processor is a micro control unit.
5. The video processing device of claim 1, wherein the clock signal unit includes at least one clock chip electrically connecting the programmable logic device and the first embedded processor.
6. The video processing device of claim 1, further comprising: and the heat dissipation unit is electrically connected with the first embedded processor or the second embedded processor.
7. The video processing device of claim 1, further comprising:
the display screen unit is electrically connected with the first embedded processor; and/or
And the control key unit is electrically connected with the first embedded processor.
8. The video processing device of claim 1, further comprising:
and the audio decoding chip is electrically connected with the input interface unit, the programmable logic device and the first embedded processor.
9. The video processing device of claim 1, further comprising: and the optical probe is electrically connected with the second embedded processor.
10. A video processing apparatus, comprising:
a first embedded processor;
the second embedded processor is electrically connected with the first embedded processor;
the programmable logic device is electrically connected with the first embedded processor and the second embedded processor;
the clock signal unit is electrically connected with the programmable logic device;
the synchronous signal unit is electrically connected with the programmable logic device;
the input interface unit is electrically connected with the second embedded processor and the programmable logic device;
the output interface unit is electrically connected with the second embedded processor and the programmable logic device;
the display screen unit is electrically connected with the first embedded processor;
the control key unit is electrically connected with the first embedded processor;
the audio decoding chip is electrically connected with the input interface unit, the programmable logic device and the first embedded processor;
the heat dissipation unit is electrically connected with the first embedded processor; and
and the optical probe is electrically connected with the second embedded processor.
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| CN202021246399.9U CN212278294U (en) | 2020-06-29 | 2020-06-29 | Video processing apparatus |
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| CN202021246399.9U CN212278294U (en) | 2020-06-29 | 2020-06-29 | Video processing apparatus |
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