CN210958308U

CN210958308U - Edge detection circuit and edge conversion circuit of integrated magnetic isolation chip

Info

Publication number: CN210958308U
Application number: CN201921367598.2U
Authority: CN
Inventors: 王佐; 袁思彤; 文守甫; 王建斌; 罗和平; 程瑜; 李威
Original assignee: Yibin Xuxin Semiconductor Co ltd
Current assignee: CHENGDU MAOYANG ELECTRONIC SCIENCE & TECHNOLOGY Co.,Ltd.
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2020-07-07
Anticipated expiration: 2029-08-22

Abstract

An edge detection circuit and an edge conversion circuit of an integrated magnetic isolation chip relate to the integrated circuit technology. The utility model discloses a: the source electrode of the first PMOS tube is connected with a reference high level, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the grid electrode of the first PMOS tube is connected with the signal input end and the first output point; the drain electrode of the second PMOS tube is connected with a second reference point, and the grid electrode of the second PMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube; a source electrode of the third PMOS tube is connected with a reference high level, and a drain electrode of the third PMOS tube is grounded through the first current source; the source electrode of the fourth NMOS tube is grounded, the grid electrode and the drain electrode of the fourth NMOS tube are connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the fourth NMOS tube is also connected with the output end of the second current source; a source electrode of the fifth NMOS tube is connected with a drain electrode of the sixth NMOS tube, a drain electrode of the fifth NMOS tube is connected with the second output point, and the drain electrode is grounded through a capacitor; and the source electrode of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube is connected with the signal input end. The utility model has the advantages that voltage ratio is more stable, has not had the problem of drain electrode parasitic capacitance charge-discharge, and switching speed is fast, does not have the problem of electric charge reposition of redundant personnel moreover. And simultaneously, the problem of charge injection of digital control signals is solved.

Description

Edge detection circuit and edge conversion circuit of integrated magnetic isolation chip

Technical Field

The utility model relates to an integrated circuit technique.

Background

The isolator is used for isolating circuit modules with independent functions in a circuit system in the occasions of medical treatment, communication, industrial bus control and the like, so that the mutual influence among the functional modules is avoided, and a sensitive circuit is protected from being damaged by dangerous voltage and current. In fig. 2, 3 and 4 it is shown that two grounds, gnd1 and gnd2, gnd1 and gnd2, may be at different potentials.

The circuit isolation device which is used in large quantity for a long time is an optical coupler device, but the optical coupler device has short service life, low data transmission rate, unstable performance and overlarge volume, and the defects are very obvious.

A new way of isolation that has emerged in the last decade is isolation using on-chip integrated transformers as the isolation devices, i.e. magnetic coupling isolation. The integrated transformer on the chip is processed on a silicon chip, and a layer of isolation material is arranged between a primary end coil and a secondary end coil of the transformer, so that the isolation effect is achieved. Magnetic coupling isolation data communication over the isolation layer is achieved by means of a varying magnetic field between the two coils using the law of electromagnetic induction. The magnetic coupling isolation has the advantages of long service life, high data transmission rate, stable performance, small volume and the like.

Fig. 1(a) is a schematic diagram of such chip architecture, in which DIE1, DIE2, and DIE3 are an encoder chip, a decoder chip, and a silicon-based transformer chip, respectively, DIE1 and DIE2 are designed using conventional CMOS processes, and DIE3 is designed using a self-developed manufacturing process. The three dice, DIE1, DIE2, and DIE3, are integrated into a package and connected by package wires.

Because the integrated magnetic coupling isolation device is small in size and small in coil inductance, the coupling coefficient of the primary end coil and the secondary end coil in a high-frequency section is higher, and the integrated magnetic coupling isolation device is more beneficial to signal transmission, the input low-frequency square wave signal is generally coded, and the frequency of the coded low-frequency square wave signal is improved so as to be beneficial to transmission of the coded low-frequency square wave signal through a transformer. One commonly used method of increasing the frequency is to perform edge detection on the incoming square wave signal, convert the rising and falling edges of the square wave signal into short pulses of about two nanoseconds duration, and then restore them to the rising or falling edges of the square wave after the pulses have passed through the transformer. This method has a problem of how to distinguish between rising and falling edges. Fig. 1(b) is a flowchart of this codec process.

Document [1] describes a method of transmitting a rising edge pulse and a falling edge pulse separately using two transformers, as shown in fig. 2. In the scheme, the rising edge and the falling edge of an input square wave are respectively converted into a single pulse, then the two single pulses are respectively transmitted by two different transformers, and after passing through the transformers, the two single pulses are respectively restored into the rising edge and the falling edge. The disadvantage of this approach is that two transformers are required, wasting chip area.

Documents [2] and [3] describe a double-single pulse coding scheme, as shown in fig. 3. In this scheme, the rising edge is represented by a double pulse and the falling edge is represented by a single pulse. The disadvantage of this solution is that the decoding circuit needs to recognize double pulses and single pulses, and a certain distance is needed between the double pulses and the single pulses, which affects the data transmission rate (i.e. a certain distance is needed between the rising edge and the falling edge of the input square wave signal, so that the frequency of the square wave signal cannot be too high). Meanwhile, the encoding and decoding circuits are relatively complex.

By search, the maximum transmission rate of the magnetic coupling isolation product in the market is 150Mbps (bps is bit per second, which is applied to non-return-to-zero signals, the same applies below), i.e. 75MHz square wave frequency (see document [4 ]).

Reference documents:

[1]B.Chen,J.Wynne,and R.Lkiger,“High speed digital isolators usingmicroscale on-chip transformers,”Elektronik Mag.,2003.

[2]B.Chen,“Fully integrated isolated DC-DC converter usingmicrotransformers,”in Proc.23rd Annual IEEE Applied Power Electronics Conf.,Feb.2008,pp.335–338.

[3]B.Chen,“Isolated half-bridge gate driver with integrated high-sidesupply,”in Proc.IEEE Power Electronics Specialists Conf.,Jun.2008,pp.3615–3618.

[4]Digital-Isolator-Product-Selection-Guide.pdf， http://www.analog.com/media/en/technical-documentation/product-selector-card/Digital-Isolator-Product-Selection-Guide.pdf

SUMMERY OF THE UTILITY MODEL

The pulse width generated by the traditional edge detection circuit is greatly influenced by the manufacturing process, voltage and temperature of the integrated circuit, and the stability and reliability of the performance of the isolator chip are influenced. To this problem, the utility model provides a new border detection circuit can reduce the dependence of pulse width to integrated circuit manufacturing process, voltage and temperature greatly, has improved pulse width's stability to improve isolator chip's stability and reliability.

The utility model provides a technical scheme that technical problem adopted is, the border detection circuitry of chip is kept apart to integrated magnetism, a serial communication port, include:

the source electrode of the first PMOS tube is connected with a reference high level, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the grid electrode of the first PMOS tube is connected with the signal input end and the first output point;

the drain electrode of the second PMOS tube is connected with the second output point, and the grid electrode of the second PMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube;

a source electrode of the third PMOS tube is connected with a reference high level, and a drain electrode of the third PMOS tube is grounded through the first current source;

the source electrode of the fourth NMOS tube is grounded, the grid electrode and the drain electrode of the fourth NMOS tube are connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the fourth NMOS tube is also connected with the output end of the second current source;

a source electrode of the fifth NMOS tube is connected with a drain electrode of the sixth NMOS tube, a drain electrode of the fifth NMOS tube is connected with the second output point, and the drain electrode is grounded through a capacitor;

and the source electrode of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube is connected with the signal input end.

The utility model also provides a border converting circuit of border detection circuit with aforementioned integrated magnetism keeps apart chip, a serial communication port, the first input of AND gate is connected to first delivery point, and the second input of AND gate is connected to the second delivery point, and the output of AND gate is as the output of rising edge short pulse. The first output point is connected with the first input end of the AND gate through two NOT gates connected in series, the second output point is connected with the second input end of the AND gate through two NOT gates connected in series,

the utility model also provides a border converting circuit of border detection circuit with aforementioned integrated magnetism keeps apart chip, a serial communication port, the first input of NOR gate is connected to first delivery point, and the second input of NOR gate is connected to the second delivery point, and the output of NOR gate is as the output of falling edge short pulse. The first output point is connected with the first input end of the NOR gate through two series-connected NOT gates, and the second output point is connected with the second input end of the NOR gate through two series-connected NOT gates.

The utility model has the advantages that voltage ratio is more stable, has not had the problem of drain electrode parasitic capacitance charge-discharge, and switching speed is fast, does not have the problem of electric charge reposition of redundant personnel moreover. And simultaneously, the problem of charge injection of digital control signals is solved. The source switch charge pump is applied to the edge detection circuit by utilizing the stability of current to the time required by charging and discharging of the capacitor and the excellent charging and discharging performance of the source switch charge pump, so that the output pulse with stable duration is realized.

The utility model discloses the pulse width who produces receives integrated circuit manufacturing process deviation, the influence of chip supply voltage fluctuation and chip temperature variation less, and its output pulse width's deviation only is one fifth (only consider the temperature influence) to the third (consider the influence of technology, voltage and temperature simultaneously) of traditional border detection circuit, can improve isolator chip job stabilization nature and reliability greatly.

Drawings

Fig. 1 is a schematic diagram of a chip architecture and a data transmission flow of a circuit isolator, where a is a schematic diagram of the chip architecture and b is a schematic diagram of the data transmission flow.

Fig. 2 shows a forward single-pulse two-transformer codec scheme.

Fig. 3 is a double-single pulse codec scheme.

Fig. 4 is a schematic diagram of a prior art rising edge transition circuit.

Fig. 5 is a schematic diagram of a falling edge switching circuit of the prior art.

Fig. 6 is a circuit diagram of the rising edge switching circuit of the present invention.

Fig. 7 is a circuit diagram of the falling edge switching circuit of the present invention.

Fig. 8 is a timing diagram for detecting the rising edge of an input square wave.

Detailed Description

The conventional edge detection circuit uses the delay effect of a digital logic gate to generate short pulses, as shown in fig. 4 and 5, where fig. 4 is used to detect the rising edge of an input square wave and fig. 5 is used to detect the falling edge of the input square wave. The input square wave signal reaches an AND gate or a NOR gate through two paths, one path directly reaches the NOR gate, the other path passes through an odd number of inverters to delay and invert the input square wave, finally, a short pulse corresponding to a rising edge is obtained at the output end of the AND gate, and a short pulse corresponding to a falling edge is obtained at the output end of the NOR gate. The duration of the pulse depends on the delay time of the delay circuit. The capacitor functions to increase the delay time of the delay circuit. The delay using the inverter has the obvious disadvantage that the delay of the inverter is greatly influenced by process deviation, power supply voltage change and temperature change, and fixed delay is not easy to obtain.

Referring to fig. 6, when the first PMOS transistor M1 (referred to as M1 in the figure, and similarly referred to as other devices) is turned off and M6 is turned on, M2 provides a constant current to charge C2, and the voltage at the output terminal rises; when M6 is turned off and M1 is turned on, M5 supplies a constant current to discharge capacitor C2 and the output voltage drops.

FIG. 6 is a diagram for detecting a rising edge of an input square wave signal, and outputting a short pulse when the rising edge is coming; fig. 7 is used for detecting the falling edge of the input square wave signal, and when the falling edge comes, a short pulse is output. The operation of the circuit will now be described by taking fig. 6 as an example, in conjunction with the timing diagram of fig. 8. The principle of operation of fig. 7 can be seen in fig. 6, with the difference being the gates in the end sections.

In FIG. 6, IB is a constant bias current for biasing the current mirrors M2 and M3, and M4 and M5. When the input square wave signal is still at low level, M1 is turned off, M6 is turned on, current source M2 charges capacitor C2 with a constant current IB, and capacitor C2 is charged to the supply voltage. When the rising edge of the square wave signal arrives, M1 turns off, M6 turns on, C2 discharges through M5 with a constant current IB, and the voltage on node N2 begins to drop linearly. When the voltage of N2 drops to the threshold voltage of inverter INV3, INV3 flips and the voltage of N4 jumps (see fig. 8). N4 is the delay and inverse of the input square wave N1, the delay time is the time required for C2 to discharge from the supply voltage to the threshold voltage of INV3 plus the delays of INV3 and INV 4; n3 is the delay of the input square wave N1, the delay time is INV1 plus the delay of INV 2. N3 and N4 finally generate a pulse at N5 corresponding to the rising edge of the input square wave through the and gate. Since the delay of INV1 plus INV2 is equal to the delay of INV3 plus INV4, the duration of this pulse is determined only by the discharge time of C2. To improve the noise immunity of the circuit, the inverters INV1 and INV3 may be replaced with schmitt triggers.

The circuits of fig. 4 and 6 were simulated using a 0.5 micron mixed signal integrated circuit process, assuming constant IB, and the simulation results are shown in tables one and two. The first table is the pulse width obtained under the condition that the process deviation and the voltage fluctuation are not considered and only the temperature change is considered; the second table shows the pulse width obtained by considering the manufacturing process variation of the integrated circuit, the power supply voltage fluctuation of the chip and the temperature variation. In the first table, the simulation temperature range is-55 ℃ to 125 ℃; table two shows the results of the full process corner simulation performed on the circuit, in which the resistance variation range is about ± 10%, the capacitance variation range is ± 14%, the NMOS and PMOS threshold voltage variation range is about ± 15%, the voltage variation range is ± 10%, and the simulation temperature range is-55 ℃ to 125 ℃. The relative pulse deviations in the table are defined as:

table one: pulse width simulation results considering only temperature variation

Table two: pulse width simulation result obtained by simultaneously considering process deviation, voltage fluctuation and temperature change

From the simulation results of table one and table two, it can be seen that the edge detection circuit using the source switch charge pump can greatly reduce the pulse width deviation.

The simulations in tables one and two use a constant bias current IB, which in practical circuits is also affected by process variations, voltage fluctuations and temperature variations. It is found that if only the temperature influence is taken into account, the temperature coefficient of the bias current generated by the bias current circuit is only 30 ppm/c or less (see documents [4] and [5]), that is, the bias current deviation is only 0.5% in the range of-55 c to 125 c, and the contribution of this deviation in table one is negligible. If the process deviation, voltage fluctuation and temperature variation are taken into consideration at the same time, the bias current deviation value is only within 10% (see documents [6] and [7]), and the data in table two can be corrected by the deviation value. Since the pulse width variation caused by the edge detection circuit itself and the pulse width variation caused by the bias current are not correlated with each other, the 6-pulse width deviation value is corrected by the following formula:

where Δ t is the total deviation, Δ t₁For deviations caused by the edge detection circuit itself, i.e. 25.8%, Δ t₂For the bias current deviation, i.e. 10%, Δ t can be calculated to be 27.7%, i.e. even if the bias current deviation is considered, the deviation of the pulse width generated by the edge detection circuit applying the source switch charge pump is only one third of that of the conventional edge detection circuit.

And (4) conclusion: the source switch charge pump is used as a delay circuit of the edge detection circuit, and the deviation of the output pulse width of the delay circuit is only one fifth (only considering the temperature influence) to one third (simultaneously considering the process, the voltage and the temperature influence) of the traditional edge detection circuit.

Claims

1. An edge detection circuit integrated with a magnetically isolated chip, comprising:

a first PMOS transistor (M1) having a source connected to a reference high level, a drain connected to the source of the second PMOS transistor (M2), and a gate connected to the signal input terminal and the first output node (N1);

a second PMOS transistor (M2), the drain of which is connected to the second output point (N2), and the gate of which is connected to the gate and the drain of the third PMOS transistor (M3);

a third PMOS transistor (M3), the source of which is connected with the reference high level and the drain of which is grounded through the first current source;

the source electrode of the fourth NMOS tube (M4) is grounded, the grid electrode and the drain electrode of the fourth NMOS tube are connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the fourth NMOS tube is also connected with the output end of the second current source;

a fifth NMOS transistor (M5), the source of which is connected to the drain of the sixth NMOS transistor (M6), the drain of which is connected to the second output point (N2), and the drain of which is grounded through a capacitor (C2);

and the source electrode of the sixth NMOS tube (M6) is grounded, and the grid electrode of the sixth NMOS tube is connected with the signal input end.

2. The edge switching circuit of the edge detector circuit with an integrated magnetically isolated chip of claim 1, wherein the first output point (N1) is connected to a first input of an and gate, the second output point (N2) is connected to a second input of the and gate, and the output of the and gate is used as an output for the rising edge short pulse.

3. The edge conversion circuit of claim 2, wherein the first output point (N1) is connected to the first input of the and gate by two series connected not gates, and the second output point (N2) is connected to the second input of the and gate by two series connected not gates.

4. The edge switching circuit of the edge detector circuit with an integrated magnetically isolated chip of claim 1 wherein the first output point (N1) is connected to a first input of a nor gate, the second output point (N2) is connected to a second input of the nor gate, and the output of the nor gate is used as an output for a short pulse of falling edges.

5. The edge conversion circuit of claim 4, wherein the first output point (N1) is connected to the first input of the NOR gate by two series-connected NOT gates, and the second output point (N2) is connected to the second input of the NOR gate by two series-connected NOT gates.