CN210956679U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
- Publication number
- CN210956679U CN210956679U CN201922361703.8U CN201922361703U CN210956679U CN 210956679 U CN210956679 U CN 210956679U CN 201922361703 U CN201922361703 U CN 201922361703U CN 210956679 U CN210956679 U CN 210956679U
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- semiconductor substrate
- layer
- semiconductor device
- passivation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000002161 passivation Methods 0.000 claims abstract description 145
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 239000010410 layer Substances 0.000 claims description 155
- 239000004642 Polyimide Substances 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
A semiconductor device is provided. The semiconductor device includes: a semiconductor substrate; and the passivation film is arranged on the semiconductor substrate and comprises a first passivation layer, a second passivation layer and a third passivation layer, wherein the first passivation layer is arranged on the semiconductor substrate, the second passivation layer is arranged on one side, away from the semiconductor substrate, of the first passivation layer, the third passivation layer is arranged on one side, away from the semiconductor substrate, of the second passivation layer, the orthographic projection of the second passivation layer on the semiconductor substrate covers the orthographic projection of the first passivation layer on the semiconductor substrate, and the orthographic projection area of the second passivation layer on the semiconductor substrate is larger than that of the first passivation layer on the semiconductor substrate.
Description
Technical Field
The embodiment of the utility model provides a relate to semiconductor device technical field, especially relate to a semiconductor device.
Background
Silicon carbide (SiC) as third generation wide bandgap semiconductor materialThe material has the advantages of large forbidden band width, high critical breakdown field strength, high electron mobility, high thermal conductivity and the like. In SiC-based semiconductor devices, a single layer of silicon oxide (SiO) is typically used on the chip surface to improve the electrical performance and reliability of the device2) Silicon nitride (SiN) or phosphosilicate glass (PSG) as a passivation film. In recent years, Polyimide (PI) has been widely used in the semiconductor field, and its high temperature and chemical stability serve to isolate a metal layer from various external environments. Practice proves that the single-layer polyimide is used as the passivation film, so that the semiconductor device has low leakage current, strong mechanical property and chemical corrosion resistance, and meanwhile, the polyimide passivation film can effectively improve the moisture resistance of components, thereby improving the electrical property and reliability of the semiconductor device.
However, a single layer of silicon oxide (SiO)2) Silicon nitride (SiN), phosphosilicate glass (PSG), Polyimide (PI), or the like, which have their own characteristics and defects. For example, in the case of a single-layer silicon oxide passivation film, on the one hand, silicon oxide has a stress close to that of a SiC substrate to ensure stability at an interface, and on the other hand, the poor particle penetration resistance, radiation sensitivity, and the difficulty in forming a pure silicon oxide film all limit the application of the single-layer silicon oxide passivation film.
Therefore, the passivation film of the conventional semiconductor device has certain defects, and further improvement is required.
SUMMERY OF THE UTILITY MODEL
In order to solve at least one aspect of the above problems, the present invention provides a semiconductor device.
In one aspect, there is provided a semiconductor device including:
a semiconductor substrate; and
a passivation film disposed on the semiconductor substrate, the passivation film including a first passivation layer, a second passivation layer, and a third passivation layer,
wherein the first passivation layer is disposed on the semiconductor substrate, the second passivation layer is disposed on a side of the first passivation layer away from the semiconductor substrate, and the third passivation layer is disposed on a side of the second passivation layer away from the semiconductor substrate,
the orthographic projection of the second passivation layer on the semiconductor substrate covers the orthographic projection of the first passivation layer on the semiconductor substrate, and the area of the orthographic projection of the second passivation layer on the semiconductor substrate is larger than that of the orthographic projection of the first passivation layer on the semiconductor substrate.
According to some exemplary embodiments, an orthographic projection of the third passivation layer on the semiconductor substrate covers an orthographic projection of the second passivation layer on the semiconductor substrate, and an area of the orthographic projection of the third passivation layer on the semiconductor substrate is larger than an area of the orthographic projection of the second passivation layer on the semiconductor substrate.
According to some exemplary embodiments, the semiconductor device further includes a scribe line disposed on the semiconductor substrate.
According to some exemplary embodiments, the first passivation layer includes a side surface adjacent to the scribe line, the second passivation layer includes a side surface adjacent to the scribe line, and a vertical distance between the side surface of the second passivation layer and the side surface of the first passivation layer is in a range of 2 to 5 μm.
According to some exemplary embodiments, the third passivation layer includes a side surface adjacent to the scribe line, and a vertical distance between the side surface of the third passivation layer and the side surface of the second passivation layer is in a range of 5 to 10 μm.
According to some exemplary embodiments, the semiconductor device further includes a field oxide layer and an interlayer dielectric layer disposed between the semiconductor substrate and the passivation film, the interlayer dielectric layer being located on a side of the field oxide layer away from the semiconductor substrate.
According to some exemplary embodiments, an orthographic projection of each of the first, second and third passivation layers on the semiconductor substrate covers an orthographic projection of each of the field oxide layer and the interlayer dielectric layer on the semiconductor substrate.
According to some exemplary embodiments, the first passivation layer is an oxide layer, the second passivation layer is a silicon nitride layer, and the third passivation layer is a polyimide layer.
According to some exemplary embodiments, the semiconductor substrate comprises silicon carbide.
According to some exemplary embodiments, the semiconductor device is a metal oxide semiconductor field effect transistor.
According to the utility model discloses semiconductor device utilizes the passive film that has laminated structure, can utilize the respective advantage of each passivation layer to improve the wholeness ability of passive film, thereby improve semiconductor device's electrical property and reliability.
Drawings
Other objects and advantages of the present invention will become apparent from the following description of the invention, which is made with reference to the accompanying drawings, and can help to provide a thorough understanding of the present invention.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; and
fig. 2 is a schematic structural diagram of a passivation film of a semiconductor device according to an embodiment of the present invention.
It is noted that in the accompanying drawings used to describe embodiments of the invention, the dimensions of layers, structures or regions may be exaggerated or reduced for clarity, i.e., the drawings are not drawn to scale.
Detailed Description
The technical solution of the present invention is further specifically described below by way of examples and with reference to the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the general technical concept of the present invention and should not be construed as limiting the present invention.
Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details.
It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.
It is further noted that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the embodiments of the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be constructed in a particular manner of operation, and are not to be construed as limiting the present invention. Moreover, it will be understood that the orientation or positional relationship indicated by these terms may be changed accordingly when the orientation of the drawings is changed, for example, if the device in the drawings is turned upside down, elements described as "under" or "beneath" other elements or features will be oriented "on" or "above" the other elements or features.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a passivation film of a semiconductor device according to an embodiment of the present invention. Referring to fig. 1 and 2 in combination, a semiconductor device according to an embodiment of the present invention may include a semiconductor substrate 1 and a passivation film 2 disposed on the semiconductor substrate 1. For example, the semiconductor substrate 1 may be a silicon carbide (SiC) substrate.
In the embodiment of the present invention, the passivation film 2 may include a first passivation layer 21, a second passivation layer 22 and a third passivation layer 23, the first passivation layer 21, the second passivation layer 22 and the third passivation layer 23 are sequentially disposed on the semiconductor substrate 1, that is, the first passivation layer 21 is disposed on the semiconductor substrate 1, the second passivation layer 22 is disposed on one side of the first passivation layer 21 away from the semiconductor substrate 1, and the third passivation layer 23 is disposed on one side of the second passivation layer 22 away from the semiconductor substrate 1.
Alternatively, the first passivation layer 21 may be an oxide layer, for example, the oxide layer may be a silicon oxide layer, an aluminum oxide layer, or the like, including, but not limited to, at least one selected from Undoped Silicate Glass (USG), phosphorus-doped silicate glass (PSG), boron-doped silicate glass (BSG), and borophosphosilicate glass (BPSG) layers.
Alternatively, the second passivation layer 22 may be a silicon nitride layer.
Alternatively, the third passivation layer 23 may be a Polyimide (PI) layer.
In the embodiment of the present invention, the passivation film has a multi-layered passivation layer structure, and the respective advantages of each passivation layer can be utilized to improve the overall performance of the passivation film, thereby improving the electrical performance and reliability of the semiconductor device.
With further reference to fig. 1 and 2, an orthographic projection of the second passivation layer 22 on the semiconductor substrate 1 may cover an orthographic projection of the first passivation layer 21 on the semiconductor substrate 1, and an area of the orthographic projection of the second passivation layer 22 on the semiconductor substrate 1 is larger than an area of the orthographic projection of the first passivation layer 21 on the semiconductor substrate 1. In manufacturing the passivation film, an etching process is generally used to form the passivation layer. The embodiment of the utility model provides an in, through above-mentioned mode of setting, at the in-process that the sculpture formed the second passivation layer, the second passivation layer that is located the top can protect the first passivation layer that is located the below, avoids forming the in-process of second passivation layer at the sculpture and excessively etches to first passivation layer.
As shown in fig. 1, the semiconductor device may include a scribe line 3. It will be understood by those skilled in the art that on a wafer or semiconductor substrate, there are typically multiple dies connected together with a gap of 80 μm to 150 μm between each die to facilitate dicing, and these abbreviations may be referred to as dicing channels (dicing channels) or dicing channels (scribes).
Referring to fig. 1 and 2 in combination, the first passivation layer 21 has a side 211 adjacent to the scribe line 3, and the second passivation layer 22 has a side 221 adjacent to the scribe line 3. In some exemplary embodiments, the vertical distance between the side 211 and the side 221 is in the range of 2-5 μm. By designing such a dimensional relationship, it is possible not only to avoid over-etching the first passivation layer in the process of forming the second passivation layer by etching, but also to avoid excessively increasing the size of the semiconductor device.
With further reference to fig. 1 and 2, an orthographic projection of the third passivation layer 23 on the semiconductor substrate 1 may cover an orthographic projection of the second passivation layer 22 on the semiconductor substrate 1, and an area of the orthographic projection of the third passivation layer 23 on the semiconductor substrate 1 is larger than an area of the orthographic projection of the second passivation layer 22 on the semiconductor substrate 1. The utility model discloses an in the embodiment, through above-mentioned mode of setting, at the in-process that the sculpture formed the third passivation layer, the third passivation layer that is located the top can protect the second passivation layer that is located the below, avoids forming the in-process of third passivation layer at the sculpture and excessively etches the second passivation layer.
The third passivation layer 23 has a side 231 adjacent to the scribe line 3. In some exemplary embodiments, the vertical distance between the side 231 and the side 221 is in the range of 5-10 μm. By designing such a dimensional relationship, it is possible not only to avoid over-etching the second passivation layer in the process of forming the third passivation layer by etching, but also to avoid excessively increasing the size of the semiconductor device.
Alternatively, as shown in fig. 1 and 2, the thickness of the third passivation layer 23 may be greater than the thickness of each of the first and second passivation layers 21 and 22. The third passivation layer 23 may also serve a planarization function. Alternatively, the thickness of the first passivation layer 21 may be equal to the thickness of the second passivation layer 22.
For example, a semiconductor device according to embodiments of the present invention may be a silicon carbide (SiC) -based Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Referring further to fig. 1, the semiconductor device may include a field oxide layer 4 and an interlayer dielectric layer 5 disposed between a semiconductor substrate 1 and a passivation film 2.
As shown in fig. 1, a field oxide layer 4 is provided on a semiconductor substrate 1, and an interlayer dielectric layer 4 is provided on a side of the field oxide layer 4 remote from the semiconductor substrate 1.
An orthogonal projection of the passivation film 2 on the semiconductor substrate 1 covers an orthogonal projection of each of the field oxide layer 4 and the interlayer dielectric layer 5 on the semiconductor substrate 1, that is, an orthogonal projection of each of the first passivation layer 21, the second passivation layer 22, and the third passivation layer 23 on the semiconductor substrate 1 covers an orthogonal projection of each of the field oxide layer 4 and the interlayer dielectric layer 5 on the semiconductor substrate 1.
In the embodiment of the utility model, utilize the passivation film of 3 range upon range of layer structures to cover semiconductor device's circuit structure, can utilize the advantage of various passivation layers comprehensively, improve the wholeness ability of passivation film to improve semiconductor device's electrical property and reliability. For example, the 3-layer stacked structure may be an oxide layer (e.g., silicon oxide) + silicon nitride + polyimide stacked structure, the lower layer of silicon oxide has a stress similar to that of the SiC substrate to ensure the stability of the interface, the middle layer of silicon nitride is beneficial to increasing the barrier capability of the passivation film to harmful impurities, water vapor and sodium ions, and the upper layer of polyimide has strong mechanical properties and chemical corrosion resistance, and at the same time, the moisture resistance of the device can be effectively improved.
Although a few embodiments in accordance with the present general inventive concept have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the claims and their equivalents.
Claims (10)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor substrate; and
a passivation film disposed on the semiconductor substrate, the passivation film including a first passivation layer, a second passivation layer, and a third passivation layer,
wherein the first passivation layer is disposed on the semiconductor substrate, the second passivation layer is disposed on a side of the first passivation layer away from the semiconductor substrate, and the third passivation layer is disposed on a side of the second passivation layer away from the semiconductor substrate,
the orthographic projection of the second passivation layer on the semiconductor substrate covers the orthographic projection of the first passivation layer on the semiconductor substrate, and the area of the orthographic projection of the second passivation layer on the semiconductor substrate is larger than that of the orthographic projection of the first passivation layer on the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein an orthographic projection of the third passivation layer on the semiconductor substrate covers an orthographic projection of the second passivation layer on the semiconductor substrate, and an area of the orthographic projection of the third passivation layer on the semiconductor substrate is larger than an area of the orthographic projection of the second passivation layer on the semiconductor substrate.
3. The semiconductor device according to claim 1 or 2, further comprising a scribe line provided on the semiconductor substrate.
4. The semiconductor device according to claim 3, wherein the first passivation layer includes a side surface adjacent to the scribe line, the second passivation layer includes a side surface adjacent to the scribe line, and a vertical distance between the side surface of the second passivation layer and the side surface of the first passivation layer is in a range of 2 to 5 μm.
5. The semiconductor device according to claim 4, wherein the third passivation layer comprises a side surface close to the scribe line, and a vertical distance between the side surface of the third passivation layer and the side surface of the second passivation layer is in a range of 5 to 10 μm.
6. The semiconductor device according to claim 1, 2, 4, or 5, further comprising a field oxide layer and an interlayer dielectric layer provided between the semiconductor substrate and the passivation film, the interlayer dielectric layer being located on a side of the field oxide layer away from the semiconductor substrate.
7. The semiconductor device according to claim 6, wherein an orthographic projection of each of the first passivation layer, the second passivation layer, and the third passivation layer on the semiconductor substrate covers an orthographic projection of each of the field oxide layer and the interlayer dielectric layer on the semiconductor substrate.
8. The semiconductor device according to claim 1, 2, 4, 5 or 7, wherein the first passivation layer is an oxide layer, the second passivation layer is a silicon nitride layer, and the third passivation layer is a polyimide layer.
9. The semiconductor device according to claim 1, 2, 4, 5, or 7, wherein the semiconductor substrate comprises silicon carbide.
10. The semiconductor device according to claim 9, wherein the semiconductor device is a metal oxide semiconductor field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922361703.8U CN210956679U (en) | 2019-12-24 | 2019-12-24 | Semiconductor device with a plurality of transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922361703.8U CN210956679U (en) | 2019-12-24 | 2019-12-24 | Semiconductor device with a plurality of transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210956679U true CN210956679U (en) | 2020-07-07 |
Family
ID=71383129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922361703.8U Expired - Fee Related CN210956679U (en) | 2019-12-24 | 2019-12-24 | Semiconductor device with a plurality of transistors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210956679U (en) |
-
2019
- 2019-12-24 CN CN201922361703.8U patent/CN210956679U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10693019B2 (en) | Film scheme for a high density trench capacitor | |
| US20230238337A1 (en) | Semiconductor device | |
| US20200176552A1 (en) | Cap structure for trench capacitors | |
| US8373254B2 (en) | Structure for reducing integrated circuit corner peeling | |
| CN104733435B (en) | 3DIC interconnection means and method | |
| US7479699B2 (en) | Seal ring structures with unlanded via stacks | |
| US6707156B2 (en) | Semiconductor device with multilevel wiring layers | |
| US8278737B2 (en) | Structure for improving die saw quality | |
| US20090121322A1 (en) | Semiconductor chip and semiconductor device | |
| US10515908B2 (en) | Seal ring for bonded dies | |
| KR20110069064A (en) | Systems and methods for enabling esd protection on 3-d stacked devices | |
| US10892363B2 (en) | Semiconductor device having termination region with insulator films having different coefficients of moisture absorption | |
| JP2011233746A (en) | Semiconductor device and manufacturing method thereof | |
| TW201310536A (en) | Crack stop structure and method for forming the same | |
| US20160233185A1 (en) | Power Semiconductor Device with a Double Metal Contact and Related Method | |
| US9853113B2 (en) | Semiconductor device | |
| US11955441B2 (en) | Interconnect structure and forming method thereof | |
| TW201906093A (en) | Trench structure | |
| CN210956679U (en) | Semiconductor device with a plurality of transistors | |
| US20080017928A1 (en) | Semiconductor Device and Method for Manufacturing the Same | |
| US6780756B1 (en) | Etch back of interconnect dielectrics | |
| US20180277672A1 (en) | Semiconductor structure | |
| TWI762997B (en) | Semiconductor device and method for fabricating the same | |
| US9293410B2 (en) | Semiconductor device | |
| US20230035217A1 (en) | Seal Ring Structure and Method of Fabricating the Same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200707 |