CN210639499U - Asset information management architecture of server system - Google Patents
Asset information management architecture of server system Download PDFInfo
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- CN210639499U CN210639499U CN201921977767.4U CN201921977767U CN210639499U CN 210639499 U CN210639499 U CN 210639499U CN 201921977767 U CN201921977767 U CN 201921977767U CN 210639499 U CN210639499 U CN 210639499U
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- eeprom
- asset information
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- information management
- server system
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Abstract
The utility model discloses a server system asset information management framework, including mainboard and daughter card, be provided with I2C Switch chip and EEPROM chip on the daughter card, the EEPROM chip is connected with I2C Switch chip, and I2C Switch chip passes through I2C bus and mainboard connection. The framework adds the EEPROM on the daughter card, and performs asset information management of each board card and component in the whole system by reading information contained in the EEPROM on an I2C bus, thereby overcoming the defects of constructing and maintaining a data table in software in the prior art and greatly improving the code development efficiency; a more complex system is supported, and the defect that the prior art only supports simple direct connection is overcome; and supports blind-reading of the EEPROM to obtain asset information.
Description
Technical Field
The utility model relates to a server system asset management field, concretely relates to server system asset information management framework.
Background
With the development of cloud computing applications, informatization gradually covers various fields of society. People's daily life and daily life are more and more communicated through the network, and the network data volume is also increasing continuously. For a complex server system, identification and distinction of the board cards are an important subject, and state reading and management, temperature monitoring and the like of the daughter cards need to be premised on board card identification and distinction.
In the existing technical scheme, the identification and the distinguishing of the BOARD cards are realized in a BOARD ID mode, different BOARD IDs are arranged on the daughter cards through pull-up and pull-down resistors, and a small database is built in a BMC code of a mainboard end and used for the corresponding of BOARD ID codes and other related information maintenance. For the main board, each connector capable of connecting the daughter cards needs to define an IDpin, and coding is performed according to the number of the daughter cards. The disadvantages of the prior art solutions are mainly: 1) in a complex system, the number and the types of BOARD cards are too many, a plurality of GPIOs are identified and distinguished by using BOARD ID, and the hardware design is very limited, for example, 8 daughter cards are supported by 3-bit ID at most; 2) a data table is required to be maintained inside the firmware (BMC or PCH) and is used for corresponding the information of the ID and the specific daughter card; 3) and the extended connector of the motherboard corresponding to the BOARD ID is difficult to encode in a complex system in many cases, such as using the connector 1, using the connector 2, and using the connectors 1 and 2 simultaneously.
Disclosure of Invention
In order to solve the problem, the utility model provides a server system asset information management framework adds EEPROM on the daughter card, through read the information that contains in EEPROM on the I2C bus, carries out the asset information management of each integrated circuit board and part in the total system.
The technical scheme of the utility model is that: the utility model provides a server system asset information management framework, includes mainboard and daughter card, is provided with I2C Switch chip and EEPROM chip on the daughter card, and the EEPROM chip is connected with I2C Switch chip, and I2CSwitch chip passes through I2C bus and is connected with the mainboard.
Furthermore, the mainboard is provided with firmware and a connector, and the connector connects the firmware with the I2C Switch chip through I2C bus, so as to realize the connection between the I2C Switch chip and the mainboard.
Further, a golden finger is arranged on the daughter card, and the I2C Switch chip is connected with the connector through the golden finger.
Further, the firmware on the motherboard is BMC or PCH.
Further, an EEPROM chip is connected to the first channel of the I2C Switch chip.
Further, the I2C address of the EEPROM chips on all daughter cards is the same value.
Further, the daughter card is a Riser card.
The utility model provides a server system asset information management framework adds EEPROM on the daughter card, through reading the information that contains in the EEPROM on I2C bus, carries out the asset information management of each integrated circuit board and part in the total system, has improved the shortcoming that builds, maintains the data sheet in software in the prior art scheme, has improved code development efficiency greatly; a more complex system is supported, and the defect that the prior art only supports simple direct connection is overcome; and supports blind-reading of the EEPROM to obtain asset information.
Drawings
Fig. 1 is a schematic diagram of an embodiment of the present invention.
In the figure, 1-mainboard, 2-daughter card, 11-firmware, 12-connector, 21-I2C Switch chip, 22-EEPROM chip, 23-golden finger.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
As shown in fig. 1, the asset information management architecture of the server system provided by this embodiment includes a motherboard 1 and a daughter card 2, an EEPROM chip 22 chip is added on the daughter card 2, and asset information management of each board card and component in the whole system is performed by reading information contained in the EEPROM chip 22 on an I2C bus.
For the design of the I2C architecture, the protocol of the I2C bus is referred to, and address collision is to be avoided for device on the same bus, but for complex server systems, it is not easy to avoid address collision. Generally speaking, the EEPROM chip 22 commonly used at present can have 4 optional addresses, and for a bus in a complex system, these 4 optional addresses are not sufficient, so that address collision is usually avoided by adding the I2C Switch chip 21 in the system. In the prior art, the I2CSwitch chip 21 is usually added on the motherboard 1, and multiple I2C signals extended by the I2C Switch chip 21 are introduced at the end of each daughter card 2, in this architecture, the position of the EEPROM chip 22 chip in the system is not fixed, which has great difficulty for directional reading of software and asset information management.
In the framework of this embodiment, an I2C Switch chip 21 is disposed on the daughter card 2, an EEPROM chip 22 is connected to the I2CSwitch chip 21, and the I2C Switch chip 21 is connected to the motherboard 1 through an I2C bus. It is sufficient that one I2C bus at the motherboard 1 side is used for external expansion. It should be noted that the daughter Card 2 may be a Riser Card.
A gold finger 23 is further provided on the daughter card 2, and the I2C Switch chip 21 is connected to the connector 12 through the gold finger 23.
Specifically, the firmware 11 and the connector 12 are arranged on the motherboard 1, and the connector 12 connects the firmware 11 and the I2CSwitch chip 21 through I2C bus, so as to realize the connection between the I2C Switch chip 21 and the motherboard 1, where it is noted that the estimate on the motherboard 1 is BMC or PCH.
The chip of the EEPROM chip 22 is connected to the first channel of the I2C Switch chip 21, and in addition, in the system, the I2C addresses of the EEPROM chips 22 on all the daughter cards 2 are the same value, so the greatest meaning of the design is to support software blind reading, when the asset information is not obtained, the BMC or the PCH does not know the type of the daughter card 2 in the system, and by blind reading the information in the EEPROM chip 22 with a fixed address on the first channel of the I2C Switch chip 21, the information of the daughter card 2PN, description, slot information, speed, and the like is obtained, and the information can be defined according to the actual design, and the required information is burned into the EEPROM chip 22.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any person skilled in the art can think of the inventive changes, and several improvements and decorations made without departing from the principle of the present invention should fall within the protection scope of the present invention.
Claims (7)
1. The asset information management architecture of the server system comprises a mainboard and a daughter card, and is characterized in that an I2C Switch chip and an EEPROM chip are arranged on the daughter card, the EEPROM chip is connected with the I2C Switch chip, and the I2C Switch chip is connected with the mainboard through an I2C bus.
2. The asset information management architecture of the server system according to claim 1, wherein a firmware and a connector are disposed on the motherboard, and the connector connects the firmware to the I2C Switch chip via I2C bus, so as to connect the I2C Switch chip to the motherboard.
3. The server system asset information management architecture of claim 2, wherein a gold finger is further disposed on the daughter card, and the I2C Switch chip is connected to the connector through the gold finger.
4. The server system asset information management architecture of claim 2 or 3, wherein the firmware on the motherboard is BMC or PCH.
5. The server system asset information management architecture of claim 1, 2 or 3, wherein an EEPROM chip is connected on the first channel of the I2C Switch chip.
6. The server system asset information management architecture of claim 5, wherein the I2C addresses of the EEPROM chips on all daughter cards are the same value.
7. The server system asset information management architecture of claim 1, 2, 3 or 6, wherein the daughter card is a Riser card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921977767.4U CN210639499U (en) | 2019-11-15 | 2019-11-15 | Asset information management architecture of server system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921977767.4U CN210639499U (en) | 2019-11-15 | 2019-11-15 | Asset information management architecture of server system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210639499U true CN210639499U (en) | 2020-05-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921977767.4U Active CN210639499U (en) | 2019-11-15 | 2019-11-15 | Asset information management architecture of server system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210639499U (en) |
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2019
- 2019-11-15 CN CN201921977767.4U patent/CN210639499U/en active Active
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