CN210490817U - Memory comparison circuit device and semiconductor memory - Google Patents
Memory comparison circuit device and semiconductor memory Download PDFInfo
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- CN210490817U CN210490817U CN201921683257.6U CN201921683257U CN210490817U CN 210490817 U CN210490817 U CN 210490817U CN 201921683257 U CN201921683257 U CN 201921683257U CN 210490817 U CN210490817 U CN 210490817U
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Abstract
The application discloses a memory comparison circuit device and a semiconductor memory. The circuit device comprises a latch and a comparator, wherein the latch is used for latching input first input data and outputting first output data and second output data, the first output data is the same as the first input data, and the second output data is different from the first input data; the comparator is used for receiving the second input data, the first output data and the second output data and outputting a comparison result. The unit structure of the latch and the comparator can simplify the device data in the latch and the comparator, reduce the chip area, reduce the calculation amount and improve the data comparison efficiency.
Description
Technical Field
The utility model relates to a semiconductor integrated circuit technical field, concretely relates to storage comparison circuit device and semiconductor memory.
Background
Currently, a common storage comparator includes a latch and an exclusive nor gate. Latches (latches) are level-triggered memory cells, the action of storing data (state transition) depends on the level value of an input clock (or enable) signal, and the output changes with the data input when the latch is in the enable state. One of two input ends of the exclusive-OR gate is used for inputting first data, and the other input end of the exclusive-OR gate is connected with the output end of the latch. The second data may be input into the latch, and the delayed data may be obtained by a delay of the latch. The delayed data is input to the other input end of the exclusive-nor gate. And finally, comparing the first data with the delayed data by an exclusive-nor gate to obtain an output signal. However, in the conventional memory comparator, the internal structure of the latch and the exclusive nor gate is complicated, and the area is too large. When such a circuit unit is used too much, the chip area is too large, which affects the chip cost.
The above information disclosed in the background section is only for enhancement of understanding of the background of the present invention, and therefore it may contain information that does not form the prior art that is known to those of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
The present invention provides a memory compare circuit arrangement and semiconductor memory to overcome or alleviate one or more of the problems of the background art, providing at least one useful choice.
As an aspect of the present invention, there is provided a memory comparison circuit device, including a latch for latching first input data inputted thereto and outputting first output data and second output data, the first output data being the same as the first input data, the second output data being different from the first input data;
the comparator is used for receiving second input data, the first output data and the second output data and outputting a comparison result.
In one embodiment, the latch includes a transmission gate, an inverter, and a tristate gate;
the input end of the transmission gate is used for inputting the first input data, and the output end of the transmission gate is connected to the input end of the inverter; the output end of the inverter is connected to the input end of the tri-state gate, and the output end of the tri-state gate is connected to the output end of the transmission gate; the transmission gate further comprises a transmission gate control end, the tristate gate further comprises a tristate gate control end, the transmission gate control end and the tristate gate control end are used for receiving control signals, the control signals are used for controlling the transmission gate to be conducted and the tristate gate to be closed, the output end of the transmission gate outputs the first output data, the output end of the inverter outputs the second output data, and the output end of the inverter outputs the second output data when the transmission gate is controlled to be closed and the tristate gate is controlled to be conducted;
the comparator comprises a first input end, a second input end and a third input end, wherein the first input end is used for receiving the second input data, the second input end is used for receiving the first output data, the third input end is used for receiving the second output data, and the output end of the comparator is used for outputting the comparison result.
In one embodiment, the transmission gate control terminal includes a first control terminal and a second control terminal, the tri-state gate control terminal includes a third control terminal and a fourth control terminal, the first control terminal and the third control terminal are both connected to the gate of the PMOS transistor, and the second control terminal and the fourth control terminal are both connected to the gate of the NMOS transistor;
the first control end inputs a low level, the second control end inputs a high level to control the transmission gate to be conducted, the third control end inputs a high level, the fourth control end inputs a low level, and the tri-state gate is in a high-impedance state;
the first control end inputs high level, the second control end inputs low level to control the transmission gate to be closed, the third control end inputs low level, the fourth control end inputs high level, and the tri-state gate is conducted.
In one embodiment, the comparator includes a first transistor and a second transistor connected in series, and a third transistor and a fourth transistor connected in parallel;
the grid electrode of the first transistor is connected with the grid electrode of the second transistor to form a first connection point, the source electrode of the third transistor is connected with the source electrode of the fourth transistor to form a second connection point, and the first connection point and the second connection point are connected to the first input end;
the source of the first transistor and the gate of the third transistor are connected to the third input terminal, which is connected to the output terminal of the inverter;
the source of the second transistor and the gate of the fourth transistor are connected to the second input terminal, and the second input terminal is connected to the input terminal of the inverter;
the drain of the first transistor and the drain of the second transistor are connected to form a third connection point, the drain of the third transistor and the drain of the fourth transistor are connected to form a fourth connection point, and the third connection point and the fourth connection point are connected to the output end of the comparator.
In a second aspect, there is provided a semiconductor memory comprising a circuit arrangement as claimed in any one of the preceding claims.
The utility model adopts the above technical scheme, have following advantage: the unit structure of the latch and the comparator can simplify device data in the latch and the comparator, reduce chip area, reduce calculation amount and improve data comparison efficiency.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope. The drawings are included to provide a better understanding of the present solution and are not intended to limit the present application. Wherein:
fig. 1 is a schematic structural diagram of a memory comparison circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an internal structure of a latch and a comparator provided in an embodiment of the present application;
fig. 3 is a data storage comparison method according to an embodiment of the present application.
Description of reference numerals:
a latch 10;
the transmission gate 110, the input end 111 of the transmission gate, the output end 114 of the transmission gate, the control end 112 of the transmission gate, the first control end 113 and the second control end 114;
inverter 120, inverter input 121, inverter output 122;
a tri-state gate 130, an input terminal 131 of the tri-state gate, an output terminal 132 of the tri-state gate, a control terminal 133 of the tri-state gate, a third control terminal 134, and a fourth control terminal 135;
a comparator 20;
a first input 201, a second input 202, a third input 203, an output 204 of the comparator;
a first transistor 210, a second transistor 220, a third transistor 230, and a fourth transistor 240.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed. In addition, the present disclosure provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Example one
In one embodiment, a storage comparison circuit device is provided, as shown in fig. 1, a storage comparison circuit device 1 includes a latch 10 and a comparator 20, the latch 10 is used for latching a first input data inputted thereto, and outputting a first output data and a second output data, the first output data is the same as the first input data, and the second output data is different from the first input data; the comparator 20 is configured to receive the second input data, the first output data, and the second output data, and output a comparison result. A Latch (Latch) is a pulse level sensitive circuit of memory cells that can change state under a specific input pulse level. Latching is the temporary storage of signals to maintain a certain level state. The most important role of the latch is buffering. The comparator compares two or more data items to determine whether they are equal or to determine the magnitude relationship and the order of arrangement between them is called comparison. A circuit or device capable of performing such a comparison function is called a comparator. A comparator is a circuit that compares an analog voltage signal with a reference voltage.
In one embodiment, as shown in FIG. 2, latch 10 includes a transmission gate 110, an inverter 120, and a tristate gate 130. The internal connection of the latch 10 includes: the input 111 of the transmission gate is used for inputting the first input data D1, and the output 114 of the transmission gate is connected to the input 121 of the inverter; the output 122 of the inverter is connected to the input 131 of the tristate gate, the output 132 of the tristate gate is connected to the output 114 of the transmission gate; the transmission gate 110 further includes a transmission gate control terminal 112, the tristate gate 130 further includes a tristate gate control terminal 133, the transmission gate control terminal 112 and the tristate gate control terminal 133 are configured to receive a control signal, the control signal is configured to control the transmission gate 110 to be turned on and the tristate gate 130 to be turned off, the output terminal 114 of the transmission gate outputs the first output data Q, the output terminal 122 of the inverter outputs the second output data QF, and the output terminal 122 of the inverter outputs the second output data QF when the transmission gate 110 is turned off and the tristate gate 130 is turned on.
The comparator 20 comprises a first input 201, a second input 202 and a third input 203, the first input 201 is configured to receive the second input data D0, the second input 202 is configured to receive the first output data Q, the third input 203 is configured to receive the second output data QF, and the output 204 of the comparator is configured to output the comparison result.
In an example, when the transmission gate 10 is controlled by the control signal to be turned on and the tri-state gate 130 is in a high impedance state, the first input data D1 inputted into the transmission gate 10 may be logic signal 1, and the first output data Q obtained after the first input data D1 passes through the transmission gate 110 is logic signal 1. After the first output data Q passes through the inverter 120, the obtained second output data QF is the logic signal 0. It is noted that the first output data Q and the second output data QF can represent the first input data D1. The first input terminal 201 of the comparator 20 receives the second input data D0, and the second input data D0 may be a logic signal 0 or a logic signal 1. The first output data Q of the logic signal 1 are input to the second input 202 of the comparator 20, and the second output data QF of the logic signal 0 are input to the third input 203 of the comparator 20.
When the second input data D0 is logic signal 0, the first output data Q is logic signal 1, and the second output data QF is logic signal 0, the comparison result output by the output terminal 204 of the comparator is logic signal 0. Since the first output data Q can represent the same data information as the first input data D1, and the second output data QF can represent data information different from the first input data D1, the comparison result indicates that the first input data D1 with logic signal 1 is different from the second input data D0 with logic signal 0, and the output comparison result is 0.
When the second input data D0 is logic signal 1, the first output data Q is logic signal 1, and the second output data QF is logic signal 0, the comparison result output by the output terminal 204 of the comparator is logic signal 1. Since the first output data Q can represent the same data information as the first input data D1, and the second output data QF can represent different data information as the first input data D1, the comparison result indicates that the first input data D1 of logic signal 1 is the same as the second input data D0 of logic signal 1, and the output comparison result is 1.
When the control signal controls the transmission gate 10 to close and the tri-state gate 130 is turned on, the first input data D1 input into the transmission gate 10 cannot enter the transmission gate no matter how it changes, at this time, the tri-state gate 130 is turned on, so that the second output data QF returns to the input of the tri-state gate 120, the first output data Q is obtained from the output of the tri-state gate 120, and the latch is formed for the first input data D1 input before the transmission gate 10 closes. At this time, please refer to the foregoing process for the comparison result output from the comparator 120, which is not described herein again. The unit structure of the latch adopted by the embodiment can simplify the device data in the latch, reduce the chip area, reduce the calculation amount and ensure the latch effect of the input data.
In one embodiment, in the latch 10, the transmission gate control terminal 112 includes a first control terminal 113 and a second control terminal 114, and the tri-state gate control terminal 133 includes a third control terminal 134 and a fourth control terminal 135; the first control end 113 and the third control end 134 are both connected to the gate of the PMOS transistor, and the second control end 114 and the fourth control end 135 are both connected to the gate of the NMOS transistor; the first control terminal 113 inputs a low level, the second control terminal 114 inputs a high level, the transmission gate 110 is controlled to be turned on, the third control terminal 134 inputs a high level, the fourth control terminal 135 inputs a low level, and the tri-state gate 130 is in a high impedance state; the first control terminal 113 inputs a high level, the second control terminal 114 inputs a low level, the transmission gate 110 is controlled to be closed, the third control terminal 134 inputs a low level, the fourth control terminal 135 inputs a high level, and the tri-state gate 130 is turned on.
In one example, the NMOS is turned on with the gate high and off with the gate low, which can be used to control the conduction to ground. The PMOS is switched on at a low level and off at a high level, and can be used for controlling the conduction with the power supply. The access control signal controls the switching of the transmission gate 10 and the tri-state gate 130 to achieve the latching of the first input data D1 according to the foregoing principle.
In one embodiment, the comparator 20 includes a first transistor 210 and a second transistor 220 in series, and a third transistor 230 and a fourth transistor 240 in parallel. The gate of the first transistor 210 is connected to the gate of the second transistor 220 to form a first connection point a, the source of the third transistor 230 is connected to the source of the fourth transistor 240 to form a second connection point B, and the first connection point a and the second connection point B are connected to the first input terminal 201; the source of the first transistor 210 and the gate of the third transistor 230 are connected to the third input terminal 203, and the third input terminal 203 is connected to the output terminal 122 of the inverter; the source of the second transistor 220 and the gate of the fourth transistor 240 are coupled to the second input 202, the second input 202 being coupled to the input 115 of the inverter;
the drain of the first transistor 210 and the drain of the second transistor 220 are connected to a third connection point C, the drain of the third transistor 230 and the drain of the fourth transistor 240 are connected to a fourth connection point D, and the third connection point C and the fourth connection point D are connected to the output terminal 204 of the comparator.
The cell structure of the comparator according to this embodiment can simplify the device data in the comparator, reduce the chip area, and reduce the amount of calculation, thereby ensuring the latch effect of the first input data D1 and the second input data D0.
Example two
In another embodiment, a semiconductor memory is provided, comprising a circuit arrangement as claimed in any one of the above.
EXAMPLE III
In a specific implementation manner, a data storage comparison method is provided, as shown in fig. 3, and is applied to the circuit device in the first embodiment, the method includes:
step S10: under the condition that the transmission gate 110 in the latch 10 is controlled to be turned on according to the control signal and the tristate gate 130 is turned off, the first input data D1 is input to the transmission gate 110 to output the first output data Q, the first output data Q is input to the inverter 120 to output the second output data QF; or
Step S20: under the condition that the transmission gate 110 is controlled to be closed according to the control signal and the tri-state gate 130 is turned on, the second output data QF is input to the tri-state gate 130, and the first output data Q is output;
step S30: the second input data D0, the first output data Q, and the second output data QF are input to the comparator, and the comparison result is output.
In one embodiment, step S30 includes:
step S301: under the condition that the second input data is the same as the first output data, the output comparison result is a logic signal 1;
step S302: in the case where the second input data is the same as the second output data, the output comparison result is a logic signal 0.
The utility model adopts the above technical scheme, have following advantage: the unit structure of the latch and the comparator can simplify device data in the latch and the comparator, reduce chip area, reduce calculation amount and improve data comparison efficiency.
The above-described embodiments should not be construed as limiting the scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (5)
1. A memory compare circuit arrangement, said circuit arrangement comprising a latch and a comparator,
the latch is used for latching input first input data and outputting first output data and second output data, wherein the first output data is the same as the first input data, and the second output data is different from the first input data;
the comparator is used for receiving second input data, the first output data and the second output data and outputting a comparison result.
2. The circuit arrangement of claim 1, wherein the latch comprises a transmission gate, an inverter, and a tristate gate;
the input end of the transmission gate is used for inputting the first input data, and the output end of the transmission gate is connected to the input end of the inverter; the output end of the inverter is connected to the input end of the tri-state gate, and the output end of the tri-state gate is connected to the output end of the transmission gate; the transmission gate further comprises a transmission gate control end, the tristate gate further comprises a tristate gate control end, the transmission gate control end and the tristate gate control end are used for receiving control signals, the control signals are used for controlling the transmission gate to be conducted and the tristate gate to be closed, the output end of the transmission gate outputs the first output data, the output end of the inverter outputs the second output data, and the output end of the inverter outputs the second output data when the transmission gate is controlled to be closed and the tristate gate is controlled to be conducted;
the comparator comprises a first input end, a second input end and a third input end, wherein the first input end is used for receiving the second input data, the second input end is used for receiving the first output data, the third input end is used for receiving the second output data, and the output end of the comparator is used for outputting the comparison result.
3. The circuit device of claim 2, wherein the transmission gate control terminal comprises a first control terminal and a second control terminal, the tri-state gate control terminal comprises a third control terminal and a fourth control terminal, the first control terminal and the third control terminal are both connected to the gate of the PMOS transistor, and the second control terminal and the fourth control terminal are both connected to the gate of the NMOS transistor;
the first control end inputs a low level, the second control end inputs a high level to control the transmission gate to be conducted, the third control end inputs a high level, the fourth control end inputs a low level, and the tri-state gate is in a high-impedance state;
the first control end inputs high level, the second control end inputs low level to control the transmission gate to be closed, the third control end inputs low level, the fourth control end inputs high level, and the tri-state gate is conducted.
4. The circuit arrangement of claim 2, wherein the comparator comprises a first transistor and a second transistor in series, and a third transistor and a fourth transistor in parallel;
the grid electrode of the first transistor is connected with the grid electrode of the second transistor to form a first connection point, the source electrode of the third transistor is connected with the source electrode of the fourth transistor to form a second connection point, and the first connection point and the second connection point are connected to the first input end;
the source of the first transistor and the gate of the third transistor are connected to the third input terminal, which is connected to the output terminal of the inverter;
the source of the second transistor and the gate of the fourth transistor are connected to the second input terminal, and the second input terminal is connected to the input terminal of the inverter;
the drain of the first transistor and the drain of the second transistor are connected to form a third connection point, the drain of the third transistor and the drain of the fourth transistor are connected to form a fourth connection point, and the third connection point and the fourth connection point are connected to the output end of the comparator.
5. A semiconductor memory comprising the circuit arrangement as claimed in any of claims 1 to 4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021068551A1 (en) * | 2019-10-08 | 2021-04-15 | 长鑫存储技术有限公司 | Data storage and comparison method, storage and comparison circuit apparatus, and semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021068551A1 (en) * | 2019-10-08 | 2021-04-15 | 长鑫存储技术有限公司 | Data storage and comparison method, storage and comparison circuit apparatus, and semiconductor memory |
| US11632100B2 (en) | 2019-10-08 | 2023-04-18 | Changxin Memory Technologies, Inc. | Method for data storage and comparison, storage comparison circuit device, and semiconductor memory |
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