CN210156381U - Power semiconductor device with cut-off ring structure - Google Patents
Power semiconductor device with cut-off ring structure Download PDFInfo
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- CN210156381U CN210156381U CN201921417313.1U CN201921417313U CN210156381U CN 210156381 U CN210156381 U CN 210156381U CN 201921417313 U CN201921417313 U CN 201921417313U CN 210156381 U CN210156381 U CN 210156381U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 89
- 239000002184 metal Substances 0.000 claims abstract description 56
- 210000000746 body region Anatomy 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000001413 cellular effect Effects 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims description 72
- 238000010586 diagram Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
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Abstract
The utility model relates to the technical field of semiconductors, in particular to a power semiconductor device with a stop ring structure, which comprises a semiconductor substrate, a cellular area is positioned in the central area of the semiconductor substrate, and a terminal protection area is positioned at the outer ring of the cellular area and is arranged around the cellular area; a stop ring structure is arranged in the second conductive type body region of the terminal protection region and surrounds the periphery of the second type groove; the stop ring structure comprises a third groove and stop ring metal, conductive polycrystalline silicon is arranged on the side wall of the third groove, insulating medium layers are filled in the bottom wall and the inside of the third groove, the stop ring metal is located above the third groove, and the stop ring metal can be respectively contacted with the conductive polycrystalline silicon on the side wall of the third groove and the first conductive type epitaxial layer. The utility model provides a power semiconductor ware with stop ring structure can prevent the device electric leakage.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a power semiconductor device with stop ring structure.
Background
Fig. 1 is a schematic structural diagram of a conventional trench MOSFET structure. As shown in fig. 1, the trench MOSFET structure includes a cell region located in a central region of the device and a terminal protection region in which a cutoff ring structure is disposed. The stop ring shown in fig. 1 is formed by a fourth type trench 16, for example, an N-type device, the fourth type trench 16 is covered by an insulating medium layer on the surface of the P-type body region, and the bottom of the trench enters the N-type epitaxial layer and surrounds the second type trench 5. A through hole is formed in the insulating medium layer above the fourth trench 16, and the through hole enters the conductive polysilicon from the surface of the insulating medium layer, and a through hole is formed in one side of the fourth trench 16, which is far away from the cellular region, and the through hole enters the P-type body region from the surface of the insulating medium layer. A stop ring metal 12 is arranged above the fourth type groove, and the stop ring metal 12 fills the fourth type groove 16 and the through hole on the side far away from the cellular area. In the actual production process, when the depth of the trench becomes shallow, a severe leakage phenomenon occurs during the voltage resistance of the device, through simulation verification, as shown in fig. 2, the potential distribution diagram is shown during the voltage resistance of the conventional trench MOSFET structure, when the device is resistant to voltage, the electric field is not completely cut off by the cut-off ring, so that the leakage of the device is caused, and through research, it is found that the drain potential on the conductive polysilicon in the fourth type trench 16 cannot be caused because the cut-off ring metal 12 in the via hole at the side of the fourth type trench 16 far from the cellular region in the conventional trench MOSFET is in contact with the P-type body region, and actually, the potential of the conductive polysilicon in the fourth type trench 16 is always lower than the drain potential.
Disclosure of Invention
The utility model provides a power semiconductor device with stop ring structure solves the electric leakage problem of the slot that exists among the correlation technique.
As an aspect of the present invention, there is provided a power semiconductor device having a cutoff ring structure, including a semiconductor substrate, the semiconductor substrate being divided into a cell region and a terminal protection region, the cell region being located in a central region of the semiconductor substrate, the terminal protection region being located at an outer ring of the cell region and being disposed around the cell region, wherein the semiconductor substrate includes a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate, a surface of the first conductive type epitaxial layer being provided with a second conductive type region;
a first-type groove is arranged in the second conductive type body region of the cellular region, and the bottom of the first-type groove extends into the first-type conductive type epitaxial layer;
at least one second-type groove is formed in the second conductive type body region of the terminal protection region and close to the cellular region;
a cut-off ring structure is arranged in the second conductive type body region of the terminal protection region and surrounds the periphery of the second type groove;
the stop ring structure comprises a third groove and stop ring metal, the bottom of the third groove extends into the first conductive type epitaxial layer, the third groove surrounds the second groove, conductive polycrystalline silicon is arranged on the side wall of the third groove, insulating medium layers are filled in the bottom wall and the inner part of the third groove, the stop ring metal is located above the third groove, and the stop ring metal can be respectively contacted with the conductive polycrystalline silicon on the side wall of the third groove and the first conductive type epitaxial layer at the bottom of the third groove.
Furthermore, the surfaces of the second conductive type body regions in the cell region and the terminal protection region are both provided with insulating medium layers, the third type trench is covered by the insulating medium layers, gate oxide layers are formed on the side wall and the bottom wall of the third type trench, the third type trench is close to the side wall of the second type trench and is provided with first type conductive polysilicon on the surface of the gate oxide layer, the third type trench is far away from the side wall of the second type trench and is provided with second type conductive polysilicon on the surface of the gate oxide layer, a first through hole is arranged in the insulating medium layer above the first type conductive polysilicon, a second through hole is arranged in the insulating medium layer in the third type trench, and one end of the stop ring metal is filled in the first through hole and is in contact with the first type conductive polysilicon, and the other end of the stop ring metal fills the second through hole and is in contact with the first conductive type epitaxial layer.
Further, the second type of conductive polysilicon is arranged in a floating manner.
Furthermore, the surfaces of the second conductive type body regions in the cell region and the terminal protection region are both provided with insulating medium layers, the third type groove is covered by the insulating medium layers, gate oxide layers are formed on the side wall and the bottom wall of the third type groove, the third type groove is close to the side wall of the second type groove and is provided with first type conductive polysilicon on the surface of the gate oxide layer, the third type groove is far away from the side wall of the second type groove and is provided with second type conductive polysilicon on the surface of the gate oxide layer, a first through hole is arranged in the insulating medium layer above the first type conductive polysilicon, a second through hole is arranged in the insulating medium layer in the third type groove, a third through hole is arranged in the insulating medium layer above the second type conductive polysilicon, one end of the stop ring metal is filled in the first through hole and is in contact with the first type conductive polysilicon, the other end of the stop ring metal is filled in the third through hole and is in contact with the second type of conductive polysilicon, and the central area of the stop ring metal is filled in the second through hole and is in contact with the first type of conductive epitaxial layer.
Further, gate oxide layers are formed on the bottom walls and the side walls of the first type of groove and the second type of groove, conductive polycrystalline silicon is arranged in the first type of groove and the second type of groove, the conductive polycrystalline silicon in the first type of groove is connected with a grid potential, and the conductive polycrystalline silicon in the second type of groove is arranged in a floating mode.
Further, a first conductive type source region is arranged on the surface of the second conductive type body region of the cell region, a source metal is arranged on the surface of the insulating medium layer of the cell region, a gate bus metal is arranged on the surface of the insulating medium layer of the terminal protection region, and the source metal is in contact with the second conductive type body region and the first conductive type source region through a fourth through hole in the insulating medium layer.
Furthermore, three second-type grooves are arranged in the second conductive type body region of the terminal protection region.
Further, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
According to the power semiconductor device with the cut-off ring structure, the third type of groove is arranged in the cut-off ring structure, and the cut-off ring metal in the third type of groove can enter the first conduction type epitaxial layer, so that the potential of the conduction polycrystalline silicon in the third type of groove is completely the same as the potential of the drain electrode, the expansion of a depletion layer to the outside of a chip is blocked, the cut-off capability of the power semiconductor device can be improved, and the leakage of the device is prevented.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a trench MOSFET structure in the prior art.
Fig. 2 is a graph showing a potential distribution when a trench MOSFET structure in the related art is resistant to voltage.
Fig. 3 is a top view of a power semiconductor device according to the present invention.
Fig. 4 is a schematic structural view of the first embodiment taken along the broken line AA' of fig. 3.
Fig. 5 is a schematic structural view of a second embodiment taken along the dashed line AA' of fig. 3.
Fig. 6 is a potential distribution diagram at the time of withstand voltage of the power semiconductor device having a cutoff ring structure shown in fig. 4.
Fig. 7 is a potential distribution diagram at the time of withstand voltage of the power semiconductor device having a cutoff ring structure shown in fig. 5.
Fig. 8 is a schematic structural diagram of the epitaxial layer formation provided by the present invention.
Fig. 9 is a schematic structural diagram of forming the first type groove, the second type groove and the third type groove according to the present invention.
Fig. 10 is a schematic structural diagram of forming a gate oxide layer according to the present invention.
Fig. 11 is a schematic structural diagram of the deposited conductive polysilicon layer according to the present invention.
Fig. 12 is a schematic structural diagram of the insulating medium layer formed in the third type of trench after etching the conductive polysilicon according to the present invention.
Fig. 13 is a schematic structural diagram of the formation of the second conductive type body region and the first conductive type source region according to the present invention.
Fig. 14 is a schematic structural diagram of forming an insulating dielectric layer and a through hole according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances for purposes of describing the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the present embodiment, a power semiconductor device with a cut-off ring structure is provided, and fig. 3 to 5 are schematic structural diagrams of a power semiconductor device with a cut-off ring structure according to an embodiment of the present invention, as shown in fig. 3 to 5, including:
the semiconductor substrate is divided into a cell area 01 and a terminal protection area 02, the cell area 01 is located in the central area of the semiconductor substrate, the terminal protection area 02 is located on the outer ring of the cell area 01 and is arranged around the cell area 01, the semiconductor substrate comprises a first conduction type substrate 1 and a first conduction type epitaxial layer 2 located on the first conduction type substrate 1, and a second conduction type body area 3 is arranged on the surface of the first conduction type epitaxial layer 2;
a first-type groove 4 is arranged in the second conductive type body region 3 of the cellular region 01, and the bottom of the first-type groove 4 extends into the first-type conductive type epitaxial layer 2;
at least one second-type trench 5 is arranged in the second conductive type body region 3 of the terminal protection region 02 and close to the cellular region 01;
a stop ring structure is arranged in the second conductive type body region 3 of the terminal protection region 02 and surrounds the periphery of the second type groove 5;
the stop ring structure comprises a third type groove 13 and a stop ring metal 12, the bottom of the third type groove 13 extends into the first conductive type epitaxial layer 2, the third type groove 13 is arranged around the second type groove 5, conductive polycrystalline silicon is arranged on the side wall of the third type groove 13, insulating medium layers 9 are filled in the bottom wall and the inner part of the third type groove 13, the stop ring metal 12 is positioned above the third type groove 13, and the stop ring metal 12 can be respectively contacted with the conductive polycrystalline silicon on the side wall of the third type groove 13 and the first conductive type epitaxial layer 2 at the bottom of the third type groove 13.
According to the power semiconductor device with the cut-off ring structure, the third type of groove is arranged in the cut-off ring structure, and the cut-off ring metal in the third type of groove can enter the first conduction type epitaxial layer, so that the potential of the conduction polycrystalline silicon in the third type of groove is completely the same as the potential of the drain electrode, the expansion of a depletion layer to the outside of a chip is blocked, the cut-off capability of the power semiconductor device can be improved, and the leakage of the device is prevented.
Fig. 4 and 5 are schematic structural views of two embodiments, each taken along a broken line AA' in fig. 3, as shown in fig. 3, which is a top view of the power semiconductor device.
As a specific implementation manner, as shown in fig. 4, an insulating medium layer 9 is disposed on the surfaces of the cell region 01 and the second conductive type body region 3 of the terminal protection region 02, the third type trench 13 is covered by the insulating medium layer 9, gate oxide layers are formed on the sidewalls and the bottom walls of the third type trench 13, a first type conductive polysilicon 14 is disposed on the sidewall of the third type trench 13 close to the second type trench 5 and on the surface of the gate oxide layer 6, a second type conductive polysilicon 15 is disposed on the surface of the gate oxide layer 6 and the sidewall of the third type trench 13 far from the second type trench 5, a first through hole 17 is disposed in the insulating medium layer 9 above the first type conductive polysilicon 14, a second through hole 18 is disposed in the insulating medium layer 9 in the third type trench 13, one end of the stop ring metal 12 fills the first via hole 17 and contacts the first conductive polysilicon 14, and the other end of the stop ring metal 12 fills the second via hole 18 and contacts the first conductive epitaxial layer 2.
In this embodiment, the second type of conductive polysilicon 15 is provided in a floating arrangement.
It should be understood that "floating set" here means not connecting any potential, i.e. the second type of conductive polysilicon is not connected to any potential.
As another specific implementation manner, as shown in fig. 5, an insulating medium layer 9 is disposed on the surfaces of the cell region 01 and the second conductive type body region 3 of the terminal protection region 02, the third type trench 13 is covered by the insulating medium layer 9, gate oxide layers 6 are formed on the sidewalls and the bottom walls of the third type trench 13, a first type conductive polysilicon 14 is disposed on the sidewall of the third type trench 13 close to the second type trench 5 and on the surface of the gate oxide layer 6, a second type conductive polysilicon 15 is disposed on the surface of the gate oxide layer 6, the insulating medium layer above the first type conductive polysilicon 14 is disposed with a first through hole 17, the insulating medium layer 9 in the third type trench 13 is disposed with a second through hole 18, a third through hole 19 is formed in the insulating medium layer 9 above the second type of conductive polysilicon 15, one end of the stop ring metal 12 fills the first through hole 17 and contacts with the first type of conductive polysilicon 14, the other end of the stop ring metal 12 fills the third through hole 19 and contacts with the second type of conductive polysilicon 15, and the central area of the stop ring metal 12 fills the second through hole 18 and contacts with the first conductive type epitaxial layer 2.
Specifically, gate oxide layers 6 are formed on the bottom walls and the side walls of the first type of groove 4 and the second type of groove 5, conductive polysilicon 7 is arranged in the first type of groove 4 and the second type of groove 5, the conductive polysilicon in the first type of groove 4 is connected with a gate potential, and the conductive polysilicon in the second type of groove 5 is arranged in a floating manner.
It should be understood that "floating set" here means that no potential is connected, i.e. the conductive polysilicon in the trenches 5 of the second type is not connected to any potential.
Specifically, a first conductive type source region 8 is disposed on the surface of the second conductive type body region 3 in the cell region 01, a source metal 10 is disposed on the surface of the insulating dielectric layer 9 in the cell region 01, a gate bus metal 11 is disposed on the surface of the insulating dielectric layer 9 in the terminal protection region 02, and the source metal 10 contacts the second conductive type body region 3 and the first conductive type source region 8 through a fourth via 20 in the insulating dielectric layer 9.
It should be understood that the fourth through holes 20 include the fourth through hole 20 located in the cell region 01 and the fourth through hole 20 located in the terminal protection region 02.
As can be seen from fig. 4 or 5, the source metal 10 located in the cell region 01 contacts the first conductive type source region 8 through the fourth via 20 located in the cell region 01; the source metal 10 located in the terminal protection region 02 is in contact with the second conductive type body region through a fourth via 20 located in the terminal protection region 02.
Specifically, three second-type trenches 5 are disposed in the second conductivity-type body region 3 of the terminal protection region 02.
It should be understood that the number of the second-type trenches 5 arranged in the second-conductivity-type body region 3 may be set according to requirements, and is not limited herein, and fig. 4 and 5 are only schematic representations.
Preferably, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device, when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
In the present embodiment, the power semiconductor device is an N-type power semiconductor device, for example.
The structure of the power semiconductor device having a cutoff ring structure provided in the present embodiment is explained below in its entirety with reference to fig. 4 and 5.
A first embodiment, as shown in fig. 4, takes an N-type power device as an example, and provides a power semiconductor device with a stop ring structure, which includes a cell area 01 and a terminal protection area 02, where the cell area 01 is located in a central area of the device, the terminal protection area 02 surrounds the cell area 01, the cell area 01 includes a plurality of cell units, the cell units include a semiconductor substrate, the semiconductor substrate includes an N-type substrate 1 and an N-type epitaxial layer 2 located on the N-type substrate 1, a P-type body area 3 is disposed on a surface of the N-type epitaxial layer 2, a first type trench 4 is disposed on a surface of the P-type body area 3, a gate oxide layer 6 and a conductive polysilicon layer 7 are disposed in the first type trench 4, a bottom of the first type trench 4 enters the N-type epitaxial layer 2, an N-type source region 8 is disposed on a surface of the P-type body area 3, an insulating medium layer 9 covers a surface of the cell area 01, the source metal 10 is contacted with a P-type body region 3 and an N-type source region 8 through a through hole on the insulating medium layer 9, the terminal protection region 02 comprises a semiconductor substrate, the semiconductor substrate comprises an N-type substrate 1 and an N-type epitaxial layer 2 positioned on the N-type substrate 1, the P-type body region 3 is arranged on the surface of the N-type epitaxial layer 2, at least one second-type groove 5 which is parallel to each other is arranged in the P-type body region 3, a gate oxide layer 6 and conductive polycrystalline silicon 7 are arranged in the second-type groove 5, the insulating medium layer 9 covers the upper portion of the second-type groove 5 and the upper portion of the P-type body region 3, and a gate bus metal 11 is arranged above the insulating medium layer 9: a stop ring structure is arranged at the outermost periphery of the device, namely at one side of the second type groove 5 far away from the cellular area 01, the stop ring is composed of a third type groove 13, the surface of the third type groove 13, which is positioned at the P type body area 3, is covered by an insulating medium layer 9, the bottom of the groove enters the N type epitaxial layer 2, the third type groove 13 surrounds the second type groove 5, the surface of the third type groove 13 is provided with a gate oxide layer 6, the side wall of the third type groove 13 is provided with conductive polysilicon, the conductive polysilicon at one side of the third type groove 13, which is close to the cellular area, is first conductive polysilicon 14, the conductive polysilicon at one side of the third type groove 13, which is far away from the cellular area, is second conductive polysilicon 15, the bottom of the groove at the central part of the third type groove 13 is not provided with conductive polysilicon 7 and is filled with the insulating medium layer 9, a through hole is arranged above the first conductive polysilicon 14, a through hole is arranged in the insulating medium layer 9 in the third groove 13, the through hole enters the N-type epitaxial layer from the surface of the insulating medium layer 9, a stop ring metal 12 is arranged above the third groove 13, and the through hole in the third groove 13 and the through hole above the first conductive polysilicon 14 are filled with the stop ring metal.
A second embodiment, which is different from the first embodiment in that a stop ring structure is provided at the outermost periphery of the device, that is, at the side of the second type trench 5 far from the cell region 01, as shown in fig. 5, the stop ring structure is formed by a third type trench 13, the third type trench 13 is located at the surface of the P type body region 3 and covered by the insulating medium layer 9, and the bottom of the trench enters the N type epitaxial layer 2, the third type trench 13 surrounds the second type trench 5, the surface of the third type trench 13 is provided with a gate oxide layer 6, the sidewall of the third type trench 13 is provided with conductive polysilicon, the conductive polysilicon at the side near the cell region in the third type trench 13 is first conductive polysilicon 14, the conductive polysilicon at the side far from the cell region in the third type trench 13 is second conductive polysilicon 15, the bottom of the groove in the central part of the third type groove 13 is not provided with the conductive polysilicon 7 and is filled with the insulating medium layer 9, a through hole is arranged above the first conductive polysilicon 14, a through hole is arranged above the second conductive polysilicon 15, a through hole is arranged in the insulating medium layer 9 in the third type groove 13, the through hole enters the N-type epitaxial layer from the surface of the insulating medium layer 9, a stop ring metal 12 is arranged above the third type groove 13, and the through hole in the third type groove 13, the through hole above the first conductive polysilicon 14 and the through hole above the second conductive polysilicon 15 are filled with the stop ring metal.
As shown in fig. 6 and 7, for the potential distribution diagram of the power semiconductor device in the withstand voltage corresponding to the two embodiments of the present embodiment, when the withstand voltage is performed, since the stop ring metal in the third type of trench enters into the N-type epitaxial layer, the potential of the conductive polysilicon in the third type of trench is completely the same as the drain potential, and therefore the stop effect of the present embodiment is better than that of the conventional stop ring.
In another embodiment of the present invention, there is provided a method for manufacturing a power semiconductor device having a cutoff ring structure, wherein as shown in fig. 8 to 14, the method for manufacturing a power semiconductor device having a cutoff ring structure includes:
as shown in fig. 8, a first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is grown on the first conductivity type substrate 1;
as shown in fig. 9, trenches are selectively etched on the first conductivity type epitaxial layer 2 to form a first type trench 4, a second type trench 5, and a third type trench 13;
as shown in fig. 10, the gate oxide layer 6 is thermally grown;
as shown in fig. 11, depositing the conductive polysilicon 7, and etching to form the conductive polysilicon 7 in the first-type trenches 4 and the second-type trenches 5 and to form the conductive polysilicon on the sidewalls of the third-type trenches 13;
as shown in fig. 12, depositing an insulating dielectric layer 9, filling the third-type trench 13, etching the insulating dielectric layer 9, and retaining the insulating dielectric layer 9 in the third-type trench 13;
as shown in fig. 13, second conductivity type impurities are implanted and thermally annealed to form a second conductivity type body region 3;
as shown in fig. 14, first conductivity type impurities are selectively implanted and activated to form a first conductivity type source region 8;
as shown in fig. 4 and 5, depositing an insulating dielectric layer 9, then selectively etching a through hole on the insulating dielectric layer 9, and injecting a second conductive type impurity;
as shown in fig. 4 and 5, a metal is deposited and selectively etched to form a source metal 10, a gate bus metal 11, and a stopper ring metal 12.
According to the power semiconductor device with the cut-off ring structure, which is manufactured by the manufacturing method of the power semiconductor device with the cut-off ring structure, the third type of groove is arranged in the cut-off ring structure, and the cut-off ring metal in the third type of groove can enter the first conduction type epitaxial layer, so that the potential of the conductive polycrystalline silicon in the third type of groove is completely the same as the potential of the drain electrode, the expansion of a depletion layer to the outside of a chip is blocked, the cut-off capability of the power semiconductor device can be improved, and the leakage of the device is prevented. In addition, the manufacturing method of the power semiconductor device with the cut-off ring structure provided by the embodiment is compatible with the existing process, and the cut-off ring structure is arranged in the same position as the prior art, so that the chip area is not increased, and the cost is not increased.
It should be understood that the above-mentioned method for manufacturing a power semiconductor device having a cutoff ring structure corresponds to the method for manufacturing a power semiconductor device having a cutoff ring structure shown in fig. 4, and the method for manufacturing a power semiconductor device having a cutoff ring structure shown in fig. 5 may refer to the method for manufacturing a structure shown in fig. 4, except for forming a via hole and filling a cutoff ring metal.
It should be noted that the schematic structural diagrams shown in fig. 4 to 13 are all illustrated by taking an N-type power device as an example, where the first conductivity type is an N-type, and the second conductivity type is a P-type.
Specifically, the forming of the conductive polysilicon on the sidewall of the third type trench 13 includes forming a first type conductive polysilicon 14 and forming a second type conductive polysilicon 15, where the first type conductive polysilicon 14 is located on the sidewall of the third type trench 13 close to the second type trench 5, and the second type conductive polysilicon 15 is located on the sidewall of the third type trench 13 far from the second type trench 5.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A power semiconductor device with a cut-off ring structure comprises a semiconductor substrate, wherein the semiconductor substrate is divided into a cell area and a terminal protection area, the cell area is located in the center area of the semiconductor substrate, the terminal protection area is located on the outer circle of the cell area and arranged around the cell area, the power semiconductor device is characterized in that the semiconductor substrate comprises a first conduction type substrate and a first conduction type epitaxial layer located on the first conduction type substrate, and a second conduction type body area is arranged on the surface of the first conduction type epitaxial layer;
a first-type groove is arranged in the second conductive type body region of the cellular region, and the bottom of the first-type groove extends into the first-type conductive type epitaxial layer;
at least one second-type groove is formed in the second conductive type body region of the terminal protection region and close to the cellular region;
a cut-off ring structure is arranged in the second conductive type body region of the terminal protection region and surrounds the periphery of the second type groove;
the stop ring structure comprises a third groove and stop ring metal, the bottom of the third groove extends into the first conductive type epitaxial layer, the third groove surrounds the second groove, conductive polycrystalline silicon is arranged on the side wall of the third groove, insulating medium layers are filled in the bottom wall and the inner part of the third groove, the stop ring metal is located above the third groove, and the stop ring metal can be respectively contacted with the conductive polycrystalline silicon on the side wall of the third groove and the first conductive type epitaxial layer at the bottom of the third groove.
2. The power semiconductor device with the stop ring structure as claimed in claim 1, wherein the surfaces of the second conductive type body regions in the cell region and the terminal protection region are both provided with an insulating dielectric layer, the third type trench is covered by the insulating dielectric layer, gate oxide layers are formed on the sidewalls and the bottom wall of the third type trench, the third type trench is provided with a first type of conductive polysilicon on the sidewall close to the second type trench and on the surface of the gate oxide layer, the third type trench is provided with a second type of conductive polysilicon on the sidewall far from the second type trench and on the surface of the gate oxide layer, a first through hole is provided in the insulating dielectric layer above the first type of conductive polysilicon, a second through hole is provided in the insulating dielectric layer in the third type trench, and one end of the stop ring metal is filled in the first through hole and contacts with the first type of conductive polysilicon, and the other end of the stop ring metal fills the second through hole and is in contact with the first conductive type epitaxial layer.
3. The power semiconductor device with the cutoff ring structure as recited in claim 2, wherein said second type of conductive polysilicon is arranged floating.
4. The power semiconductor device with the stop ring structure as claimed in claim 1, wherein the surfaces of the second conductive type body regions in the cell region and the terminal protection region are respectively provided with an insulating dielectric layer, the third type trench is covered by the insulating dielectric layer, gate oxide layers are formed on the side wall and the bottom wall of the third type trench, the third type trench is close to the side wall of the second type trench and is provided with a first type of conductive polysilicon on the surface of the gate oxide layer, the third type trench is far away from the side wall of the second type trench and is provided with a second type of conductive polysilicon on the surface of the gate oxide layer, a first through hole is provided in the insulating dielectric layer above the first type of conductive polysilicon, a second through hole is provided in the insulating dielectric layer in the third type trench, and a third through hole is provided in the insulating dielectric layer above the second type of conductive polysilicon, one end of the stop ring metal is filled in the first through hole and is in contact with the first conductive polycrystalline silicon, the other end of the stop ring metal is filled in the third through hole and is in contact with the second conductive polycrystalline silicon, and the central area of the stop ring metal is filled in the second through hole and is in contact with the first conductive type epitaxial layer.
5. The power semiconductor device with the stop ring structure as claimed in any one of claims 1 to 4, wherein a gate oxide layer is formed on the bottom wall and the side wall of each of the first type trench and the second type trench, conductive polysilicon is disposed in each of the first type trench and the second type trench, the conductive polysilicon in the first type trench is connected to a gate potential, and the conductive polysilicon in the second type trench is arranged in a floating manner.
6. The power semiconductor device with the cutoff ring structure as claimed in claim 2 or 4, wherein a first conductivity type source region is disposed on a surface of the second conductivity type body region of the cell region, a source metal is disposed on a surface of the insulating dielectric layer of the cell region, a gate bus metal is disposed on a surface of the insulating dielectric layer of the terminal protection region, and the source metal is in contact with the second conductivity type body region and the first conductivity type source region through a fourth via hole on the insulating dielectric layer.
7. The power semiconductor device with the cutoff ring structure as recited in claim 1, wherein three second-type trenches are disposed in said second conductivity-type body region of said termination protection region.
8. The power semiconductor device with the cutoff ring structure according to any one of claims 1 to 4, wherein the power semiconductor device comprises an N-type power semiconductor device and a P-type power semiconductor device, and when the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type, and when the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.
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| CN201921417313.1U CN210156381U (en) | 2019-08-29 | 2019-08-29 | Power semiconductor device with cut-off ring structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110379848A (en) * | 2019-08-29 | 2019-10-25 | 无锡新洁能股份有限公司 | A kind of power semiconductor and preparation method thereof with cut-off ring structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110379848A (en) * | 2019-08-29 | 2019-10-25 | 无锡新洁能股份有限公司 | A kind of power semiconductor and preparation method thereof with cut-off ring structure |
| CN110379848B (en) * | 2019-08-29 | 2024-03-12 | 无锡新洁能股份有限公司 | Power semiconductor device with cutoff ring structure and manufacturing method thereof |
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