CN219917132U

CN219917132U - Integrated circuit

Info

Publication number: CN219917132U
Application number: CN202320055034.5U
Authority: CN
Inventors: C·A·苏亚雷斯·塞戈维亚; D·帕克; C·特鲁伊勒; A·马勒布; S·尼埃尔
Original assignee: STMicroelectronics Crolles 2 SAS; STMicroelectronics Rousset SAS
Current assignee: STMicroelectronics Crolles 2 SAS; STMicroelectronics Rousset SAS
Priority date: 2022-01-10
Filing date: 2023-01-09
Publication date: 2023-10-27
Anticipated expiration: 2033-01-09

Abstract

The present disclosure relates to integrated circuits. An integrated circuit, comprising: a semiconductor substrate; an electrically active region in the semiconductor substrate; and a thermally conductive protection structure extending around the electrically active region at a boundary of the integrated circuit. Thus, an improved integrated circuit is provided.

Description

Integrated circuit

Technical Field

Embodiments and implementations relate to integrated circuits

Background

Semiconductor substrate wafers are used as supports for the fabrication of integrated circuit components. The same semiconductor wafer may support several identical integrated circuits. Once the components of the integrated circuit have been manufactured, the integrated circuits are separated from one another in a singulation process by dicing (i.e., cutting through) the semiconductor wafer (typically designated by "die") according to dicing paths (typically designated by "dicing lines") that bypass the various integrated circuits.

There are different methods for singulating the different wafer pieces supporting the integrated circuits. For example, a saw may be used to saw the wafer along the dicing path.

Other singulation methods use laser ablation (also referred to as "laser scoring") followed by chemical etching or physical dicing along dicing paths.

In these singulation methods, laser ablation forms trenches in a semiconductor wafer down to the substrate level, and then chemical etching or physical dicing processes are used to ultimately singulate the wafer into individual integrated circuits.

For example, the etching may be plasma etching ("plasma dicing"). Plasma etching has several advantages over sawing.

In practice, the plasma etching does not generate vibrations during dicing, and thus the quality of dicing is improved. In practice, plasma etching is the act of electrically ionizing (plasma) bombardment of the wafer to remove one or more layers. Thus, plasma etching allows avoiding the application of mechanical pressure to the semiconductor wafer.

Plasma etching also allows finer dicing to be achieved, making it possible to form a greater number of integrated circuits on a semiconductor wafer.

However, laser ablation can cause significant heat release, which can generate thermal stresses in the semiconductor wafer.

However, plasma etching requires direct exposure of the semiconductor wafer substrate to the plasma.

Therefore, the use of metal structures in the center of the scribe path to optimize laser ablation is not possible.

As a result, the integrated circuit cannot withstand thermal stress caused by heat generated by laser ablation, and thus degradation of the integrated circuit is possible.

In particular, during dicing, heat generated by the laser may cause degradation of the substrate. Such substrate degradation may weaken the substrate. Then, during plasma etching, the weakening of the substrate may generate undesired lateral cracks in the substrate. However, lateral cracks propagate to the active parts of the integrated circuit and thus deteriorate them.

Therefore, there is a need to propose a solution that allows to protect integrated circuits during dicing of semiconductor wafers by laser ablation followed by chemical etching or physical dicing.

Disclosure of Invention

The present disclosure solves at least one or more of the problems set forth above.

According to another aspect, an integrated circuit formed on a semiconductor substrate is provided that includes an electrically active region and a thermally conductive protective structure extending around the electrically active region at a boundary of the integrated circuit.

Such an integrated circuit may be an integrated circuit obtained by implementing the integrated circuit manufacturing method as described above.

Preferably, the protective structure comprises a stack of continuous or discontinuous metal elements surrounding the active area of the integrated circuit.

The stack of metal elements may be at least partially formed in the shallow isolation trench.

In an advantageous embodiment, the protection structure further comprises a semiconductor substrate shoulder surrounding the active area of the integrated circuit.

Alternatively, the protection structure advantageously further comprises at least one polysilicon trench extending at least partially into the semiconductor substrate around the active area of the integrated circuit.

Preferably, the protection structure comprises several polysilicon trenches.

In an advantageous embodiment, the at least one polysilicon trench extends continuously around the active area of the integrated circuit.

Preferably, when the protection structure comprises several polysilicon trenches, the polysilicon trenches extend discontinuously around the active area of the integrated circuit, the trenches being arranged such that at least one trench faces the active area at any point around the active area.

In an advantageous embodiment, the integrated circuit further comprises a chip edge (sealing) ring surrounding said active area, the protective structure being formed around the chip edge ring.

Advantageously, the protection structure consists of the same heat conducting element as the other components of the integrated circuit.

According to a first aspect of the present disclosure, there is provided an integrated circuit comprising: a semiconductor substrate; an electrically active region in the semiconductor substrate; and a thermally conductive protection structure extending around the electrically active region at a boundary of the integrated circuit.

In some embodiments, the protective structure includes a stack of metal elements surrounding the electrically active region of the integrated circuit.

In some embodiments, the stack of metal elements is continuous around the electrically active region.

In some embodiments, the stack of metal elements is discontinuous around the electrically active region.

In some embodiments, the protective structure further comprises: a shoulder in the semiconductor substrate wafer around the electrically active region of the integrated circuit, wherein the semiconductor substrate wafer is thicker in the dicing path than in the electrically active region due to the presence of the shoulder; and at least one polysilicon trench below the thermally conductive protection structure and at least partially deeper into the semiconductor substrate around the electrically active region of the integrated circuit at a location adjacent to the semiconductor substrate shoulder.

In some embodiments, a metal contact structure extending between a bottom of the thermally conductive protection structure and a top of the at least one polysilicon trench is further included.

In some embodiments, the protection structure further comprises at least one polysilicon trench extending at least partially into the semiconductor substrate around the electrically active region of the integrated circuit.

In some embodiments, the protection structure includes a number of polysilicon trenches.

In some embodiments, the polysilicon trenches extend discontinuously around the electrically active area of the integrated circuit, the trenches being arranged such that at least one trench faces the electrically active area at any point around the electrically active area.

In some embodiments, the at least one polysilicon trench extends continuously around the electrically active region of the integrated circuit.

In some embodiments, the integrated circuit further comprises a metal contact structure extending between a bottom of the thermally conductive protection structure and a top of the at least one polysilicon trench.

In some embodiments, the integrated circuit further comprises a chip edge ring surrounding the electrically active region, the protection structure being formed between the chip edge ring and the boundary of the integrated circuit.

In some embodiments, the protective structure further includes a thermally conductive element that is the same as other components of the integrated circuit.

Thus, an improved integrated circuit is provided

Drawings

Other advantages and features of the utility model will appear upon examination of the detailed description of non-limiting implementations and embodiments, and the accompanying drawings, in which:

FIG. 1 illustrates a cross-sectional view of an embodiment of a semiconductor substrate wafer;

FIGS. 2A through 2F illustrate cross-sectional views of different embodiments of a protective structure;

figures 3A to 3C show top views of different embodiments of the trench; and

fig. 4 illustrates steps of a method for fabricating integrated circuits from a semiconductor substrate wafer.

Detailed Description

According to one aspect, a method for fabricating integrated circuits from a semiconductor substrate wafer includes: forming integrated circuits, each integrated circuit including an electrically active region; forming a thermally conductive protective structure around the active areas of the various integrated circuits in the scribe line path, the protective structure being located between the electrically active areas of the integrated circuits and the laser ablated areas of the scribe line path; and then separating the integrated circuits by dicing the semiconductor substrate wafer along dicing paths, wherein dicing comprises performing laser ablation in the laser ablated region, followed by performing one of chemical etching or physical dicing.

The thermally conductive protective structure allows capturing and subsequently dissipating heat generated by the laser downstream of the laser relative to the direction of movement of the laser. Thus, the protective structure allows reducing thermal stresses in the wafer. In this way, the protection structure allows to reduce the risk of lateral cracks occurring which may damage the active area of the integrated circuit.

Preferably, the formation of the protective structure includes forming a stack of continuous or discontinuous metal elements around the active areas of the various integrated circuits.

In an advantageous embodiment, the formation of the protective structure further comprises the formation of a semiconductor substrate shoulder. The substrate shoulder allows a deeper trench to be obtained, which allows a deeper thermal isolation into the substrate to be obtained, and limits or even prevents propagation of lateral cracks in the substrate, which can be generated during plasma etching due to the heat generated by laser ablation.

Alternatively, advantageously, the formation of the protective structure further comprises the formation of at least one polysilicon trench which extends at least partially into the semiconductor substrate.

Forming the polysilicon trenches allows trenches deeper into the substrate to be obtained. Each trench provides deeper thermal isolation and prevents lateral crack propagation to the active area of the integrated circuit.

Each polysilicon trench may be formed in the shallow isolation trench.

The formation of the at least one polysilicon trench may be performed simultaneously with the formation of polysilicon trenches for the fabrication of other integrated circuit components in the active area of the integrated circuit, such as capacitors, the at least one trench of the isolation structure being the same as the trenches for the fabrication of the other components of the integrated circuit.

Preferably, the protection structure comprises several polysilicon trenches.

Preferably, when the protection structure comprises several polysilicon trenches, the polysilicon trenches extend discontinuously around the active area of the integrated circuit, the trenches being arranged such that at least one trench faces the dicing path at any point around the active area of the integrated circuit.

In an advantageous implementation, the forming of each integrated circuit includes the forming of a chip edge ring surrounding the active region, and the protective structure is formed between the laser ablated region and the chip edge ring.

Each chip edge (or seal) ring may have mechanical protection properties and may seal the integrated circuit it surrounds from moisture.

Advantageously, the etching performed after laser ablation is plasma etching.

Preferably, the formation of the protective structure is performed simultaneously with the formation of other components of the integrated circuit. Thus, the formation of the protective structure does not require the use of an additional mask and is therefore inexpensive.

Fig. 1 shows a cross-sectional view of an embodiment of a semiconductor substrate SUB wafer PLQ. Several integrated circuit ICs are formed in multiple wafers (commonly referred to by the term "die"). In fig. 1, only two integrated circuits CI are partially represented.

Each integrated circuit CI comprises an electrically active region ZA. The active area ZA of each integrated circuit CI is surrounded by a chip edge ring SR (e.g. a seal ring). The chip edge ring SR may have mechanical protection characteristics and may seal the integrated circuit from moisture entering the integrated circuit.

The semiconductor wafer is configured to be diced in order to separate (i.e., singulate) the integrated circuits (die) from each other. In particular, a semiconductor wafer may be diced by performing laser ablation followed by chemical etching or physical dicing. The etching may in particular be plasma etching.

More specifically, the semiconductor wafer PLQ includes a space where dicing paths SCRB (commonly referred to as "dicing") are formed between various integrated circuits CI. The scribe path SCRB extends around the chip edge ring SR of the integrated circuit IC. Each scribe path SCRB includes a laser ablation region GRV on which laser ablation is performed. In fig. 1, laser ablation has been performed to form grooves RNR extending into the scribe path SCRB.

In order to protect the active area of the integrated circuit, the semiconductor wafer PLQ comprises a protection structure SP around the active area of the various integrated circuits. In particular, the protection structure SP extends vertically between the laser ablation region GRV and the active region of the integrated circuit CI, in particular between the laser ablation region GRV and the chip edge ring SR. The protection structure SP extends along the laser ablated region GRV. Thus, the protective structure adjoins the laser ablated region GRV. In particular, each protection structure SP is arranged at a chip edge ring distance D from its periphery. The distance D may be comprised between 0 μm and half the total width of the scribe path SCRB. More specifically, it is preferable to place the protective structure as close as possible to the laser ablated region GRV.

These protection structures SP are configured to dissipate the heat generated by laser ablation downstream of the laser with respect to the direction of movement of the laser, so as to reduce the risk of lateral cracks occurring which may degrade the active area of the integrated circuit after performing the plasma etching. The protection structure SP comprises an element formed of a thermally conductive material that surrounds the active area of the integrated circuit and extends along the laser ablated area. Thus, each element allows capturing and diffusing the heat generated by laser ablation downstream of the laser with respect to the direction of movement of the laser.

Fig. 2A to 2F show cross-sectional views of different embodiments of the protection structure SP.

In each embodiment, the protection structure SP includes a stack EPL of metal elements formed in an inter-metal oxide layer COIM. These elements, which are metal, are therefore thermally conductive and thus allow capturing and subsequently diffusing the heat generated by laser ablation. The stack EPL includes alternating successive metal layers p_epl and vias v_epl connecting different metal layers p_epl. This stacked EPL is formed in the back end of line (BEOL) portion of integrated circuit fabrication. Here, the stack EPL is vertically continuous in that it includes a via v_epl that connects to the metal layer p_ep, such as shown in the embodiment shown in fig. 2A. However, a vertically discontinuous stack EPL may be provided, which may include only metal layers p_epl that are not connected to each other, or only via holes v_epl that are not connected to each other. Discontinuous stacks EPL may also be provided, comprising metal layers p_epl and vias v_epl connecting only some of the metal layers p_epl.

As shown in the embodiments of fig. 2B, 2C, 2D, 2E and 2F, the protection structure SP may also comprise at least one metal element CTC, identical to the contacts used in the active area of the integrated circuit or to the contacts ctc_sr used in the chip edge ring. The metal elements CTC may extend vertically in order to connect the stack EPL to the substrate SUB of the semiconductor wafer PLQ. The metal element CTC may be made of tungsten. Stacking EPL and metal elements CTC allows heat generated by laser ablation to dissipate deep into substrate SUB. The use of metal elements CTC allows the addition of thermally conductive elements in order to improve the dissipation of heat generated by laser ablation.

As shown in each of the embodiments of fig. 2A to 2F, the protection structure SP may further comprise a shoulder STP of the substrate SUB of the semiconductor wafer in the vicinity of the laser ablated region. The substrate SUB shoulder STP allows a deeper trench STI to be obtained, which allows thermal isolation deeper into the substrate and limits or even prevents propagation of lateral cracks in the substrate SUB that may be generated due to heat generated by laser ablation during plasma etching. In particular, the shoulder STP may be formed at the stacked EPL, or between the stacked EPL and the laser ablated region, or between the stacked EPL and the chip edge ring. The shoulder STP may have a height of, for example, several hundred nanometers.

Furthermore, as shown in the embodiment of fig. 2C, the metal element CTC is directly connected to the shoulder STP of the substrate SUB. Therefore, the protection structure SP does not include the trench TRCH between the metal element CTC and the substrate SUB.

In the embodiment shown in fig. 2D, 2E and 2F, the protection structure further comprises at least one trench TRCH, which is formed partly in the shallow isolation trench STI and extends deep into the semiconductor substrate SUB.

Each trench TCRH is filled with a thermally conductive material. For example, each trench TRCH is filled with polysilicon. The polysilicon material allows for the introduction of thermal resistance in the substrate. For example, 10 can be used ¹³ atoms/cm ³ And 10 ²⁴ atoms/cm ³ The doping concentration between them dopes the polysilicon. Each trench extends deep into the semiconductor wafer substrate. As shown in the embodiments of fig. 2D and 2E, the width of the trench may vary. Forming the trench TRCH in the shallow isolation trench STI results in the trench TRCH extending deeper into the substrate SUB. Each trench TRCH allows deeper thermal isolation to be obtained and prevents propagation of lateral cracks towards the active region ZA of the integrated circuit.

In the embodiment of fig. 2D and 2E, the protective structure comprises a single trench. Alternatively, the protection structure may comprise several different trenches TRCH. Thus, as shown in the embodiment of fig. 2F, the stack EPL may be connected to two different trenches TRCH, for example by two metal elements CTC.

More specifically, fig. 3A to 3C show different embodiments of the trench TRCH in top views. As shown in the embodiments of fig. 3A and 3B, each trench TRCH may be continuous around the active area of the integrated circuit. In particular, the embodiment of fig. 3A has a continuous trench of greater width, as shown in the embodiment of fig. 2D. The embodiment of fig. 3B has two continuous trenches of narrower width as shown in the embodiment of fig. 2F.

Alternatively, as shown in the embodiment of fig. 3C, when the structure includes several trenches, particularly thin trenches as shown in the embodiment of fig. 2F, the trenches may be discontinuous. In the latter case, the trench TRCH is preferably arranged so as to have at least one trench facing the active region at any point around the active region. This embodiment allows to simplify the manufacture of the trench TRCH, since the trench TRCH then consists of a portion of limited length.

Fig. 4 shows a method for manufacturing integrated circuits from a semiconductor substrate SUB wafer PLQ.

The method comprises several steps 40, 41 and 42 (which may for example be performed simultaneously). In particular, the method includes fabricating 40 integrated circuits in a semiconductor substrate SUB wafer PLQ. The method further includes fabricating 41 a chip edge ring around the active region ZA of the integrated circuit. The method further comprises manufacturing 42 a protection structure SP according to one of the above embodiments.

In particular, the formation 42 of the protection structure may include the formation of at least one trench TRCH. The formation 42 of the protection structure may also include the formation of the stack EPL and at least one other metal element CTC connected or not connected to the at least one trench TRCH. As previously described, the formation 42 of the protection structure SP is carried out together with the formation of the integrated circuit CI. In particular, the formation of the trench TRCH may be performed simultaneously with the formation of the trench for manufacturing other components (not shown), such as a capacitor in an integrated circuit CI, the trench TRCH of the isolation structure being identical to the trench for manufacturing the other components. Furthermore, the formation of the stack EPL and the at least one metal element CTC may be performed simultaneously with the formation of the same stack and metal elements used for manufacturing the elements CTC of the integrated circuit or chip edge ring SR. In particular, the stack EPL and the at least one metal element CTC may be formed simultaneously with the stack EPL-SR and the metal element ctc_sr of the chip edge ring shown in fig. 1.

The method then comprises dicing 43, wherein the integrated circuits CI are separated from each other. In particular, the wafer is diced by dicing along dicing paths. Dicing the wafer first involves performing laser ablation and then performing one of chemical etching or physical dicing (e.g., sawing or plasma etching). The protective structure SP allows the heat generated by laser ablation to dissipate deep into the substrate in order to reduce the risk of cracks occurring in the semiconductor substrate during chemical etching or during physical dicing. After dicing, each integrated circuit includes on the boundary said protection structure SP which may have been damaged by the diced portion.

According to one aspect of the present disclosure, there is provided a method for manufacturing integrated circuits from a semiconductor substrate wafer, comprising: forming integrated circuits in the semiconductor substrate wafer, wherein each integrated circuit includes an electrically active region; forming thermally conductive protective structures around the electrically active regions of the various integrated circuits along scribe paths, wherein the protective structures are located between the electrically active regions of the integrated circuits and laser ablated regions of the scribe paths; and then separating the semiconductor substrate wafer by dicing the semiconductor substrate wafer along the dicing path

The integrated circuit, wherein dicing includes performing laser ablation in the laser ablated region followed by one of etching or physical dicing.

In some embodiments, wherein forming the protective structure includes forming a stack of metal elements around the electrically active regions of the various integrated circuits.

In some embodiments, wherein the stack of metal elements is continuous around the electrically active region.

0, wherein the stack of metal elements is discontinuous around the electrically active region.

In some embodiments, wherein forming the protective structure further comprises: forming shoulders in said semiconductor substrate wafer around said electrically active regions of various said integrated circuits

A portion in which the semiconductor substrate wafer is thicker in the dicing path 5 than in the electrically active region due to the presence of the shoulder portion; and forming at least one polysilicon trench under the thermally conductive protective structure, and the at least one polysilicon trench extending at least partially deep into the semiconductor substrate at a location adjacent the semiconductor substrate shoulder.

In some embodiments, the method further includes forming a metal contact structure extending between a bottom of the thermally conductive protection structure and a top of the at least one polysilicon trench.

0 in some embodiments, wherein forming the protective structure further comprises forming at least one polysilicon trench under the thermally conductive protective structure, and the at least one polysilicon trench extends at least partially deep into the semiconductor substrate.

In some embodiments, wherein the protection structure comprises a number of polysilicon trenches.

In some embodiments, wherein the trenches extend discontinuously around the electrically active 5 region of the integrated circuit, the trenches are arranged such that at least one trench faces the dicing path at any point around the electrically active region of the integrated circuit.

In some embodiments, wherein the at least one polysilicon trench extends continuously around the electrically active region of the integrated circuit.

In some embodiments, wherein forming each integrated circuit includes forming a chip edge ring surrounding the electrically active region, and wherein the protective structure is located between the laser ablated region and the chip edge ring.

In some embodiments, wherein the etching comprises plasma etching.

In some embodiments, forming the protection structure is performed concurrently with forming other components of the integrated circuit.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate;

an electrically active region in the semiconductor substrate; and

a thermally conductive protection structure extending around the electrically active region at a boundary of the integrated circuit.

2. The integrated circuit of claim 1, wherein the protection structure comprises a stack of metal elements surrounding the electrically active region of the integrated circuit.

3. The integrated circuit of claim 2, wherein the stack of metal elements is continuous around the electrically active region.

4. The integrated circuit of claim 2, wherein the stack of metal elements is discontinuous around the electrically active region.

5. The integrated circuit of claim 2, wherein the protection structure further comprises:

a shoulder in the semiconductor substrate wafer around the electrically active region of the integrated circuit, wherein the semiconductor substrate wafer is thicker in a dicing path than in the electrically active region due to the presence of the shoulder; and

at least one polysilicon trench below the thermally conductive protection structure and surrounding the electrically active region of the integrated circuit at least partially deep into the semiconductor substrate at a location adjacent to the semiconductor substrate shoulder.

6. The integrated circuit of claim 5, further comprising a metal contact structure extending between a bottom of the thermally conductive guard structure and a top of the at least one polysilicon trench.

7. The integrated circuit of claim 2, wherein the protection structure further comprises at least one polysilicon trench extending at least partially into the semiconductor substrate around the electrically active region of the integrated circuit.

8. The integrated circuit of claim 7, wherein the protection structure comprises a plurality of polysilicon trenches.

9. The integrated circuit of claim 8, wherein the polysilicon trenches extend discontinuously around the electrically active area of the integrated circuit, the trenches being arranged such that at least one trench faces the electrically active area at any point around the electrically active area.

10. The integrated circuit of claim 7, wherein the at least one polysilicon trench extends continuously around the electrically active region of the integrated circuit.

11. The integrated circuit of claim 7, further comprising a metal contact structure extending between a bottom of the thermally conductive guard structure and a top of the at least one polysilicon trench.

12. The integrated circuit of claim 1, further comprising a chip edge ring surrounding the electrically active region, the protection structure being formed between the chip edge ring and the boundary of the integrated circuit.

13. The integrated circuit of claim 1, wherein the protection structure further comprises a thermally conductive element that is the same as other components of the integrated circuit.