CN219644116U - Integrated base station - Google Patents

Abstract

The utility model provides an integrated base station which comprises an FPGA module, a CPU module, a first baseband module and an air interface synchronization module, wherein the FPGA module is in communication connection with the air interface synchronization module through a first pin, the FPGA module is in communication connection with the first baseband module through a second pin, the FPGA module is in communication connection with the CPU module through a third pin, and the FPGA module is used for distributing synchronization signals acquired from the air interface synchronization module to the first baseband module and the CPU module. The air interface synchronization module capable of monitoring surrounding base station signals and hardware for synchronizing signal transmission are newly added, when the first baseband module processes a physical layer, and when the CPU module processes a data link layer and a network layer, network synchronization can be carried out according to the synchronizing signals, load is balanced, interference among base stations is reduced, and therefore base station performance is improved.

Description

Integrated base station

Technical Field

The utility model relates to the technical field of communication, in particular to an integrated base station.

Background

The integrated base station generally adopts a System on Chip (SoC) architecture scheme, and signal transmission and reception are required to be completed under the state of network synchronization, so that interference among base stations is avoided. However, the conventional fifth generation mobile communication technology (5th Generation Mobile Communication Technology,5G) base station does not have an air interface interception function, and performs network synchronization in an indoor scene (such as a house, a shop, a garage, etc.) by means of a global positioning system (Global Positioning System, GPS) and a master-slave synchronization system (1588), which has the problems of large inter-base station interference and reduced performance.

It can be seen that the existing base station has a problem of poor performance.

Disclosure of Invention

The embodiment of the utility model provides an integrated base station to solve the problem of poor performance of the existing base station.

The integrated base station provided by the embodiment of the utility model comprises a Field Programmable Gate Array (FPGA) module, a Central Processing Unit (CPU) module, a first baseband module and an air interface synchronization module, wherein the FPGA module is in communication connection with the air interface synchronization module through a first pin, the FPGA module is in communication connection with the first baseband module through a second pin, the FPGA module is in communication connection with the CPU module through a third pin, and the FPGA module is used for distributing synchronization signals acquired from the air interface synchronization module to the first baseband module and the CPU module.

Optionally, the first baseband module is a fifth generation mobile communication technology 5G baseband module, and the air interface synchronization module is a fourth generation mobile communication technology 4G baseband module.

Optionally, the first baseband module is a 5G baseband module, and the air interface synchronization module includes a first synchronization module for listening to a 4G base station signal and a second synchronization module for listening to a 5G base station signal.

Optionally, the air interface synchronization module is integrated in the integrated base station.

Optionally, the FPGA module obtains the synchronization signal through the first pin, the synchronization signal includes a second pulse PPS signal and a single frequency network SFN signal, the first baseband module obtains the PPS signal and the SFN signal through the second pin, and the CPU module obtains the PPS signal through the third pin.

Optionally, the integrated base station further includes a global positioning system GPS interface, the GPS interface is connected to the air interface synchronization module, the air interface synchronization module is disposed at a first position, the FPGA module, the CPU module, and the first baseband module are disposed at a second position, and signal strength of the first position is greater than signal strength of the second position.

Optionally, under the condition that the air interface synchronization module is connected with the first pin of the FPGA module through the GPS interface, the FPGA module further includes a fourth pin, and the FPGA module is connected with the CPU module through the fourth pin in a communication manner;

the FPGA module obtains PPS signals in the synchronous signals through the first pins, the FPGA module obtains SFN signals in the synchronous signals through the fourth pins, the first baseband module obtains the PPS signals and the SFN signals through the second pins, and the CPU module obtains the PPS signals through the third pins.

Optionally, the CPU module includes a universal asynchronous receiver transmitter interface, where the universal asynchronous receiver transmitter interface is connected to the GPS interface, and the CPU module obtains a time-date TOD signal in the synchronization signal through the universal asynchronous receiver transmitter interface.

Optionally, the integrated base station further comprises a physical layer module, and the physical layer module is in communication connection with the FPGA module through the CPU module.

Optionally, the first pin, the second pin and the third pin are all general purpose input/output GPIO hardware pins.

In the embodiment of the utility model, the air interface synchronization module capable of monitoring the signals of the surrounding base stations and the hardware for transmitting the synchronization signals are newly added, the air interface synchronization module transmits the synchronization signals obtained by analyzing the signals of the surrounding base stations to the FPGA module, the FPGA module locks according to the synchronization signals and distributes the locked signals to the first baseband module and the CPU module, and the first baseband module can perform network synchronization according to the synchronization signals when processing the physical layer and the CPU module when processing the data link layer and the network layer, so that the load is balanced, the interference among the base stations is reduced, and the performance of the base stations is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings used in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an integrated base station according to an embodiment of the present utility model;

FIG. 2 is a second schematic diagram of an integrated base station according to an embodiment of the present utility model;

fig. 3 is a third schematic structural diagram of an integrated base station according to an embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The terms "first," "second," and the like in embodiments of the present utility model are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the utility model provides an integrated base station, which comprises a field programmable gate array (Field Programmable Gate Array, FPGA) module, a central processing unit (Central Processing Unit, a CPU) module, a first baseband module and an air interface synchronization module, wherein the FPGA module is in communication connection with the air interface synchronization module through a first pin, the FPGA module is in communication connection with the first baseband module through a second pin, the FPGA module is in communication connection with the CPU module through a third pin, and the FPGA module is used for distributing synchronization signals acquired from the air interface synchronization module to the first baseband module and the CPU module.

In this embodiment, an air interface synchronization module capable of intercepting signals of surrounding base stations and hardware for transmitting synchronization signals are newly added, the air interface synchronization module transmits the synchronization signals obtained by analyzing the signals based on the surrounding base stations to the FPGA module, the FPGA module locks according to the synchronization signals and distributes the locked signals to the first baseband module and the CPU module, and when the first baseband module processes the physical layer L1 and when the CPU module processes the data link layer L2 and the network layer L3, the network synchronization can be performed according to the synchronization signals, load is balanced, interference between base stations is reduced, and accordingly, performance of the base station is improved.

The first pin, the second pin and the third pin can be newly added in the air interface synchronous module, so that the FPGA module is in communication connection with the air interface synchronous module through the first pin, the FPGA module is in communication connection with the first baseband module through the second pin, the FPGA module is in communication connection with the CPU module through the third pin, it is understood that the pin matched with the first pin is also arranged in the air interface synchronous module, the pin matched with the second pin is also arranged in the first baseband module, the pin matched with the third pin is also arranged in the CPU module, a communication line is arranged between the FPGA module and the air interface synchronous module, and a communication line is arranged between the FPGA module and the first baseband module to realize transmission of synchronous signals.

Alternatively, the first pin, the second pin, and the third pin may each be General-purpose input/output (GPIO) hardware pins. The GPIO hardware pin has the advantages of low power consumption, predeterminable response time, simple wiring and the like.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an integrated base station provided by an embodiment of the present utility model, and as shown in fig. 1, the integrated base station provided by the embodiment of the present utility model includes an FPGA module, a CPU module, a first baseband module, and an air interface synchronization module, where the FPGA module is communicatively connected with the air interface synchronization module through a first pin, the FPGA module is communicatively connected with the first baseband module through a second pin, and the FPGA module is communicatively connected with the CPU module through a third pin, and is configured to distribute a synchronization signal obtained from the air interface synchronization module to the first baseband module and the CPU module. The first baseband module is a fifth generation mobile communication technology 5G baseband module, and the air interface synchronization module is a fourth generation mobile communication technology (4th Generation Mobile Communication Technology,4G) baseband module.

In this embodiment, the integrated base station may be a 4G/5G dual-mode integrated base station, and since the existing 5G base station chip does not have an air interface interception function, a 4G baseband module capable of intercepting surrounding base station signals and hardware for synchronizing signal transmission may be newly added in the integrated base station, and the 4G baseband module is utilized to acquire signals of base stations within its coverage area and analyze and obtain synchronizing signals aligned with network time; then, the FPGA module can acquire the synchronous signal in the 4G baseband module through the first pin, the FPGA module locks according to the synchronous signal and distributes the synchronous signal to the 5G baseband module and the CPU module, when the 5G baseband module processes the physical layer L1 and when the CPU module processes the data link layer L2 and the network layer L3, the network synchronization can be carried out according to the synchronous signal, the load is balanced, and the interference among base stations is reduced, so that the performance of the base station is improved.

Specifically, the FPGA module is correspondingly designed with a hardware pin, and acquires a synchronization signal aligned with the network time in the 4G baseband module through the first pin, where the synchronization signal may include a Pulse Per Second (PPS) signal (e.g., 4g_1pps) and a single frequency network (Single Frequency Network, SFN) signal.

The FPGA module finishes locking the 4G_1PPS and the SFN to obtain FPGA2NR_1PPS, FPGA2CPU_1PPS and FPGA2NR_SFN; the FPGA module distributes the FPGA2NR_1PPS and the FPGA2NR_SFN to the 5G baseband module through the second pin, and distributes the FPGA2CPU_1PPS to the CPU module through the third pin, wherein the FPGA can be controlled to select synchronous source input according to actual conditions.

The CPU module can process the data link layer L2 and the network layer L3 according to the FPGA2 CPU_1PPS; the 5G baseband module configures 5G baseband chip parameters according to the frame offset relation of the current networks 4G and 5G to align time information with the 5G network, then generates internal time and time interval (Time and Time Interval, TTI) time sequences, and performs uplink and downlink processing according to the FPGA2NR_1PPS and the FPGA2 NR_SFN.

Referring to fig. 2, fig. 2 is a second schematic structural diagram of an integrated base station provided by the embodiment of the present utility model, as shown in fig. 2, the integrated base station provided by the embodiment of the present utility model includes an FPGA module, a CPU module, a first baseband module and an air interface synchronization module, where the FPGA module is communicatively connected with the air interface synchronization module through a first pin, the FPGA module is communicatively connected with the first baseband module through a second pin, the FPGA module is communicatively connected with the CPU module through a third pin, and the FPGA module is configured to distribute a synchronization signal obtained from the air interface synchronization module to the first baseband module and the CPU module. The first baseband module may be a 5G baseband module, and the air interface synchronization module includes a first synchronization module for listening to a 4G base station signal and a second synchronization module for listening to a 5G base station signal.

In this embodiment, the integrated base station may be an integrated air interface synchronization module centralized 5G base station, and since the existing 5G base station chip does not have an air interface interception function, an air interface synchronization module designed based on a terminal device and hardware for transmitting synchronization signals may be newly added in the integrated base station, so that the integrated base station may be used in combination with the terminal device, so that the integrated base station has an air interface interception capability. The terminal device may be a mobile phone, a computer, etc. Because the terminal equipment comprises a 4G chip or a 5G chip, the corresponding air interface synchronization module is provided with a first synchronization module and a second synchronization module, the 4G base station signal acquired by the terminal equipment can be intercepted by the first synchronization module, and the 5G base station signal acquired by the terminal equipment can be intercepted by the second synchronization module. The terminal equipment receives signals of base stations in the coverage area of the terminal equipment and inputs the signals to the air interface synchronization module through a radio frequency channel; the air interface synchronization module analyzes the air interface information to obtain a network synchronization signal; then, the FPGA module can acquire the synchronous signal in the air interface synchronous module through the first pin, the FPGA module locks according to the synchronous signal and distributes the synchronous signal to the 5G baseband module and the CPU module, when the 5G baseband module processes the physical layer L1 and when the CPU module processes the data link layer L2 and the network layer L3, the CPU module can perform network synchronization according to the synchronous signal, load is balanced, interference among base stations is reduced, and therefore base station performance is improved.

Specifically, the FPGA module is correspondingly designed with a hardware pin, and obtains a synchronization signal obtained by analyzing an air interface message based on the terminal device in the air interface synchronization module through the first pin, where the synchronization signal may include a PPS signal and an SFN signal.

The FPGA module finishes locking NL_1PPS and SFN to obtain FPGA2NR_1PPS, FPGA2CPU_1PPS and FPGA2NR_SFN; the FPGA module distributes the FPGA2NR_1PPS and the FPGA2NR_SFN to the 5G baseband module through the second pin, and distributes the FPGA2CPU_1PPS to the CPU module through the third pin, wherein the FPGA can be controlled to select synchronous source input according to actual conditions.

The CPU module may perform the processing of the data link layer L2 and the network layer L3 according to the FPGA2cpu_1 PPS. Under the condition that the synchronous signal is a signal obtained by analyzing an air interface message of the terminal equipment based on the 4G chip, the 5G baseband module configures 5G baseband chip parameters according to the frame offset relation of the current network 4G and 5G so as to level time information with the 5G network, then generates an internal TTI time sequence, and performs uplink and downlink processing according to the FPGA2NR_1PPS and the FPGA2 NR_SFN. Under the condition that the synchronous signal is detected to be a signal obtained by analyzing an air interface message of the terminal equipment based on the 5G chip, the 5G baseband module directly obtains time information aligned with a network, generates an internal TTI time sequence and performs uplink and downlink processing.

In some alternative embodiments, the air interface synchronization module is integrated within the integrated base station. By integrating the air interface synchronization module, the circuit arrangement is reduced, and the stability of the integrated base station is improved. After the air interface synchronization module is newly added, the integrated base station has an air interface interception function, can perform network synchronization according to the synchronization signals, balances loads, reduces interference among base stations, and accordingly improves base station performance.

In other alternative embodiments, the air interface synchronization module may be configured as a separate external component that receives and parses the base station signals within its coverage area. The structural design is free from the position of the integrated base station in deployment, the deployment is more flexible, and the air interface synchronization module can be selectively deployed in the areas with better base station signals around the window edge, the balcony and the like. Referring specifically to fig. 3, fig. 3 is a third schematic structural diagram of an integrated base station provided by the embodiment of the present utility model, as shown in fig. 3, the integrated base station provided by the embodiment of the present utility model includes an FPGA module, a CPU module, a first baseband module and an air interface synchronization module, where the FPGA module is communicatively connected with the air interface synchronization module through a first pin, the FPGA module is communicatively connected with the first baseband module through a second pin, the FPGA module is communicatively connected with the CPU module through a third pin, and the FPGA module is configured to distribute a synchronization signal obtained from the air interface synchronization module to the first baseband module and the CPU module. The integrated base station further comprises a global positioning system GPS interface, the GPS interface is connected with the air interface synchronization module, the air interface synchronization module is placed at a first position (such as a window edge, a balcony and other surrounding base station signal better areas), the FPGA module, the CPU module and the first baseband module are placed at a second position, and the signal intensity of the first position is greater than that of the second position.

In this embodiment, the integrated base station may be an integrated air interface synchronization module distributed 5G base station, and since the existing 5G base station chip does not have an air interface interception function, any one of the air interface synchronization module and the GPS receiving unit may be connected through the GPS interface. The GPS interface can input GPS_1PPS and time and date TOD information, so that the air interface synchronous module multiplexes the GPS interface (such as RJ 45) to reduce redundancy.

In this way, whether to use the air interface synchronization module can be flexibly selected according to the scene. When the GPS and master-slave synchronization system 1588 conditions are met, the air interface synchronization module can be selected to be no longer configured. The air interface synchronization module can be adapted to a 5G module or a 4G module, and can select specifications according to scenes. When the GPS condition and the master-slave synchronization system 1588 condition are not met, the air interface synchronization module can be quickly adapted, the synchronization signals are acquired and distributed to the 5G baseband module and the CPU module, so that the integrated base station can perform network synchronization according to the synchronization signals, load is balanced, interference among base stations is reduced, and therefore base station performance is improved.

Optionally, under the condition that the air interface synchronization module is connected with the first pin of the FPGA module through the GPS interface, the FPGA module further includes a fourth pin, and the FPGA module is connected with the CPU module through the fourth pin in a communication manner;

the FPGA module obtains PPS signals in the synchronous signals through the first pins, the FPGA module obtains SFN signals in the synchronous signals through the fourth pins, the first baseband module obtains the PPS signals and the SFN signals through the second pins, and the CPU module obtains the PPS signals through the third pins.

In an example, when the GPS condition and the master-slave synchronization system 1588 condition are not present, the air interface synchronization module may be quickly adapted, i.e., the air interface synchronization module is connected to the GPS interface. The air interface synchronization module acquires signals of base stations in the coverage area of the air interface synchronization module, and analyzes the signals to obtain synchronization signals aligned with network time; and then, the FPGA module can be connected with a corresponding pin in the GPS interface through the first pin to acquire a PPS signal in the synchronous signal, and the FPGA module locks according to the PPS signal in the synchronous signal to distribute the PPS signal to the 5G baseband module and the CPU module. And the FPGA module locks after receiving the SFN signals in the synchronous signals, and distributes the SFN signals to the 5G baseband module.

The CPU module is provided with a universal asynchronous receiver/Transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface and a GPIO interface connected with a fourth pipe pin of the FPGA module, the UART interface on the CPU module can be connected with the GPS interface, and the GPIO interface on the CPU module can be connected with the fourth pipe pin of the FPGA module. Therefore, the UART interface on the CPU module can be connected with the GPS interface to convert TOD signals into SFN signals after synchronizing TOD signals in the signals, and the GPIO on the CPU module is connected with the fourth pin of the FPGA module to distribute the SFN signals to the 5G baseband module. Therefore, the time information of the air interface synchronization module can be obtained through the GPS interface, and the internal processing multiplexing and GPS synchronization mode reduces the cost of configuring the integrated base station.

Under the condition that the synchronous signal is a signal obtained by analyzing an air interface message based on a 4G base station, the 5G base band module configures 5G base band chip parameters according to the frame offset relation of the current network 4G and 5G so as to align time information with the 5G network, then generates an internal TTI time sequence, and performs uplink and downlink processing according to the FPGA2NR_1PPS and the FPGA2 NR_SFN. Under the condition that the synchronous signal is detected to be a signal based on the air interface message analysis of the 5G base station, the 5G baseband module directly obtains time information aligned with a network, generates an internal TTI time sequence and performs uplink and downlink processing. When the 5G baseband module processes the physical layer L1 and the CPU module processes the data link layer L2 and the network layer L3, network synchronization can be performed according to the synchronization signals, load is balanced, interference among base stations is reduced, and therefore base station performance is improved.

In other alternative embodiments, the integrated base station further includes a Physical (PHY) module, and the PHY module is communicatively connected to the FPGA module through the CPU module.

When the GPS synchronization mode is adopted, the FPGA acquires a GPS_1pps source signal from a GPS interface, locks the signal, outputs the signal to a 5G baseband module and a CPU module, and completes the processing of the base stations L1, L2 and L3 in a system synchronization state.

When the 1588 synchronization mode is adopted, a CPU obtains a data source from a PHY module, generates 1588_1pps and outputs the 1588_1pps to an FPGA module, and the FPGA module completes the generation and locking of 1588_1pps signals and outputs the 1588_1pps signals to a 5G baseband module and a CPU module to complete the processing of the base stations L1, L2 and L3.

The common deployment scene of the integrated base station is a resident family, the GPS and 1588 synchronous deployment condition is not generally provided, and the current 5G integrated base station is limited by the fact that a 5G baseband chip cannot support air interface synchronous capability, so that the integrated base station is limited in use. Therefore, the integrated base station provided by the embodiment of the utility model can be a 4G/5G dual-mode integrated base station, or can be an integrated air interface synchronization module centralized 5G base station, or can be an integrated air interface synchronization module distributed 5G base station, so that the integrated base station is not limited by the capability of a 5G chip by configuring an air interface synchronization module and hardware for synchronizing information transmission, the air interface synchronization capability of a 5G function is provided, and the application scene of the base station is enlarged.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present utility model is not limited to performing the functions in the order discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

The embodiments of the present utility model have been described above with reference to the accompanying drawings, but the present utility model is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present utility model and the scope of the claims, which are to be protected by the present utility model.

Claims (10)

1. The integrated base station is characterized by comprising a field programmable gate array module, a central processing unit module, a first baseband module and an air interface synchronization module, wherein the field programmable gate array module is in communication connection with the air interface synchronization module through a first pin, the field programmable gate array module is in communication connection with the first baseband module through a second pin, the field programmable gate array module is in communication connection with the central processing unit module through a third pin, and the field programmable gate array module is used for distributing synchronization signals acquired from the air interface synchronization module to the first baseband module and the central processing unit module.

2. The integrated base station of claim 1, wherein the first baseband module is a fifth generation mobile communication technology baseband module and the air interface synchronization module is a fourth generation mobile communication technology baseband module.

3. The integrated base station of claim 1, wherein the first baseband module is a fifth generation mobile communication technology baseband module, and the air interface synchronization module comprises a first synchronization module for listening to a fourth generation mobile communication technology base station signal and a second synchronization module for listening to a fifth generation mobile communication technology base station signal.

4. A unitary base station as claimed in any one of claims 2 to 3, wherein the air interface synchronization module is integrated within the unitary base station.

5. The integrated base station of any of claims 2-3, wherein the field programmable gate array module obtains the synchronization signal via the first pin, the synchronization signal comprising a pulse-per-second signal and a single frequency network signal, the first baseband module obtains the pulse-per-second signal and the single frequency network signal via the second pin, and the central processor module obtains the pulse-per-second signal via the third pin.

6. The integrated base station of claim 1, further comprising a global positioning system interface coupled to the air interface synchronization module, the air interface synchronization module positioned at a first location, the field programmable gate array module, the central processor module, and the first baseband module positioned at a second location, the first location having a signal strength greater than a signal strength of the second location.

7. The integrated base station of claim 6, wherein in the case where an air interface synchronization module is connected to a first pin of the field programmable gate array module through the global positioning system interface, the field programmable gate array module further comprises a fourth pin, the field programmable gate array module is communicatively connected to the central processor module through the fourth pin;

the field programmable gate array module acquires a second pulse signal in the synchronous signal through the first pin, the field programmable gate array module acquires a single-frequency network signal in the synchronous signal through the fourth pin, the first baseband module acquires the second pulse signal and the single-frequency network signal through the second pin, and the central processing unit module acquires the second pulse signal through the third pin.

8. The integrated base station of claim 7, wherein the central processor module includes a universal asynchronous receiver transmitter interface, the universal asynchronous receiver transmitter interface being coupled to the global positioning system interface, the central processor module obtaining a time-date signal of the synchronization signal through the universal asynchronous receiver transmitter interface.

9. The integrated base station of claim 1, further comprising a physical layer module communicatively coupled to the field programmable gate array module via the central processor module.

10. The integrated base station of claim 1, wherein the first pin, the second pin, and the third pin are all universal input-output hardware pins.