CN219267656U

CN219267656U - Reduce array substrate of feedthru voltage

Info

Publication number: CN219267656U
Application number: CN202320154646.XU
Authority: CN
Inventors: 毛清平
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2023-01-28
Filing date: 2023-01-28
Publication date: 2023-06-27
Anticipated expiration: 2033-01-28

Abstract

The utility model relates to the technical field of displays, and provides an array substrate for reducing a feedback voltage, which comprises the following components: a glass substrate; a first metal layer plated on the upper surface of the glass substrate to form a grid electrode, a first CK signal wire, a second CK signal wire, a third CK signal wire and a fourth CK signal wire which are distributed at intervals; an active layer plated on an upper surface of the gate insulating layer; the second metal layer is plated on the upper surface of the gate insulating layer, and source electrodes, drain electrodes, first signal connecting lines and second signal connecting lines which are distributed at intervals are formed; the conducting layer is plated on the upper surface of the passivation layer and is also positioned right above the drain electrode; and the pixel electrode is plated on the upper surface of the passivation layer. The utility model has the advantages that: the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, and the feedback voltage is reduced.

Description

Reduce array substrate of feedthru voltage

Technical Field

The utility model relates to the technical field of displays, in particular to an array substrate for reducing a feedback voltage.

Background

In the case of a TFT-LCD display, the side of the TFT connected to the pixel electrode is generally called the drain, and the capacitance formed between the drain and the gate metal is generally called the parasitic capacitance C _gd . The grid electrode of the TFT device is connected with the grid lines which are transversely distributed and used for controlling the on-off of the TFT device; the source electrode of the TFT device is connected with the data lines which are longitudinally distributed and used for writing the data voltage to be displayed into the TFT device; when the TFT is turned on, the source electrode is conducted with the drain electrode, the data voltage enters the drain electrode and reaches the liquid crystal capacitor Cst from the pixel electrode, and the light transmittance of the liquid crystal is adjusted; when the TFT is turned off, the source and drain are turned off, and the data voltage of the source cannot enter the drain. The data voltage of the source electrode changes in positive and negative polarities periodically, and is a deflection voltage for making the liquid crystal generate positive and negative polarities.

Referring to fig. 1 and 2, at the instant of TFT off, the gate voltage V _g V from high level _high V instantaneously dropping to low level _low Due to parasitic capacitance C _gd The presence of (C) will be V _g The transient change of (a) is coupled to the drain electrode, resulting in a drop in the drain voltage, and the voltage difference between the pixel electrode and the drain electrode may cause a jump in the voltage of the pixel electrode, which is referred to as the feedback voltage. In the waveform diagram of FIG. 2, V _g Is the gate voltage, V _d Is the drain voltage in an ideal state,

is the center point of the actually supplied common electrode voltage, i.e. the actually supplied positive and negative deflection voltages, V _p (t) is the actual pixel electrode voltage, V _com Is the common electrode voltage in the ideal state of keeping the same voltage at both ends of the liquid crystal in the positive and negative polarity state, V _offset Is the deviation of the ideal common electrode voltage from the actual common electrode voltage, T _f Is the switching period of the TFT device, _Vlc ＞V _com is the region where the pixel electrode voltage is greater than the common electrode voltage in the current ideal state, V _lc ＜V _com Is a region where the pixel electrode voltage is less than the common electrode voltage of the current ideal state.

As shown in FIG. 2, the existence of the feed through voltage results in an ideal state of the common electrode V _com The point position deviates from the center position of the actually provided positive and negative deflection voltages, namely the common electrode voltage in an ideal state changes, but the actually provided positive and negative deflection voltages are unchanged, so that voltages at two ends of liquid crystal in the positive and negative states are different, the deflection angles of the liquid crystal in the positive and negative states are different, the light quantity of the array substrate is different, and the picture of the liquid crystal display is flickering. Reducing the Feedthrough voltage is a problem that should be solved at present.

Disclosure of Invention

The utility model aims to solve the technical problem of providing an array substrate for reducing the feed through voltage, and the conductive layer is arranged above the drain electrode, so that the potential of the conductive layer is opposite to that of the grid electrode, and the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, thereby reducing the feed through voltage.

The utility model is realized in the following way:

reduce array substrate of feedthru voltage

A glass substrate;

a first metal layer plated on the upper surface of the glass substrate to form grid electrodes, a first CK signal wiring, a second CK signal wiring, a third CK signal wiring and a fourth CK signal wiring which are distributed at intervals, wherein the potential of the first CK signal wiring is opposite to that of the third CK signal wiring, the potential of the second CK signal wiring is opposite to that of the fourth CK signal wiring, and the grid electrodes are divided into a first row of grid electrodes and a second row of grid electrodes;

the grid insulation layer is plated on the upper surfaces of the glass substrate and the first metal layer, a first hole, a second hole, a third hole and a fourth hole are formed in the grid insulation layer outside the pixel display area, the first row of grid electrodes are exposed out of the first hole, the second row of grid electrodes are exposed out of the second hole, the first CK signal wire is exposed out of the third hole, and the second CK signal wire is exposed out of the fourth hole;

the active layer is plated on the upper surface of the grid electrode insulating layer, and is positioned right above the grid electrode and also positioned in the pixel display area;

the second metal layer is plated on the upper surface of the gate insulating layer to form source electrodes, drain electrodes, first signal connecting lines and second signal connecting lines which are distributed at intervals, the source electrodes are connected with the left end of the active layer, the drain electrodes are connected with the right end of the active layer, the source electrodes and the drain electrodes are positioned in the pixel display area, the right end of the first signal connecting line penetrates through the first hole to be connected with the first row of grid electrodes, the left end of the first signal connecting line penetrates through the third hole to be connected with the first CK signal wiring, the right end of the second signal connecting line penetrates through the second hole to be connected with the second row of grid electrodes, and the left end of the second signal connecting line penetrates through the fourth hole to be connected with the second CK signal wiring;

the passivation layer is plated on the upper surfaces of the gate insulating layer, the active layer and the second metal layer, a fifth hole and a sixth hole are formed in the passivation layer outside the pixel display area, a seventh hole is formed in the pixel display area, the fifth hole and the sixth hole penetrate through the gate insulating layer, the third CK signal wiring is exposed out of the fifth hole, the fourth CK signal wiring is exposed out of the sixth hole, and the drain electrode is exposed out of the seventh hole;

the conducting layer is plated on the upper surface of the passivation layer and is further positioned right above the drain electrode, the conducting layer is divided into a first row of conducting layers and a second row of conducting layers, a third signal connecting wire and a fourth signal connecting wire are plated on the upper surface of the passivation layer, the first row of conducting layers are connected with the right end of the third signal connecting wire, the left end of the third signal connecting wire penetrates through the fifth hole to be connected with the third CK signal wiring, the second row of conducting layers are connected with the right end of the fourth signal connecting wire, and the left end of the fourth signal connecting wire penetrates through the sixth hole to be connected with the fourth CK signal wiring;

and the pixel electrode is plated on the upper surface of the passivation layer, and a lead of the pixel electrode passes through the seventh hole to be connected with the drain electrode.

Further, the method further comprises the following steps:

the second metal layer also forms TP wirings which are distributed at intervals;

the outer insulating layer is plated on the upper surfaces of the pixel electrode, the conducting layer and the passivation layer, an eighth hole is formed in the surface of the pixel display area, the eighth hole penetrates through the passivation layer, and the TP wiring is exposed out of the eighth hole;

and the public electrode is plated on the upper surface of the outer insulating layer, and a lead of the public electrode also passes through the eighth hole to be connected with the TP wiring.

Further, the signal timing phase of the first CK signal trace is one quarter cycle earlier than the signal timing phase of the second CK signal trace, and the signal timing phase of the third CK signal trace is one quarter cycle earlier than the signal timing phase of the fourth CK signal trace.

Further, the circuit further comprises a drive IC, wherein the drive IC is connected with the first CK signal wiring, the second CK signal wiring, the third CK signal wiring and the fourth CK signal wiring.

Further, the first metal layer is any one of an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO double-layer structure and an AL/Ti double-layer structure, and the second metal layer is an MO/AL/MO three-layer structure or a Ti/AL/Ti three-layer structure.

Further, the gate insulating layer is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer is of SiO ₂ The outer insulating layer is made of SiOx, siNO or SiNx.

Further, the active layer is made of an IGZO material, and the conductive layer, the pixel electrode and the common electrode are made of an ITO material.

The utility model has the advantages that: 1. a conductive layer is arranged above the drain electrode, a complementary capacitor is formed between the conductive layer and the drain electrode, signals of a first row of grid electrodes are provided by a first CK signal wiring, signals of a second row of grid electrodes are provided by a second CK signal wiring, signals of a first row of conductive layer are provided by a third CK signal wiring, signals of a second row of conductive layer are provided by a fourth CK signal wiring, the potential of the conductive layer is opposite to that of the grid electrode, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conductive layer to the drain electrode are mutually offset, the voltage difference generated between the pixel electrode and the drain electrode is reduced, the feed through voltage is reduced, and the picture flicker of the liquid crystal display is reduced; when the supplementary capacitance and the parasitic capacitance are equal in size, the feedback voltage is eliminated, and the picture display stability of the liquid crystal display is improved. 2. Under the control of the first CK signal wiring, the second CK signal wiring, the third CK signal wiring and the fourth CK signal wiring, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are turned on and off successively, so that the first row of pixels and the second row of pixels of the display screen are set to brightness successively, and the liquid crystal display screen displays stably row by row. 3. The conductive layer is arranged at a position close to the contact of the drain electrode and the active layer, and the field intensity of the position is larger, so that the Schottky barrier formed by the contact of the active layer semiconductor and the metal line of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current can be increased. 4. The ITO has good conductivity and light transmittance, and the conductive layer and the pixel electrode of the array substrate are made of ITO, so that the conductive layer and the pixel electrode can be formed into a film in the same process, thereby simplifying the substrate structure and improving the productivity.

Drawings

The utility model will be further described with reference to examples of embodiments with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of parasitic capacitance existing between a gate and a drain of a TFT device in the background art.

FIG. 2 is a schematic diagram of a common electrode V in an ideal state due to the presence of a feed through voltage in the background art _com Schematic diagram of point location deviation.

Fig. 3 is a schematic design diagram of an array substrate for reducing a Feedthrough voltage according to the present utility model.

Fig. 4 is a circuit schematic diagram of a first row of TFT devices of the array substrate of fig. 3.

Fig. 5 is a circuit schematic of a second row of TFT devices of the array substrate of fig. 3.

FIG. 6 is a timing diagram of a first CK signal trace, a second CK signal trace, a third CK signal trace, and a fourth CK signal trace in the present utility model.

Fig. 7 is a schematic top view of an array substrate for reducing Feedthrough voltage according to the present utility model.

Fig. 8.1 is a flow chart of the manufacturing process of the array substrate for reducing the Feedthrough voltage of the present utility model.

Fig. 8.2 is a second flowchart of the manufacturing of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.3 is a third flowchart of the manufacturing of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.4 is a flowchart of the manufacturing process of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.5 is a flowchart of the manufacturing process of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.6 is a flowchart of manufacturing the array substrate with reduced Feedthrough voltage according to the present utility model.

Fig. 8.7 is a flow chart of fabricating an array substrate with reduced Feedthrough voltage according to the present utility model.

Fig. 8.8 is a flowchart eight of the manufacturing method of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.9 is a flowchart of manufacturing an array substrate with reduced Feedthrough voltage according to the present utility model.

Fig. 8.10 is a flowchart of manufacturing an array substrate with reduced Feedthrough voltage according to the present utility model.

Fig. 8.11 is a flowchart eleven of the manufacturing process of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.12 is a flowchart showing a manufacturing process of an array substrate for reducing a Feedthrough voltage according to the present utility model.

Fig. 8.13 is a flowchart of a manufacturing process of an array substrate for reducing a Feedthrough voltage according to the present utility model.

Fig. 8.14 is a flowchart fourteen of the manufacturing method of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.15 is a flowchart fifteen of the manufacturing process of the array substrate for reducing the Feedthrough voltage according to the present utility model.

Fig. 8.16 is a flowchart of manufacturing a reduced Feedthrough voltage array substrate according to the present utility model.

Reference numerals: a glass substrate 1; a pixel display area 11;

a gate electrode 2; a first row of gates 21; a second row of gates 22;

a first CK signal wiring 31; a second CK signal trace 32; a third CK signal wiring 33; a fourth CK signal trace 34;

a gate insulating layer 4; a first hole 41; a second hole 42; a third hole 43; fourth cutout 44;

an active layer 5;

a source electrode 6;

a drain electrode 7;

a first signal connection line 81; a second signal connection line 82; a third signal connection line 83; a fourth signal connection line 84;

a passivation layer 9; fifth hole 91; sixth cutout 92; seventh hole digging 93;

a conductive layer 10; a first row conductive layer 101; a second row conductive layer 102;

a pixel electrode 20;

TP trace 30;

an outer insulating layer 40; eighth hole 401;

and a common electrode 50.

Detailed Description

The embodiment of the utility model solves the problem of flicker of a liquid crystal display picture caused by the existence of the feed through voltage in the background technology by providing the array substrate for reducing the feed through voltage, and achieves the technical effects of reducing the feed through voltage and stabilizing the liquid crystal display picture.

The technical scheme in the embodiment of the utility model aims to solve the defects, and the general idea is as follows:

the main improvement of the utility model is that after the passivation layer is plated, a conductive layer is plated on the upper side of the drain electrode, the conductive layer and the drain electrodeThe drain forms a complementary capacitor C _{Supplement and supplement} Then the potential of the conductive layer is opposite to the potential of the grid electrode of the TFT array substrate at any time. Parasitic capacitance C exists between drain electrode and gate electrode of TFT device _gd Therefore, the coupling effect of the grid electrode to the drain electrode and the coupling effect of the conducting layer to the drain electrode are mutually offset, so that the voltage difference generated between the pixel electrode and the drain electrode is reduced, the voltage jump of the pixel electrode is reduced, and the purpose of reducing the feed through voltage is achieved. The signal of the first row of grid electrodes is provided by a first CK signal wire, the signal of the second row of grid electrodes is provided by a second CK signal wire, the signal of the first row of conducting layers is provided by a third CK signal wire, and the signal of the second row of conducting layers is provided by a fourth CK signal wire; when supplementing capacitor C _{Supplement and supplement} And parasitic capacitance C _gd When the magnitudes of the signals are uniform, the feedback voltage caused by the signal change of the grid electrode can be eliminated. The capacitance C can be supplemented by regulating the positive area and the film distance between the conductive layer and the drain electrode _{Supplement and supplement} And parasitic capacitance C _gd Is uniform in size.

Under the control of the first CK signal wiring, the second CK signal wiring, the third CK signal wiring and the fourth CK signal wiring, the first row of TFT devices and the second row of TFT devices of the liquid crystal display screen are turned on and off successively, so that the first row of pixels and the second row of pixels of the display screen are set to brightness successively, and the liquid crystal display screen displays stably row by row.

In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.

Referring to fig. 1 to 8.16, a preferred embodiment of the present utility model.

An array substrate for reducing a feedthru voltage, comprising:

a glass substrate 1;

a first metal layer plated on the upper surface of the glass substrate 1 to form a gate 2, a first CK signal trace 31 (CK 1), a second CK signal trace 32 (CK 2), a third CK signal trace 33 (CK 3) and a fourth CK signal trace 34 (CK 4) which are distributed at intervals, wherein the potential of the first CK signal trace 31 is opposite to that of the third CK signal trace 33, the potential of the second CK signal trace 32 is opposite to that of the fourth CK signal trace 34, and the gate 2 is divided into a first row gate 21 and a second row gate 22;

a gate insulating layer 4 plated on the upper surfaces of the glass substrate 1 and the first metal layer, wherein a first hole 41, a second hole 42, a third hole 43 and a fourth hole 44 are formed in the gate insulating layer 4 outside the surface of the pixel display region 11, the first row of gates 21 are exposed in the first hole 41, the second row of gates 22 are exposed in the second hole 42, the first CK signal trace 31 is exposed in the third hole 43, and the second CK signal trace 32 is exposed in the fourth hole 44;

an active layer 5 plated on the upper surface of the gate electrode 2 insulating layer, wherein the active layer 5 is positioned right above the gate electrode 2 and also positioned in the plane of the pixel display area 11;

the second metal layer is plated on the upper surface of the gate insulating layer 4, and source electrodes 6, drain electrodes 7, first signal connection lines 81 and second signal connection lines 82 are formed in an interval distribution, wherein the source electrodes 6 are connected with the left end of the active layer 5, the drain electrodes 7 are connected with the right end of the active layer 5, the source electrodes 6 and the drain electrodes 7 are all positioned in the pixel display area 11, the right end of the first signal connection lines 81 penetrate through the first hole 41 to be connected with the first row grid 21, the left end of the first signal connection lines 81 penetrate through the third hole 43 to be connected with the first CK signal wiring 31, the right end of the second signal connection lines 82 penetrate through the second hole 42 to be connected with the second row grid 22, and the left end of the second signal connection lines 82 penetrate through the fourth hole 44 to be connected with the second CK signal wiring 32;

a passivation layer 9 plated on the upper surfaces of the gate insulating layer 4, the active layer 5 and the second metal layer, wherein a fifth hole 91 and a sixth hole 92 are formed in the passivation layer 9 outside the surface of the pixel display region 11, a seventh hole 93 is formed in the surface of the pixel display region 11, the fifth hole 91 and the sixth hole 92 penetrate through the gate insulating layer 4, the third CK signal trace 33 is exposed from the fifth hole 91, the fourth CK signal trace 34 is exposed from the sixth hole 92, and the drain 7 is exposed from the seventh hole 93;

the conductive layer 10 is plated on the upper surface of the passivation layer 9 and is further located right above the drain electrode 7, the conductive layer 10 is divided into a first row conductive layer 101 and a second row conductive layer 102, a third signal connection line 83 and a fourth signal connection line 84 are plated on the upper surface of the passivation layer 9, the first row conductive layer 101 is connected with the right end of the third signal connection line 83, the left end of the third signal connection line 83 passes through the fifth hole 91 and is connected with the third CK signal trace 33, the second row conductive layer 102 is connected with the right end of the fourth signal connection line 84, and the left end of the fourth signal connection line 84 passes through the sixth hole 92 and is connected with the fourth CK signal trace 34;

and a pixel electrode 20 plated on the upper surface of the passivation layer 9, wherein a lead of the pixel electrode 20 is connected with the drain electrode 7 through the seventh hole 93.

In the utility model, a conductive layer 10 is arranged above a drain electrode 7, a complementary capacitance is formed between the conductive layer 10 and the drain electrode 7, a signal of a first row of grid electrodes 21 is provided by a first CK signal wire 31, a signal of a second row of grid electrodes 22 is provided by a second CK signal wire 32, a signal of a first row of conductive layers 101 is provided by a third CK signal wire 33, a signal of a second row of conductive layers 102 is provided by a fourth CK signal wire 34, and in the same row of TFT devices, the potential of the conductive layer 10 is opposite to the potential of the grid electrode 2, the coupling effect of the grid electrode 2 on the drain electrode 7 and the coupling effect of the conductive layer 10 on the drain electrode 7 are mutually offset, so that the voltage difference generated between a pixel electrode 20 and the drain electrode 7 is reduced, the Feedthrough voltage is reduced, and when the complementary capacitance and the parasitic capacitance are equal, the Feedthrough voltage is eliminated; effectively prevent V of the common electrode 50 in an ideal state _com The point position deviates from the center position of the positive and negative deflection voltages actually provided; the voltage values at two ends of the liquid crystal in the positive and negative polarity states are kept the same, and the deflection angles of the liquid crystal in the positive and negative polarities are the same, so that the light quantity of the array substrate is the same, and the picture of the liquid crystal display is stable.

Under the control of the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33 and the fourth CK signal wiring 34, the first row TFT devices and the second row TFT devices of the liquid crystal display screen are turned on and off successively, so that the first row pixels and the second row pixels of the display screen are set to brightness successively, and the liquid crystal display screen displays stably row by row.

The conductive layer 10 is disposed near the position where the drain electrode 7 contacts the active layer 5, and the field strength of the position is larger, so that the schottky barrier formed by the contact of the semiconductor of the active layer 5 and the metal line of the drain electrode 7 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

Further comprises: the second metal layer also forms TP traces 30 that are spaced apart;

an outer insulating layer 40 plated on the upper surfaces of the pixel electrode 20, the conductive layer 10 and the passivation layer 9, wherein an eighth hole 401 is formed in the surface of the pixel display region 11 in the outer insulating layer 40, the eighth hole 401 penetrates through the passivation layer 9, and the TP trace 30 is exposed out of the eighth hole 401;

and a common electrode 50 plated on the upper surface of the outer insulation layer 40, wherein the lead wire of the common electrode 50 is connected with the TP trace 30 through the eighth hole 401. One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 20, and the other end is connected to the common electrode 50. The full name of TP wiring is Touch Panel Senser Line; the TP trace 30 provides a voltage signal to the common electrode 50.

The signal timing phase of the first CK signal trace 31 is one-quarter cycle earlier than the signal timing phase of the second CK signal trace 32, and the signal timing phase of the third CK signal trace 33 is one-quarter cycle earlier than the signal timing phase of the fourth CK signal trace 34. When the first CK signal wiring 31 drives the gate electrode 2 of the first row TFT device to a high potential, the source electrode 6 and the drain electrode 7 of the first row TFT device are turned on, a data voltage signal is written to the pixel electrode 20, and after a quarter period of time, the second CK signal wiring 32 drives the gate electrode 2 of the second row TFT device to a high potential, the source electrode 6 and the drain electrode 7 of the second row TFT device are turned on, and a data voltage signal is written to the pixel electrode 20. When the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, and when the first CK signal wiring 31 is at a low potential, the third CK signal wiring 33 is at a high potential; the potential of the second CK signal wiring 32 is the same as that of the fourth CK signal wiring 34. The array substrate causes the display screen to be sequentially lighted from top to bottom or bottom to top of the pixels of one row under the control of the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34. For example, when the first CK signal trace 31 is 10V, the third CK signal trace 33 is-15V; when the first CK signal trace 31 is at-15V, the third CK signal trace 33 is at 10V.

And a driving IC connected to the first, second, third, and fourth CK signal wirings 31, 32, 33, and 34. The driving ICs are used to give different timing signals to the first CK signal wiring 31, the second CK signal wiring 32, the third CK signal wiring 33, and the fourth CK signal wiring 34.

The first metal layer is any one of an MO/AL/MO three-layer structure, a Ti/AL/Ti three-layer structure, an AL/MO double-layer structure and an AL/Ti double-layer structure, and the second metal layer is an MO/AL/MO three-layer structure or a Ti/AL/Ti three-layer structure.

The gate insulating layer 4 is of SiOx single-layer structure or SiNx/SiOx double-layer structure, and the passivation layer 9 is of SiO ₂ The outer insulating layer 40 is made of SiOx, siNO or SiNx.

The active layer 5 is made of IGZO, and the conductive layer 10, the pixel electrode 20 and the common electrode 50 are made of ITO. The third signal connection line 83 and the fourth signal connection line 84 are also made of ITO.

The utility model relates to an array substrate capable of reducing the feed through voltage, which adopts the working principle that:

in this embodiment, the design of the single-sided transfer 4CK is taken as an example (note that the circuit design of the present utility model is not limited to the single-sided transfer 4CK, but may be double-sided transfer), the timing chart is shown in fig. 6, fig. 4 is a circuit diagram corresponding to all pixel TFTs in the first row in fig. 3, and fig. 5 is a circuit diagram corresponding to all pixel TFTs in the second row in fig. 3. In short, the display of the picture is realized by sequentially lighting pixels of a row from top to bottom or from bottom to top. And pixelsThe pixel TFT device of the row is required to be turned on with the corresponding gate electrode 2 at a high potential, then the TFT device is turned on, and a data signal is written to the pixel electrode 20, thereby controlling the liquid crystal to twist, and the pixel is turned on. Taking the first row of pixels as an example, when the first CK signal wiring 31 is at a high potential, the third CK signal wiring 33 is at a low potential, the high potential of the first CK signal wiring 31 is transferred to the first row gate 21, the TFT devices of the first row are turned on, the pixel electrode 20 is signal-written, and the low potential of the third CK signal wiring 33 is transferred to the conductive layer 10 of the first row; when the first CK signal trace 31 is switched to a low potential, the third CK signal trace 33 is switched to a high potential, the gate 2 is switched to a low potential from a high potential, and the parasitic capacitance formed by the gate 2 and the drain 7 will have a coupling effect, so as to pull down the voltage of the drain 7, but since the third CK signal trace 33 is switched to a high potential from a low potential at this time, that is, the conductive layer 10 of the first row is switched to a high potential from a low potential, the complementary capacitance formed by the conductive layer 10 and the drain 7 will also have a coupling effect, so as to pull up the voltage of the drain 7, so that the voltage of the drain 7 will not change due to the jump of the gate 2, that is, the voltage of the pixel electrode 20 will not change. Note that the design here requires C _{Supplement and supplement} And C _gs Equal in magnitude, the purpose of this design is to have an increased and decreased two feedthru voltages at the drain 7 and equal in magnitude. Similarly, the TFT devices of each row can avoid the Feedthrough voltage caused by the production jump of the gate 2.

At the microscopic level, it is the migration of charges between the drain electrode 7 and the pixel electrode 20 that causes a change in the amount of charges stored on the pixel electrode 20 and thus a change in voltage. After the pixel electrode 20 is charged, the electric potential between the drain electrode 7 and the pixel electrode 20 is equal, and no electron transfer occurs between them, but since the voltage of the gate electrode 2 is switched from a high potential to a low potential at this moment, the change is coupled to the drain electrode 7 through the parasitic capacitance formed by the gate electrode 2 and the drain electrode 7, and a voltage difference is generated between the drain electrode 7 and the pixel electrode 20, so that the electric charge transfer occurs between the drain electrode 7 and the pixel electrode 20, and the pixel electrode 20 is changed. The utility model is thatThe starting point for solving this problem is to add a conductive layer 10, which conductive layer 10 and drain electrode 7 form a supplemental capacitance C _{Supplement and supplement} Then, opposite potential signals are respectively given to the first row gate electrode 21 and the first row conductive layer 101 through the first CK signal wiring 31 and the third CK signal wiring 33, opposite potential signals are respectively given to the second row gate electrode 22 and the second row conductive layer 102 through the second CK signal wiring 32 and the fourth CK signal wiring 34, so that the coupling effect of parasitic capacitance and complementary capacitance is offset, and the working performance of the device is improved.

A manufacturing method of an array substrate for reducing a feed through voltage comprises the following steps:

s1, referring to FIG. 8.1, a first metal layer is plated on the upper surface of a glass substrate 1 to form a grid electrode 2, a first CK signal wire 31, a second CK signal wire 32, a third CK signal wire 33 and a fourth CK signal wire 34 which are distributed at intervals, wherein the potential of the first CK signal wire 31 is opposite to that of the third CK signal wire 33, the potential of the second CK signal wire 32 is opposite to that of the fourth CK signal wire 34, and the grid electrode 2 is divided into a first row grid electrode 21 and a second row grid electrode 22;

the gate 2 is used for turning on and off the TFT device, the first CK signal wire 31 is used for transmitting the first row gate 21 signal, the second CK signal wire 32 is used for transmitting the second row gate 22 signal, the third CK signal wire 33 is used for transmitting the first row conductive layer 101 signal, and the fourth CK signal wire 34 is used for transmitting the second row conductive layer 102 signal; the material of the first metal layer can be selected from MO/AL/MO three-layer structure, ti/AL/Ti three-layer structure, AL/MO double-layer structure (MO as top layer), AL/Ti double-layer structure (Ti as top layer), etc., and PVD film is formed. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, by using the small expansion coefficient of MO or Ti, the deformation of AL in a high-temperature process can be restrained, and the oxidation of AL can be prevented.

S2, referring to FIGS. 8.2 to 8.4, plating a gate insulating layer 4 on the upper surfaces of the glass substrate 1 and the first metal layer, wherein a first hole 41, a second hole 42, a third hole 43 and a fourth hole 44 are formed in the surface of the pixel display area 11 of the gate insulating layer 4, the first row grid 21 is exposed out of the first hole 41, the second row grid 22 is exposed out of the second hole 42, the first CK signal trace 31 is exposed out of the third hole 43, and the second CK signal trace 32 is exposed out of the fourth hole 44;

the gate insulating layer 4 serves as an insulating medium and also serves as a capacitance medium between the gate electrode 2 and the active layer 5, and is formed by CVD using a SiOx single layer or a SiNx/SiOx double layer. Considering that the requirements of TFT devices at present are fast reaction and low power consumption, and these are all achieved by shrinking TFT devices, and in order to achieve miniaturization of the devices, a suitable high-K material (such as HfO 2) needs to be selected for the gate insulating layer 4, but considering that the interface of HfO2 has more defects, if the interface is directly contacted with the active layer 5 or the gate 2 metal, the stability of the devices may be affected, so that SiOx or SiNx with a relatively good interface may be considered (SiNx can only be used as a contact film layer with the gate metal layer, if as a contact surface with IGZO, H remained in the SiNx film layer during film forming may destroy IGZO characteristics) serving as a contact surface, such as SiOx/HfO2/SiOx three-layer structure needs to be relatively larger in thickness in the SiOx three-layer structure in order to ensure that the advantage of representing the high-K material is guaranteed.

The first hole 41, the second hole 42, the third hole 43, and the fourth hole 44 are dug in the gate insulating layer 4 by dry etching.

S3, referring to FIG. 8.5, plating an active layer 5 on the upper surface of the gate insulating layer 4, wherein the active layer 5 is positioned right above the grid electrode 2 and is also positioned in the plane of the pixel display area 11;

the material of the active layer 5 is selected from metal oxide semiconductors such as IGZO, and PVD is performed by wet etching.

S4, in FIGS. 8.6 to 8.8, plating a second metal layer on the upper surface of the gate insulating layer 4 to form source electrodes 6, drain electrodes 7, first signal connection lines 81 and second signal connection lines 82 which are distributed at intervals, wherein the source electrodes 6 are connected with the left end of the active layer 5, the drain electrodes 7 are connected with the right end of the active layer 5, the source electrodes 6 and the drain electrodes 7 are both positioned in the surface of the pixel display area 11, the right end of the first signal connection lines 81 passes through the first digging holes 41 to be connected with the first row grid electrodes 21, the left end of the first signal connection lines 81 passes through the third digging holes 43 to be connected with the first CK signal traces 31, the right end of the second signal connection lines 82 passes through the second digging holes 42 to be connected with the second row grid electrodes 22, and the left end of the second signal connection lines 82 passes through the fourth digging holes 44 to be connected with the second CK signal traces 32;

the material of the second metal layer can be selected from MO/AL/MO lamination, ti/AL/Ti lamination, PVD film forming and acid wet etching. The resistance of AL is small and is used for conducting electricity (Cu can be used for replacing the AL), so that the impedance can be reduced, and the power consumption can be reduced; secondly, the expansion coefficient of the outer metal MO or Ti is smaller, so that the deformation of the AL in a high-temperature process can be restrained, and the oxidation of the AL can be prevented.

S5, referring to FIGS. 8.9 to 8.11, plating a passivation layer 9 on the upper surfaces of the gate insulating layer 4, the active layer 5 and the second metal layer, wherein a fifth hole 91 and a sixth hole 92 are formed in the passivation layer 9 outside the surface of the pixel display area 11, and a seventh hole 93 is formed in the surface of the pixel display area 11;

the fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched simultaneously, the gate insulating layer 4 is continuously etched downwards until the third CK signal trace 33 is exposed after the passivation layer 9 is etched at the position of the fifth hole 91, the gate insulating layer 4 is continuously etched downwards until the fourth CK signal trace 34 is exposed after the passivation layer 9 is etched at the position of the sixth hole 92, and the outer metal of the drain electrode 7 is continuously etched after the passivation layer 9 is etched at the position of the seventh hole 93; since the fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched at the same time, the depth of etching the metal of the outer layer of the drain electrode 7 at the position of the seventh hole 93 is equal to the depth of etching the gate insulating layer 4 by the fifth hole 91.

The advantage of selecting the fifth hole 91, the sixth hole 92 and the seventh hole 93 to be etched simultaneously here is that one photomask is saved; the disadvantage is that MO or Ti of the drain electrode 7 is lost, and the AL may be oxidized when exposed to air, resulting in a problem of larger contact resistance.

Since the position of the drain electrode 7 is higher than the position of the third CK signal wiring 33, when the fifth hole 91, the sixth hole 92, and the seventh hole 93 are selected to be etched simultaneously, the fifth hole 91 and the sixth hole 92 reach the upper surface of the gate insulating layer 4 when the seventh hole 93 reaches the upper surface of the drain electrode 7; when the fifth hole 91 and the sixth hole 92 continue to etch down to the upper surfaces of the third CK signal trace 33 and the fourth CK signal trace 34, respectively, the seventh hole 93 also continues to etch down to the same depth, which may cause the MO/AL/MO three-layer structure or the outer protective metal MO or Ti of the Ti/AL/Ti three-layer structure of the drain electrode 7 to be missing, and AL may be exposed to air and oxidized, resulting in a larger contact resistance.

The material of the passivation layer 9 is selected to be SiO ₂ And (5) forming a film by CVD. The fifth cutout 91 serves to provide a connection of the third CK signal trace 33 to the first row conductive layer 101, the sixth cutout 92 serves to provide a connection of the fourth CK signal trace 34 to the second row conductive layer 102, and the seventh cutout 93 serves to provide a connection of the pixel electrode 20 and the drain electrode 7.

S6, referring to fig. 8.12 to 8.14, the conductive layer 10, the third signal connection line 83, the fourth signal connection line 84 and the pixel electrode 20 are plated on the upper surface of the passivation layer 9, the conductive layer 10 is located right above the drain electrode 7, the conductive layer 10 is divided into a first row of conductive layers 101 and a second row of conductive layers 102, the first row of conductive layers 101 is connected with the right end of the third signal connection line 83, the left end of the third signal connection line 83 passes through the fifth hole 91 to be connected with the third CK signal trace 33, the second row of conductive layers 102 is connected with the right end of the fourth signal connection line 84, the left end of the fourth signal connection line 84 passes through the sixth hole 92 to be connected with the fourth CK signal trace 34, and the lead wire of the pixel electrode 20 passes through the seventh hole 93 to be connected with the drain electrode 7.

The conductive layer 10 is a channel that does not cover to the active layer 56; the materials of the conductive layer 10 and the pixel electrode 20 are selected from ITO, mainly because ITO has good conductivity and light transmittance, PVD film formation, and wet etching with acid solution. The conductive layer 10 is required to be designed right above the drain electrode 7, so that the conductive layer 10 and the drain electrode 7 form a complementary capacitance, and the size of the complementary capacitance is required to be consistent with the size of parasitic capacitance formed by the gate electrode 2 and the drain electrode 7, and the size of the complementary capacitance can be equal by regulating the positive area and the film layer distance of the conductive layer 10.

The method also comprises the following steps:

referring to fig. 8.6, in S4, the second metal layer further forms TP traces 30 that are distributed at intervals;

s7, referring to FIG. 8.15, plating an outer insulating layer 40 on the upper surfaces of the pixel electrode 20, the conductive layer 10 and the passivation layer 9, wherein an eighth hole 401 is formed in the surface of the pixel display region 11 on the outer insulating layer 40, the eighth hole 401 penetrates through the passivation layer 9, and the TP wiring 30 is exposed out of the eighth hole 401;

the material of the outer insulating layer 40 may be SiOx, siNO, siNx or the like, and CVD film is formed. The eighth hole 401 is obtained by dry etching through the outer insulating layer 40 and the passivation layer 9 until the TP trace 30 is exposed, in order to provide a junction of the common electrode 50 and the TP trace 30.

S8, referring to fig. 8.16, a common electrode 50 is plated on the upper surface of the outer insulating layer 40, and the lead wire of the common electrode 50 is connected to the TP trace 30 through the eighth hole 401.

The material of the common electrode 50 is selected to be ITO mainly because ITO has good conductivity and light transmittance, PVD film formation, acid wet etching.

One end of the liquid crystal Cst of the liquid crystal display is connected to the pixel electrode 20, and the other end is connected to the common electrode 50. The full name of TP trace 30 is Touch Panel Senser Line; the TP trace 30 provides a voltage signal to the common electrode 50.

In another implementation manner of this embodiment, in the step S5, the etching manner of the fifth hole 91, the sixth hole 92 and the seventh hole 93 is replaced with: the fifth hole 91, the sixth hole 92 and the seventh hole 93 are etched simultaneously in the passivation layer 9 until the fifth hole 91 and the sixth hole 92 are exposed out of the gate insulating layer 4 and the seventh hole 93 are exposed out of the drain electrode 7, then the seventh hole 93 is stopped being etched, and then the fifth hole 91 and the sixth hole 92 are continuously etched simultaneously until the third CK signal trace 33 is exposed out of the fifth hole 91 and the fourth CK signal trace 34 is exposed out of the sixth hole 92. The advantage here is that drain 7 does not have the problem of oxidation of AL due to MO or Ti deficiency and increased resistance; the disadvantage is that since the sixth hole 92 and the seventh hole 93 are etched twice, this is one more etching process and one mask cost.

While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the utility model, and that equivalent modifications and variations of the utility model in light of the spirit of the utility model will be covered by the claims of the present utility model.

Claims

1. An array substrate for reducing a feedthru voltage, comprising:

a glass substrate;

2. The array substrate for reducing a feedthru voltage of claim 1 further comprising:

3. The array substrate for reducing a feedback voltage according to claim 1, wherein a signal timing phase of the first CK signal trace is one quarter cycle earlier than a signal timing phase of the second CK signal trace, and a signal timing phase of the third CK signal trace is one quarter cycle earlier than a signal timing phase of the fourth CK signal trace.

4. The array substrate for reducing a feedback voltage according to claim 3, further comprising a driving IC, wherein the driving IC is connected to the first, second, third, and fourth CK signal wirings.

5. The array substrate for reducing a feedback voltage according to claim 2, wherein the first metal layer is any one of MO/AL/MO triple layer structure, ti/AL/Ti triple layer structure, AL/MO double layer structure, and AL/Ti double layer structure, and the second metal layer is MO/AL/MO triple layer structure or Ti/AL/Ti triple layer structure.

6. The array substrate for reducing a feed through voltage according to claim 2, wherein the gate insulating layer is a SiOx single-layer structure or a SiNx/SiOx double-layer structure, and the passivation layer is SiO ₂ The outer insulating layer is made of SiOx, siNO or SiNx.

7. The array substrate for reducing a feedback voltage according to claim 2, wherein the active layer is IGZO material, and the conductive layer, the pixel electrode and the common electrode are all ITO material.