CN219266827U - DDS-based dual-channel radar arbitrary waveform signal generator - Google Patents

Abstract

The utility model relates to the technical field of radar waveform generation, in particular to a DDS-based dual-channel radar arbitrary waveform signal generator. Including: control module, clock module, waveform generation module, filter output module, interface module and power supply module. The utility model controls two AD9910 chips by FPGA to realize dual-channel arbitrary waveform output at a frequency of 400MHz, and the output waveform quality is good after the signal passes through a low-pass filter circuit. Moreover, the overall design has a variety of output waveforms, a simple design structure, flexible operation, and strong versatility, and can realize signal generation functions under various radar backgrounds.

Description

DDS-Based Dual-Channel Radar Arbitrary Waveform Signal Generator

technical field

The utility model relates to the technical field of radar waveform generation, in particular to a DDS-based dual-channel radar arbitrary waveform signal generator.

Background technique

With the continuous development of radar technology, various radars emerge in an endless stream, and continue to play an important role in military and civilian applications. As an important component in the radar system, the radar signal generator's performance quality directly affects the accuracy of the radar's target detection results. According to different application scenarios of radar, the requirements of radar waveforms to be generated are different. According to the radar waveform requirements, the radar signal generator needs to be specially customized, resulting in a long radar development cycle and high development costs. Therefore, it is very meaningful to develop a general-purpose radar signal generator that can generate arbitrary waveforms.

For a long time, the research on radar signal waveform generator has been very hot. For example, in 2005, Lei Xiaohua of the University of Electronic Science and Technology of China published a paper using FPGA to control AD9854 to design a LFMCW radar waveform generator, and two AD9854s were used to generate LFMCW radar waveform signals and radar target echo analog signals respectively. However, since the waveform data in the system design is pre-calculated and stored in the ROM, instead of being generated in real time by a special waveform data operation circuit, the types of waveforms output by the waveform generator are limited and can only be used to generate linear FM continuous wave signal.

In 2009, Liu Lulu of Xidian University used FPGA to control AD9854 chip to design a high-precision, high-purity practical digital frequency synthesis signal generator in a paper published. The combination of software and hardware realizes the system waveform output, which greatly improves the system flexibility. However, due to the constraints of the inherent ROM capacity of the AD9854 chip itself, the non-ideal characteristics of the D/A converter, and the upper limit of the output frequency, etc. , making the system waveform output spurs larger.

In 2011, Xu Qing of the University of Electronic Science and Technology of China published a paper "Design and Implementation of Ka-band Radar Intermediate Frequency Signal Source Module", which provided a frequency synthesis scheme based on DDS chip AD9910, phase-locked loop, frequency multiplier and other components to generate Spot and sweep signals. In this scheme, the FPGA controls the AD9910 chip to generate an intermediate frequency signal, and then the signal frequency is multiplied to the Ka band through the subsequent frequency multiplication circuit. However, the design of this scheme only uses the single-frequency and digital ramp modes of the AD9910 chip, and the types of waveforms generated are relatively single, and arbitrary waveform signals cannot be generated.

In 2015, Wang Shiyou of Xidian University published a paper "Design and Realization of Multifunctional MIMO Radar Signal Source", which provided a multi-channel waveform output design scheme based on multi-chip AD9910. The main output waveforms are linear frequency modulation signal and bi-phase coded signal. Receive and analyze waveform parameters through Ethernet, and control multiple AD9910 chips to output multi-channel waveforms through FPGA. The filter output circuit provided in the thesis uses the integrated low-pass filter chip SCLF-380 and the power amplifier chip ADL5536 for waveform filtering and amplification.

In 2018, the application publication number is CN 209375583 U, and the patent application titled "A 300MHz Sine Wave Signal Generating Circuit" discloses a signal generator design architecture based on a single-chip microcomputer and AD9910 chip. First of all, this design method controls the DDS chip through the STM32F103RGT6 chip to achieve a sine wave output with a frequency below 300MHz. The design circuit structure of the single-chip microcomputer is simple and the cost is low. However, due to the limitation of the number of pins of the single-chip microcomputer, this method can only design a single-channel waveform output, and the use of the single-chip microcomputer as the core control module will limit the speed of waveform switching and data processing. Moreover, the design method is further used to generate a sine wave signal, and the output signal waveform has a single type.

In 2021, the paper "Design and Development of a Multifunctional Radar Signal Generator" published by Zhang Hong of the University of Electronic Science and Technology of China provides a design scheme for receiving waveform commands through the host computer and controlling AD9910 through FPGA to generate multiple radar waveform outputs. . The output waveform frequency range of the scheme is within 160MHz, and the output waveform type can be modulated according to the requirements of the host computer. The output waveform of this design method is relatively flexible, but because the filter circuit designed in this scheme is an elliptic filter circuit with a passband frequency of 160MHz and a stopband attenuation of 70dB, the frequency range of the output waveform is relatively limited by the filter circuit. And the design scheme receives the waveform control command of the upper computer as serial port reception.

That is, in the prior art, the types of radar waveforms generated are relatively single, and arbitrary waveform signals cannot be generated.

Contents of the invention

In order to overcome at least to a certain extent the problem that the types of radar waveforms generated in the related art are relatively single and cannot generate arbitrary waveform signals, the utility model provides a dual-channel radar arbitrary waveform signal generator based on DDS.

The scheme of the present utility model is as follows:

The utility model provides a DDS-based dual-channel radar arbitrary waveform signal generator, including:

Control module, clock module, waveform generation module, filter output module, interface module and power module;

Wherein, the interface module is used to generate waveform commands and arbitrary waveform data;

The control module is used to receive the waveform command and arbitrary waveform data from the interface module, analyze and process the waveform command and arbitrary waveform data, and output the waveform state parameters to the waveform generation module;

The waveform generation module receives the waveform state parameters transmitted from the control module, and outputs an analog signal to the filter output module;

The filter output module receives the analog signal output by the waveform generation module, processes it through the filter output circuit in the filter output module, and outputs an intermediate frequency output signal;

The power supply module is electrically connected to the control module, clock module, waveform generation module, filter output module and interface module respectively; the power supply module is used for the control module, clock module, waveform generation module, filter output module and Interface module power supply;

The clock module is electrically connected with the control module.

Further, the control module includes: an FPGA chip of product model XC7Z015 and a dual-core ARM Cortex-A9 processor.

Further, the waveform generation module includes: two DDS chips, and the product model of the DDS chips is AD9910.

Further, the clock module includes: a clock chip, and the product model of the clock chip used is ADCLK950.

Further, the interface module includes: a PHY chip and a UART serial port level conversion chip, and the product model of the PHY chip is: 88E1111.

Further, the interface module also includes:

Communication with the host computer interface includes: serial port communication and Ethernet communication;

Among them, the serial port communication converts the differential signal into a single-ended signal through the chip MAX3490EESA, and then performs level conversion through the level conversion chip SN74AVC4T245PWR to connect to the FPGA pin; the Ethernet communication converts the interface signal through the transformer HX5004NL and then passes the PHY chip 88E1111 and FPGA The PS side is connected.

Further, the power module includes: a step-down micro-module voltage regulator whose product model is LTM4644.

Further, the filter output module includes: a low-pass filter circuit, and the frequency of the low-pass filter circuit is 400MHz.

The technical solution provided by the utility model can include the following beneficial effects:

The utility model controls two AD9910 chips through the FPGA to realize dual-channel arbitrary waveform output at a frequency of 400 MHz, and the output waveform quality is good after the signal passes through a low-pass filter circuit. Moreover, the overall design output waveforms are diverse, the design structure is simple, the operation is flexible, and the versatility is strong, which can realize the signal generation function under various radar backgrounds.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention.

Description of drawings

The accompanying drawings, which are incorporated in the specification and constitute a part of the specification, illustrate embodiments consistent with the present utility model, and are used together with the specification to explain the principle of the utility model.

Fig. 1 is the structural composition schematic diagram of the dual-channel radar arbitrary waveform signal generator based on DDS that an embodiment of the present invention provides;

Fig. 2 is a system design architecture diagram of the present utility model;

Fig. 3 is FPGA and AD9910 connection schematic diagram among the utility model;

Fig. 4 is a block diagram of system design hardware in the utility model;

Fig. 5 is the circuit diagram of the waveform filter module in the utility model;

Fig. 6 is the pin interface diagram of the network port PHY chip of the utility model;

Fig. 7 is clock circuit design diagram in the utility model;

Fig. 8 is a design diagram of the power supply circuit in the utility model;

Fig. 9 is the connection circuit diagram of FPGA and AD9910 in the utility model;

Fig. 10 is the connection circuit diagram of FPGA and PHY chip in the utility model;

Fig. 11 is the peripheral circuit diagram of two AD9910 in the utility model.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of devices and methods consistent with aspects of the invention as recited in the appended claims.

Embodiment one

Please refer to Fig. 1. Fig. 1 is a schematic diagram of the structural composition of a DDS-based dual-channel radar arbitrary waveform signal generator provided by an embodiment of the present invention, including:

Control module 20, clock module 50, waveform generation module 30, filter output module 40, interface module 10 and power module 60;

Wherein, the interface module 10 is used to generate waveform commands and arbitrary waveform data;

The control module 20 is used to receive the waveform command and the arbitrary waveform data from the interface module 10, and analyze the waveform command and the arbitrary waveform data, and output the waveform state parameters to the waveform generation module 30;

The waveform generation module 30 receives the waveform state parameters transmitted from the control module 20, and outputs an analog signal to the filter output module 40;

The filter output module 40 receives the analog signal output by the waveform generation module 30, processes it through the filter output circuit in the filter output module 40, and outputs an intermediate frequency output signal;

The power supply module 60 is electrically connected with the control module 20, the clock module 50, the waveform generation module 30, the filter output module 40 and the interface module 10 respectively; the power supply module 60 is used for the control module 20, the clock module 50 , the waveform generation module 30, the filter output module 40 and the interface module 10 are powered;

The clock module 50 is electrically connected to the control module 20 .

In specific implementation, please refer to Figure 2 and Figure 4, the generator includes a control circuit electrically connected to each other, a waveform generation circuit, a filter output circuit and a communication interface circuit, wherein the control circuit is used to receive information from the communication The host computer waveform data and waveform control commands of the interface circuit, after analysis and processing, the waveform state parameters to be output are transferred to the waveform generation circuit; the analog signal output by the waveform generation circuit is connected to the filter output circuit, and the signal waveform After being processed by the filter output circuit, it becomes an intermediate frequency output signal with good quality, which is connected to the final analog output terminal for waveform output.

It should be pointed out that the core of the control module 20 in the present invention is an FPGA chip, which has multiple external communication modes such as Ethernet and serial port. FPGA can receive the waveform control command transmitted by the host computer, and also receive the arbitrary waveform data transmitted from the host computer. The command or waveform data received by the FPGA is analyzed and then the waveform output of the DDS chip is controlled. Furthermore, the FPGA chip is selected as XC7Z015, which combines a dual-core ARM Cortex-A9 processor and a traditional field programmable gate array (FPGA) logic component inside, which can be used as the core component of the control module 20 .

On the other hand, the waveform generating module 30 of the present invention includes two DDS chips, and the type of the DDS chip is AD9910. AD9910 is a high-performance DDS chip with a 14-bit DAC, a maximum sampling frequency of 1GHz, a frequency resolution of 0.23Hz, and an output waveform frequency of up to 400MHz. It is equipped with four working modes: single frequency modulation mode, RAM modulation mode, linear ramp modulation mode and parallel data port mode.

Further, referring to Fig. 10 and Fig. 11, the waveform generating circuit of the present invention includes chip AD9910_1, chip AD9910_2, resistor R1, resistor R2, resistor R5, resistor R7, resistor R9, resistor R12, resistor R15, resistor R18 , resistor R19, resistor R22, resistor R24, resistor R29, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C13, capacitor C14, capacitor C15, capacitor C16, light emitting diode D1, light emitting diode D2, light emitting diode D3 and light emitting diode Diode D4; one end of resistor R1 and resistor R18 are respectively connected to the MASTER_RESET pin of AD9910_1 and AD9910_2, and the other end is connected to the ground; one end of resistor R2 and resistor R19 are respectively connected to the SYNC_SMP_ERR pin of AD9910_1 and AD9910_2, and the other end is respectively connected to the light-emitting diode D1 is connected to light-emitting diode D3, and the other ends of light-emitting diode D1 and light-emitting diode D3 are grounded; the PLL_LOOP_FILTER pins of chip AD9910_1 and chip AD9910_2 are respectively connected to capacitor C1, capacitor C2, capacitor C13, capacitor C14, and the other end of capacitor C2 and capacitor C14 Resistor R5 and resistor R22 are connected in series at one end, and the other end of capacitor C1, capacitor C13, resistor R5 and resistor R22 are connected to analog power supply 1.8V; the REF_CLK+ and REF_CLK- pins of chip AD9910_1 are respectively connected to capacitor C3 and capacitor C4, capacitor C3 and the other end of capacitor C4 are respectively connected to the P terminal and N terminal of the reference clock input; the REF_CLK+ and REF_CLK- pins of the chip AD9910_2 are respectively connected to the capacitor C15 and the capacitor C16, and the other ends of the capacitor C15 and the capacitor C16 are respectively connected to the reference clock input The P terminal and N terminal of the chip AD9910_1 and the chip AD9910_2 are grounded through the resistor R7 and the resistor R24 respectively; the PLL_LOCK pins of the chip AD9910_1 and the chip AD9910_2 are respectively connected in series with the light-emitting diode D3 and the light-emitting diode D4 through the resistor R9 and the resistor R26 Grounding; DAC_RSET pins of chip AD9910_1 and chip AD9910_2 are grounded through resistor R12 and resistor R29 respectively; DGND and AGND pins of chip AD9910_1 and chip AD9910_2 are grounded, DVDD33_I/O pin is connected to digital power supply 3.3V, DVDD18 pin is connected to digital power supply 1.8V, AVDD18 is connected to analog power supply 1.8V, AVDD33 is connected to analog power supply 3.3V.

Further, please refer to Fig. 5, the filter output circuit of the present invention includes resistor R10, resistor R11, resistor R13, resistor R14, resistor R27, resistor R28, resistor R30, resistor R31, capacitor C5, capacitor C6, capacitor C7 , capacitor C8, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C17, capacitor C18, capacitor C19, capacitor C20, capacitor C21, capacitor C22, capacitor C23, capacitor C24, inductance L1, inductance L2, inductance L3, inductance L4, inductor L5, inductor L6, balun transformer U34, balun transformer U36, SMA interface U3, SMA interface U5; both ends of resistor R10 and resistor R28 are respectively connected to the IOUT+ and IOUT- pins of chip AD9910_1 and chip AD9910_2; The IOUT+ pin of the chip AD9910_1 is connected in series with the resistor R13 and then grounded, and the IOUT- pin is connected in series with the resistor R14 and then grounded; the IOUT+ pin of the chip AD9910_2 is connected in series with the resistor R30 and grounded, and the IOUT- pin is connected in series with the resistor R31 and grounded; the balun The pin 4 of the transformer U34 is connected to the IOUT+ of the chip AD9910_1, the pin 6 is connected to the IOUT- of the chip AD9910_1, the pin 2 is connected to the analog ground, the pin 3 is connected to the resistor R11, the pin 1 is connected to the analog ground, and the pin 5 is suspended; the balun The pin 4 of the transformer U36 is connected to the IOUT+ of the chip AD9910_2, the pin 6 is connected to the IOUT- of the chip AD9910_2, the pin 2 is connected to the analog ground, the pin 3 is connected to the resistor R27, the pin 1 is connected to the analog ground, and the pin 5 is suspended; the inductor L1 One end is connected to resistor R11, the other end is connected to inductor L2, one end of inductor L2 is connected to inductor L1, the other end is connected to inductor L3, one end of inductor L3 is connected to inductor L2, and the other end is connected to SMA analog output interface U3; one end of inductor L6 is connected to resistor R11, and the other end is connected to Inductor L4, one end of inductor L4 is connected to inductor L6, the other end is connected to inductor L5, one end of inductor L5 is connected to inductor L4, and the other end is connected to SMA analog output interface U5; one end of capacitor C5 and capacitor C6 is connected to resistor R11, and the other end is connected to analog ground; capacitor C7 One end of capacitor C8 is connected to inductor L1, and the other end is connected to analog ground; one end of capacitor C9 and capacitor C10 is connected to inductor L2, and the other end is connected to analog ground; one end of capacitor C11 and capacitor C12 is connected to inductor L3, and the other end is connected to analog ground; capacitor C17 and capacitor One end of C18 is connected to resistor R27, and the other end is connected to analog ground; one end of capacitor C19 and capacitor C20 is connected to inductor L6, and the other end is connected to analog ground; one end of capacitor C21 and capacitor C22 is connected to inductor L4, and the other end is connected to analog ground; one end of capacitor C23 and capacitor C24 Connect the inductor L5, and connect the other end to the analog ground; the SMA interface U3 and the interface U5 are used as the analog waveform output interfaces of the chip AD9910_1 and the chip AD9910_2 respectively.

Further, please refer to Fig. 3 and Fig. 6, the interface communication between the utility model and the upper computer mainly includes two modes of serial port communication and Ethernet communication; the serial port communication converts the differential signal into a single-ended signal through the chip MAX3490EESA, and then through the level conversion The chip SN74AVC4T245PWR is connected to the FPGA pin for level conversion; the interface signal is converted by the transformer HX5004NL through the Ethernet communication, and then connected to the PS terminal of the FPGA through the PHY chip 88E1111.

Specifically, the core of the control module 20 is FPGA, the waveform generation module 30 includes two AD9910s, the clock chip used by the clock module 50 is ADCLK950, the interface module 10 includes a PHY chip 88E1111 and a UART serial port level conversion chip, and the chip used by the power supply module 60 For two LTM4644. FPGA is connected with two pieces of AD9910 as the control core, and each piece of AD9910 is connected with a set of 400MHz low-pass filter output circuit.

The FPGA chip is XC7Z015, which has abundant IO pins, and internally combines a dual-core ARM Cortex-A9 processor and a traditional field programmable gate array (FPGA) logic unit. The PL logic control part is connected to two pieces of AD9910, and the circuit connection is shown in Figure 9; the PS part is connected to the Ethernet PHY chip, and the circuit connection is shown in Figure 10. It should be noted that the FPGA chip XC7Z015 integrates an ARM system (that is, the PS part) And PL logic control part.

The external input differential clock 120MHz of the system and the clock generated by the internal 120MHz crystal oscillator are buffered and selected by the ADCLK950 chip, and the output clock provides reference clock input for the FPGA and two AD9910s, as shown in Figure 7. After the 120MHz reference clock is sent to AD9910, the clock frequency can be multiplied by the built-in frequency multiplier of the chip to generate the working clock inside the chip.

The core of the waveform generating module 30 is the AD9910 chip, as shown in FIG. 11 . The second pin PLL_LOOP_FILTER of AD9910 uses a third-order RC passive low-pass filter as an external loop filter. Refer to the chip manual to calculate the resistance and capacitance values in the loop filter. AVDD (1.8V) pin of AD9910 chip is connected to analog 1.8V power supply, DVDD (1.8V) pin of AD9910 chip is connected to digital 1.8V power supply, AVDD (3.3V) pin of AD9910 chip is connected to analog 3.3V power supply, AD9910 chip The DVDD33_I/O (3.3V) pin is connected to the digital 3.3V power supply, and the AGND pin and DVDD pin of the AD9910 chip are connected to the power ground. AD9910 has a built-in 14-bit current output DAC, which uses two outputs to ensure the balance of the output current signal. The balanced output reduces potential common-mode noise at the DAC output, providing a higher signal-to-noise ratio. According to the chip design manual, connect an external 10K resistor between DAC_RSET and AGND to establish the reference current. The 80th and 81st pins of AD9910 are analog waveform output pins, which are connected to the low-pass filter output circuit.

FPGA analyzes the command information sent by the upper computer through the UART serial port, and after obtaining the dual-channel waveform parameters to be generated, it controls the CFR1-3 mode control registers of the two AD9910s through the SPI serial interface, so that the two AD9910s work in single-frequency modulation mode, In RAM modulation mode, linear ramp modulation mode, or parallel data mode.

When the target waveform is a single-frequency signal, the single-frequency modulation mode can be preferentially used for generation. The output waveform parameters are provided directly by the programming register of AD9910.

When the target waveform is an arbitrary waveform signal, it can be generated in RAM modulation mode. The RAM modulation mode is divided into two steps of waveform data writing and waveform data playback. When the waveform data is written, the FPGA writes the waveform data to the waveform storage register corresponding to the RAM in the AD9910 through the SPI interface. There are 8 profile registers available inside the AD9910 To store 8 independent time-domain waveforms, different profile registers are controlled and selected through the PROFILE[2:0] pin. Each profile register contains 10-bit waveform start address, 10-bit waveform end address, and 16-bit address step rate control word. The maximum waveform data transmission rate of SPI is 70M. When the waveform data is being played back, the RAM can send the corresponding DDS signal control parameters at a specified rate according to the contents of the profile register. The clock rate of the playback address, that is, the sampling rate of the generated waveform is determined by the 16-bit address step rate control word M. The playback rate is shown in Equation 1 as follows:

Among them, f _sysclk is the chip system clock after frequency multiplication, f _DDSCLOCK represents the waveform playback clock frequency; M is the playback address step rate.

When using the digital ramp mode, the digital ramp limit register, the digital ramp step size register and the digital ramp rate register need to be configured. Digital ramp limit register, address 0x0B, 8 bytes 64 bits. The upper 32 bits are the upper limit value of the digital ramp, the lower 32 bits are the lower limit value of the digital ramp, the destination bit of the digital ramp is set to frequency, and the corresponding limit values are the upper limit frequency and the lower limit frequency respectively. The corresponding relationship between the limit frequency and the FTW value is shown in formula 2:

Among them, FTW is the value of the limit register, and f is the limit frequency.

Digital ramp step register, address 0x0C, 8 bytes 64 bits. The upper 32 bits are the decreasing value of the digital ramp, and the lower 32 bits are the increasing value of the digital ramp. In a chirp signal, the step value is the step frequency at each step interval. The step frequency value is affected by bandwidth, duration and time interval. The stepping frequency and the stepping time interval are shown in Equation 3:

Among them, DFTW is the value of the ramp step register, Δf is the step frequency, BW is the bandwidth, TW is the time width, and Δt is the step time interval.

Digital ramp rate register, address 0x0D, 4 bytes 32 bits. The upper 16 bits are the time interval between two decremented values, and the lower 16 bits are the time interval between two incremented values. When the digital ramp rate register value (DFRRW) is configured as 1, the minimum frequency conversion time interval (Δt) is 4 times the AD9910 system clock period.

When using the parallel data mode, the DDS signal control parameters are directly provided by the 18-bit parallel data port. The data port is divided into two parts, 16-bit data word DATA[15:0] and 2-bit destination word F[1:0]. The data word is waveform data information, and the destination word is used to control whether the waveform data information belongs to amplitude, frequency or phase. Because the parallel transmission rate PDCLK of FPGA and AD9910 can reach up to 250MHz. PDCLK is used as the data clock of the parallel port, so this mode can be used for arbitrary waveform signal generation in high-speed scenarios.

The filter output module 40 adopts a 400MHz low-pass filter circuit design. Since the analog output pins of the AD9910 chip are in the form of differentials, and the general output intermediate frequency signals are single-ended, it is necessary to perform single- and dual-mode output through a balun. The conversion of the end; the balun uses TRE001, the balun frequency input range is 0.4 ~ 800MHz, the maximum insertion loss is 1db in the range of 1 ~ 400MHz, and the impedance is 1:1. The analog signal data interface adopts SMA interface, and the filter output circuit is shown in Figure 5.

The core PHY chip of the Ethernet interface module 10 is 88E1111. The RGMII interface is used to connect with the PS side of the FPGA.

By connecting the 7 pins of CONFIG[6:0] of the PHY chip to external signals, different chip configuration results can be obtained, such as transmission rate, optical fiber, Ethernet interface, etc., and the connection with different external pins also affects With registers, they can be connected with VSS, LED_TX, LED_RX, LED_DUPLEX, LED_LINK1000, LED_LINK100, LED_LINK10, VDDO respectively, which in turn represent the value of 3 bits from 000 to 111, for CONFIG[6:0] corresponding to 3 bits, each bit has its own meaning.

According to the configuration instructions in the chip manual, configure the initialization state of the 88E1111 chip as: address PHY_ADDR[4:0]=11000b, interface mode "RGMII to copper".

The core of the design of the power module 60 is the LTM4644 voltage conversion chip. The power supply voltage used in this novel design includes digital voltage and analog voltage. The waveform signal generation and output process needs to use analog voltage, and the other parts are digital voltage. Chips that need power supply include FPGA chip, two DDS chips AD9910, clock driver chip, etc.

FPGA chip adopts XC7Z015. The required chip pin voltages are 3.3V, 1.0V, 1.2V, 1.5V and 1.8V, a total of 5 voltages. The DDS chip adopts the AD9910 design of ADI Company, and the power requirements of AD9910 are shown in Table 1.

Table 1

AD9910 power supply pin supply voltage AVDD(1.8V) Analog 1.8V AVDD(3.3V) Analog 3.3V DVDD (1.8V) Digital 1.8V DVDD_IO(3.3V) Digital 3.3V

According to the above statistics of the power supply voltage required by each chip, the power supply module 60 can be designed as follows.

In the power circuit design, two LTM4644 power conversion chips are used. The LTM4644 power conversion chip can realize 4-channel voltage conversion and minimize input ripple. The chip has a wide input voltage range: 4V to 14V, output voltage range: 0.6V to 5.5V. The LTM4644 can regulate the output over a wide range of input supply voltages. The regulator also includes output overvoltage and overcurrent fault protection, so it is very suitable to use this power conversion chip for input power conversion.

The first LTM4644 converts the 12V external input power supply into four voltages: 1.2V, 1.8V, 1.5V and 3.3V. The four output channels of the second LTM4644 convert the 12V external input power to 1.0V required by Z7, 1.8V and 3.3V required by DDS, and 2.5V power supply voltage of the PHY chip. The circuit design of the power module 60 is shown in FIG. 8 .

It can be understood that, the same or similar parts in the above embodiments can be referred to each other, and the content that is not described in detail in some embodiments can be referred to the same or similar content in other embodiments.

It should be noted that, in the description of the present utility model, terms such as "first" and "second" are only used for description purposes, and should not be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" means at least two.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments or portions of code comprising one or more executable instructions for implementing specific logical functions or steps of the process , and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order depending on the functions involved, which It should be understood by those skilled in the art to which the embodiments of the present invention belong.

It should be understood that each part of the present invention can be realized by hardware, software, firmware or their combination. In the embodiments described above, various steps or methods may be implemented by software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques known in the art: Discrete logic circuits, ASICs with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

Those of ordinary skill in the art can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. During execution, one or a combination of the steps of the method embodiments is included.

In addition, each functional unit in each embodiment of the present invention can be integrated into one processing module, or each unit can exist separately physically, or two or more units can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structures, materials or features are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and should not be construed as limitations of the present invention, and those skilled in the art are within the scope of the present invention. Variations, modifications, substitutions and variations can be made to the above-described embodiments.

Claims (8)

1. The dual-channel radar arbitrary waveform signal generator based on DDS is characterized in that, comprising: Control module, clock module, waveform generation module, filter output module, interface module and power module; Wherein, the interface module is used to generate waveform commands and arbitrary waveform data; The control module is used to receive the waveform command and arbitrary waveform data from the interface module, analyze and process the waveform command and arbitrary waveform data, and output the waveform state parameters to the waveform generation module; The waveform generation module receives the waveform state parameters transmitted from the control module, and outputs an analog signal to the filter output module; The filter output module receives the analog signal output by the waveform generation module, processes it through the filter output circuit in the filter output module, and outputs an intermediate frequency output signal; The power supply module is electrically connected to the control module, clock module, waveform generation module, filter output module and interface module respectively; the power supply module is used for the control module, clock module, waveform generation module, filter output module and Interface module power supply; The clock module is electrically connected with the control module. 2. The generator according to claim 1, wherein the control module comprises: an FPGA chip of product model XC7Z015 and a dual-core ARM Cortex-A9 processor. 3. The generator according to claim 1, wherein the waveform generating module comprises: two DDS chips, and the product model of the DDS chips is AD9910. 4. The generator according to claim 1, wherein the clock module comprises: a clock chip, and the product model of the clock chip used is ADCLK950. 5. The generator according to claim 1, wherein the interface module comprises: a PHY chip and a UART serial port level conversion chip, and the product model of the PHY chip is: 88E1111. 6. The generator according to claim 1, wherein the interface module further comprises: Communication with the host computer interface includes: serial port communication and Ethernet communication; Among them, the serial port communication converts the differential signal into a single-ended signal through the chip MAX3490EESA, and then performs level conversion through the level conversion chip SN74AVC4T245PWR to connect to the FPGA pin; the Ethernet communication converts the interface signal through the transformer HX5004NL and then passes the PHY chip 88E1111 and FPGA The PS side is connected. 7. The generator according to claim 1, wherein the power supply module comprises: a step-down micro-module voltage regulator whose product model is LTM4644. 8. The generator according to claim 1, wherein the filter output module comprises: a low-pass filter circuit, and the frequency of the low-pass filter circuit is 400MHz.

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