Wide-range voltage self-adaptive frequency detection circuit with isolation
Technical Field
The utility model relates to a frequency sampling circuit who carries out frequency sampling to photovoltaic inverter's output and electric wire netting end belongs to photovoltaic system, photovoltaic inverter technical field.
Background
Because photovoltaic power generation utilizes solar energy to generate power and is pollution-free, the photovoltaic power generation is favored by various countries, and more photovoltaic power stations and energy storage power stations are built. With the increasing power generation of the photovoltaic power station, the input voltage and the output voltage are also continuously increased, the current general input voltage reaches 1500VDC input, the general output voltage reaches 600Vac output, and the output frequency is usually 50HZ or 60HZ. Because the photovoltaic power station needs to be connected to a national power grid in a grid-connected mode, the voltage and frequency of the output end of the photovoltaic inverter and the power grid end need to be sampled, and the same-frequency and same-amplitude phase-locked grid connection is achieved. Due to the continuous improvement of the output voltage, especially the under-voltage tripping of the latest IEEE1547.1-2018 regulation 5.4.3 chapter requires that the voltage setting range reaches 0% -100%, which requires that the sampling range of the output voltage and frequency sampling circuit reaches 0% -100%. It is very difficult for a frequency sampling circuit to realize accurate sampling of frequency in the range of-891V (-Va) to +891V (+ Va), and especially after the output voltage drops below 30% (600 x 0.3 x 1.414=254.52v (+ Vb)) of the rated voltage when IEEE1547.1-2018 regulations require voltage drop, the current sampling circuit cannot sample the frequency signal, especially the output voltage drops to 5% (600 x 0.05 x 1.414=42.42v (+ Vc)) of the rated voltage, and even more, the current sampling circuit cannot meet the requirements of the regulations. The current general frequency sampling circuit can only realize accurate frequency sampling between-254.52V (-Vb) to-Va and + Vb to + Va, cannot realize frequency sampling of output voltage between-Vb to 0V and + Vb to 0V, and is not isolated from high voltage.
Disclosure of Invention
The to-be-solved technical problem of the utility model is: the current frequency sampling circuit is difficult to realize accurate sampling of frequency in the range of-891V (-Va) to +891V (+ Va), and no way is available to meet the requirements of regulations.
In order to solve the technical problem, the technical scheme of the utility model a wide range voltage self-adaptation frequency detection circuit of area isolation is provided, a serial communication port, including at least three isolation amplifying unit, chip selection signal processing unit, passageway chip selection unit, central processing unit, voltage detection unit and the frequency detection unit that has different amplification gains, wherein:
the input ends of all the isolation amplifying units are connected with the voltage frequency signal to be detected, the output ends of all the isolation amplifying units are connected with the input ends of different chip selection channels of the channel chip selection unit, the output ends of the channel chip selection unit are connected with the detection signal input ends of the voltage detection unit and the frequency detection unit, and the detection signal output ends of the voltage detection unit and the frequency detection unit are connected with the data input end of the central processing unit; the instruction output end of the central processing unit is connected with the instruction input end of the chip selection signal processing unit, and the chip selection signal output end of the chip selection signal processing unit is connected with the chip selection signal input end of the channel chip selection unit.
Preferably, the at least three isolation amplifying units are respectively implemented by three independent isolation amplifying circuits.
Preferably, the at least three isolation amplifying units are three different isolation amplifying channels in the same isolation amplifying circuit.
Preferably, the at least three isolation amplifying units are implemented by at least two independent isolation amplifying circuits, and different isolation amplifying channels in all the isolation amplifying circuits are respectively used for implementing different isolation amplifying units.
Preferably, the number of the channel chip selection units is equal to the number of the isolation amplifying circuits.
Preferably, there are three isolation amplifying units, which are respectively defined as a first isolation amplifying unit with an amplification gain of first, a second isolation amplifying unit with an amplification gain of second, and a third isolation amplifying unit with an amplification gain of third, and the gain of first < gain of second < gain of third.
Preferably, the chip selection signal processing unit is implemented based on a logic control chip, or is a chip selection analog circuit, or is a chip selection digital logic circuit.
Preferably, the channel chip selection unit is implemented based on a controllably conductive device.
Preferably, the voltage detection unit is a differential amplification circuit composed of differential operational amplifiers.
Preferably, the frequency detection unit includes a low-pass filtering unit, an inverting and low-pass filtering unit, a comparing unit, and a level converting unit, wherein:
the low-pass filtering unit and the negating and low-pass filtering unit are simultaneously connected with externally input signals, the outputs of the low-pass filtering unit and the negating and low-pass filtering unit are synchronously connected with the comparing unit, after the two signals are compared by the comparing unit, a square wave signal with the same frequency as the detected voltage frequency signal is obtained, the square wave signal is transmitted to the level conversion unit, and the square wave signal is converted into a square wave signal with the level capable of being received by the central processing unit.
The utility model discloses a wide range voltage self-adaptation frequency detection circuit of area isolation can satisfy the requirement that IEEE1547.1-2018 regulation can all realize fine control detection to high-low pressure well, has realized the detection of arbitrary voltage and frequency, no longer receives the restriction of voltage, and the value of Va, vb, vc is not limited to the voltage value that the background art points out promptly. And be in the technical scheme of the utility model, detect output signal end and high pressure and realized insulating the isolation by the detection point, realize the accurate of high-low voltage frequency and detected, realized the sense terminal again and detected the insulating isolation of high-pressure side, satisfied the requirement of new regulation promptly, also improved the steady operation of grid-connected inverter.
Drawings
FIG. 1 is a schematic diagram of a wide range voltage adaptive frequency detection circuit with isolation;
FIG. 2 is a schematic diagram of the frequency detection unit of FIG. 1;
FIG. 3 is a schematic diagram of a second isolation amplifying unit of FIG. 1;
fig. 4 illustrates a detection flow of the wide-range voltage adaptive frequency detection circuit with isolation.
Detailed Description
The present invention will be further described with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Furthermore, it should be understood that various changes or modifications can be made by those skilled in the art after reading the teachings of the present invention, and these equivalents also fall within the scope of the appended claims.
As shown in fig. 1, the wide-range voltage adaptive frequency detection circuit with isolation disclosed in this embodiment includes a first isolation amplifying unit, a second isolation amplifying unit having two isolation amplifying channels, a chip selection signal processing unit, a channel chip selection unit 1, a channel chip selection unit 2, an MCU processing unit, a voltage detection unit, and a frequency detection unit.
With reference to fig. 4, the operation process of the frequency detection circuit is as follows: the detected voltage frequency signals VR and VS simultaneously reach the first isolation amplifying unit and the second isolation amplifying unit through the detection lines. As the voltage of the detected voltage frequency signal is unknown at first, the MCU processing unit sends a chip selection signal to the chip selection signal processing unit, the chip selection signal processing unit gates a channel 1 of the channel chip selection unit 1 through the chip selection signal 1 according to a command of the MCU processing unit, so that a detected voltage frequency signal acquired by the first isolation amplifying unit is amplified by the chip selection signal processing unit, a pin of the 1 unit of the first isolation amplifying unit enters the channel 1, and the voltage frequency signal is output to the voltage detection unit and the frequency detection unit after passing through the channel chip selection unit 1. The detected voltage frequency signal amplified by the first isolation amplifying unit is sent to the MCU processing unit after being subjected to the proportion processing of the voltage detecting unit. The MCU processing unit obtains a detected voltage signal after calculation processing according to a given proportion; meanwhile, after the detected voltage frequency signal amplified by the first isolation amplifying unit is processed by the frequency detecting unit, the MCU processing unit samples the frequency of the detected voltage frequency signal according to the processed signal. If the MCU processing unit finds that the detected voltage signal is more than two times of the preset detection voltage or more, the MCU processing unit turns off all chip selection signals to protect the following detection circuit; if the MCU processing unit finds that the detected voltage signal is between-Vb and-Va or + Vb and + Va, keeping a channel 1 to detect the signal; if the MCU processing unit finds that the detected voltage signal is not between-Vb to-Va and + Vb to + Va and is not higher than + Va and not lower than-Va, a chip selection signal is sent to the chip selection signal processing unit, the chip selection signal processing unit gates a first channel of the channel chip selection unit 2 through the chip selection signal 2 according to the command of the MCU processing unit, the output end of a gain 1 of a second isolation amplification unit is communicated with the input end of the gain 1 to form a loop, namely, a first isolation amplification channel with the amplification gain of 1 in the second isolation amplification unit is selected, the second isolation amplification unit works in the state of gain 1, the second isolation amplification unit working in the state of gain 1 processes the detected voltage frequency signal, and then the detected voltage frequency signal is output to the channel 2 of the channel chip selection unit 1 through a 2 unit output pin of the second isolation amplification unit. The detected voltage frequency signal processed by the second isolation amplifying unit is output to the voltage detecting unit and the frequency detecting unit through the channel 2 of the channel chip selecting unit 1. The detected voltage frequency signal processed by the second isolation amplifying unit working in the gain 1 state is subjected to proportion processing by the voltage detecting unit and then is sent to the MCU processing unit, and the MCU processing unit obtains the detected voltage signal after calculation processing according to the given proportion; meanwhile, after the detected voltage frequency signal processed by the second isolation amplifying unit working in the gain 1 state is processed by the frequency detection unit, the MCU processing unit samples the frequency of the detected voltage frequency signal according to the processed signal. If the MCU processing unit finds that the detected voltage signal is between-Vb and-100V (-Vc) or between +100V (+ Vc) and + Vb, the MCU processing unit sends a chip selection signal to the chip selection signal processing unit, the chip selection signal processing unit gates a channel I of the channel chip selection unit 2 through the chip selection signal 2 according to the command of the MCU processing unit until the voltage range of the detected voltage signal is out of the range between-Vb and-Vc or between + Vc and + Vb, and the voltage range is not more than + Vb and is not lower than-Vb. And then the MCU processing unit sends a chip selection signal to the chip selection signal processing unit again, the chip selection signal processing unit gates a second channel of the channel chip selection unit 2 through the chip selection signal 2 according to a command of the MCU processing unit, so that a second isolation amplifying channel with the amplification gain of 2 in the second isolation amplifying unit is selected to form a loop after the output end of the gain 2 of the second isolation amplifying unit is communicated with the input end of the gain 2, namely the second isolation amplifying channel with the amplification gain of 2 in the second isolation amplifying unit is selected, the second isolation amplifying unit works in the state of gain 2, the detected voltage frequency signal is processed by the second isolation amplifying unit working in the state of gain 2, and then the processed voltage frequency signal is output to the channel 2 of the channel chip selection unit 1 through a 2-unit output pin of the second isolation amplifying unit. The detected voltage frequency signal processed by the second isolation amplifying unit working in the gain 2 state is processed by the voltage detecting unit in proportion and then is sent to the MCU processing unit, and the MCU processing unit obtains the detected voltage signal after calculation processing according to the given proportion; meanwhile, after the detected voltage frequency signal is processed by the frequency detection unit, the MCU processing unit samples the frequency of the detected signal according to the processed signal.
The gain of the first isolation amplifying unit is minimum and corresponds to the voltage and the frequency of the sampling high voltage; the gain 1 of the second isolation amplifying unit is centered and corresponds to the sampling of the intermediate voltage and frequency signals; the gain 2 of the second isolation amplifying unit is maximum, corresponding to the signal sampling of the minimum voltage and frequency. Through the chip selection function of the MCU processing unit, the MCU processing unit can sample the voltage and the frequency of the detected voltage frequency signal under the conditions of high voltage, medium voltage and low voltage, and the first isolation amplification unit and the second isolation amplification unit are used isolation amplification operational amplifiers (for example, an isolation gain amplifier, an isolation linear optical coupler, an isolation amplification device with the same function, or a combination of the isolation device and the amplification device), so that the detected voltage frequency signal and the detection output signal are isolated, and the detection safety of the MCU processing unit is ensured.
The channel chip selection unit 1 and the channel chip selection unit 2 may be low-voltage multiplexing switches, or may be other controllably conductive devices. The chip selection signal processing unit can be a logic control chip, a chip selection analog circuit consisting of an analog resistance-capacitance MOS tube or a triode, and a digital logic circuit. The voltage detection unit can be a differential amplification circuit consisting of differential operational amplifiers, and can also be other circuits with the same amplification function. The MCU processing unit can be a DSP, or control logic detection devices such as a CPLD, an FPGA, a singlechip and the like.
The frequency detection unit may be composed of a low-pass filter, an operational amplifier and a comparator, or may be composed of a filter circuit, an amplifying circuit and a comparing circuit having the same function. As shown in fig. 2, in the present embodiment, the frequency detection unit includes a low-pass filtering unit, an inverting and low-pass filtering unit, a comparing unit, and a level converting unit. The frequency detection unit divides the input signal into two paths: one path enters a low-pass filtering unit for low-pass filtering, and the required low-pass cut-off frequency can be set in advance; the other path enters an inverting and low-pass filtering unit for signal inversion and the same low-pass filtering is carried out, and the required low-pass cut-off frequency can be set in advance. The signal processed by the low-pass filtering unit and the signal processed by the negating and low-pass filtering unit are simultaneously input to the comparing unit, the two signals are compared by the comparing unit to obtain a square wave signal with the same frequency as the frequency signal of the detected voltage, the square wave signal is transmitted to the level converting unit, the square wave signal is converted into a square wave signal with the level capable of being received by the MCU processing unit, the square wave signal is further processed by the MCU processing unit, and the frequency of the detected signal is detected by the MCU processing unit according to the received square wave signal. Because the current general frequency detection circuit does not separately carry out gain processing, when the detected voltage is higher, the comparison unit can work well, but when the detected signal voltage is very low and is lower than 30% of the output voltage of the grid-connected inverter or is close to 0V, the comparison unit is almost close to 0V because the input voltage is very small. In addition, the input end of the comparison unit is often superimposed with a small fluctuation voltage for various reasons, and the differential mode voltage generated by the fluctuation can cause the output of the comparison unit to continuously change or abnormally change, so that the comparison unit cannot normally work. The utility model discloses an amplification unit's first isolation of second isolation amplification channel and second isolation amplification channel adjustment detection signal output's gain, send the comparison unit to after making the voltage of output amplified suitable multiple, the comparison unit just can work well like this, when having solved the detected voltage frequency signal voltage very low, can't detect frequency signal's problem, the isolation and the section function of piece selection have been increased simultaneously, the high pressure that will be detected is kept apart with the detection output signal, the safe operation of the detection unit at back has been guaranteed, the requirement of IEEE1547.1-2018 regulation has been satisfied, photovoltaic power generation system's stability has been improved.
As shown in fig. 3, in the present embodiment, the second isolation amplifying unit includes a second isolation unit (implemented based on an isolation amplifying chip well known to those skilled in the art) shared by the first isolation amplifying channel and the second isolation amplifying channel, and an amplifier U1 (implemented based on an amplifier well known to those skilled in the art, and having 5 pins which are generally non-inverting input terminals, 6 pins which are generally inverting input terminals, and 7 pins which are generally output terminals). The input end of the second isolation unit is connected with the detection voltage frequency signals VR and VS, and the output end of the second isolation unit is connected with the non-inverting input end and the inverting input end of the amplifier U1 through the resistors R1 and R2 respectively. The non-inverting input terminal of the amplifier U1 is grounded AGND via a resistor R3 and a capacitor C1 connected in parallel. The output terminal of the amplifier U1 is connected to the channel 2 of the channel chip unit 1 via the resistor R6. The amplifying resistor R4 and the capacitor C2 which are connected in parallel form a first isolating amplifying channel, the amplifying resistor R5 and the capacitor C3 which are connected in parallel form a second isolating amplifying channel, and the specific values of the gain 1 and the gain 2 depend on the resistance values of the amplifying resistor R4 and the amplifying resistor R5. One end of the first isolation amplifying channel is connected to the inverting input terminal of the amplifier U1, and the other end of the first isolation amplifying channel constitutes the aforementioned gain 1 output terminal, the output terminals of the amplifier U1 are simultaneously led out to serve as the aforementioned gain 1 input terminal and gain 2 input terminal, and the other end of the first isolation amplifying channel and the output terminal of the amplifier U1 are connected to the channel one of the channel chip selecting unit 2. One end of the second isolation amplification channel is connected with the inverting input end of the amplifier U1, the other end of the second isolation amplification channel forms the output end of the gain 2, and the other end of the second isolation amplification channel and the output end of the amplifier U1 are connected with a second channel of the channel chip selection unit 2. Fig. 3 illustrates only a preferred embodiment of the second isolation amplifying unit, and those skilled in the art can implement the second isolation amplifying unit in other circuit configurations according to the teachings of the present invention after reading the present invention. Meanwhile, the second isolation amplifying unit can also be realized by two independent isolation amplifying circuits, wherein the amplifying gain of one isolation amplifying circuit is gain 1, and the amplifying gain of the other isolation amplifying circuit is gain 2.