CN218332402U - Band gap reference source circuit and electronic equipment - Google Patents
Band gap reference source circuit and electronic equipment Download PDFInfo
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- CN218332402U CN218332402U CN202221348553.2U CN202221348553U CN218332402U CN 218332402 U CN218332402 U CN 218332402U CN 202221348553 U CN202221348553 U CN 202221348553U CN 218332402 U CN218332402 U CN 218332402U
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Abstract
The utility model discloses a band gap reference source circuit and electronic equipment, include: the band-gap reference source power supply starting circuit is used for controlling the on-off of the work of the band-gap reference core circuit; the band-gap reference core circuit is used for generating a reference voltage; the utility model utilizes the starting circuit of the band gap reference source power supply to control the start and stop of the work of the band gap reference core circuit, and utilizes the band gap reference core circuit to generate the reference voltage; an additional current loop is arranged to meet the output requirements of the low power supply voltage and the low band-gap voltage of the band-gap reference source circuit; the circuit structure is simple, and the flow sheet production under different processes can be met; meanwhile, the method can be applied to large-scale integrated circuits and low-chip voltage and low-power consumption circuit designs, and the requirements of high-precision chip production processes are met.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, in particular to band gap reference source circuit and electronic equipment.
Background
With the rapid development of large-scale integrated circuits, the chip production process is continuously updated; the voltage of the chip needs to be continuously reduced to realize the design of a low-power consumption circuit, so that the requirements of low voltage and low power consumption are provided for the internal functional module of the chip; at present, most chips adopt a bandgap reference source to provide reference voltages for internal circuit modules of an analog-to-digital converter ADC, a digital-to-analog converter DAC and a serializer deserializer Ser Des.
The minimum power supply voltage of the reference circuit is one of the limits of a single power supply system adopted by a chip, while the existing band-gap reference source voltage is mostly 1.2V, and the power supply voltage is more than 2V; therefore, the conventional bandgap reference source cannot meet the requirements of low power supply voltage and low bandgap output voltage.
SUMMERY OF THE UTILITY MODEL
To the technical problem who exists among the prior art, the utility model provides a band gap reference source circuit and electronic equipment to solve the technical problem that current band gap reference source can't satisfy low supply voltage and low band gap voltage output.
In order to achieve the above purpose, the utility model adopts the technical scheme that:
the utility model provides a band gap reference source circuit, include:
the band-gap reference source power supply starting circuit is used for controlling the on-off of the work of the band-gap reference core circuit;
and the band-gap reference core circuit is used for generating a reference voltage.
Further, the band gap reference source power supply starting circuit comprises an inverter INV1, an inverter INV2, a P-type MOS transistor MP4, a P-type MOS transistor MP5, a P-type MOS transistor MP6, an N-type MOS transistor MN1, an N-type MOS transistor MN2 and a resistor R5;
the input end of the inverter INV1 is connected with the EN port, and the output end of the inverter INV1 is divided into three paths; the first path is connected with the input end of the inverter INV2, the second path is connected with the grid electrode of the P-type MOS tube MP5, and the third path is connected with the grid electrode of the P-type MOS tube MP 6; the output end of the inverter INV2 is connected with the grid electrode of the P-type MOS tube MP 4;
the source electrode of the P-type MOS tube MP4 and the source electrode of the P-type MOS tube MP5 are connected with a VDD port; the drain electrode of the P-type MOS tube MP5 is connected with the source electrode of the P-type MOS tube MP 6; the drain electrode of the P-type MOS tube MP6 is divided into two paths, wherein one path is connected with the drain electrode of the N-type MOS tube MN1, and the other path is connected with the grid electrode of the N-type MOS tube MN 2; the source electrode of the N-type MOS tube MN2 is connected with the first end of the resistor R5;
the drain electrode of the P-type MOS tube MP4 and the drain electrode of the N-type MOS tube MN2 are connected with the first input end of the band-gap reference core circuit; and the grid electrode of the N-type MOS tube MN1 is connected with the second input end of the band-gap reference core circuit.
Furthermore, the source of the N-type MOS transistor MN1 and the second end of the resistor R5 are both connected to GND.
Further, the band gap reference core circuit comprises a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, a PNP triode Q1, a PNP triode Q2, a PNP triode Q3, a PNP triode Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and an operational amplifier A1;
the source electrode of the P-type MOS tube MP1, the source electrode of the P-type MOS tube MP2, the source electrode of the P-type MOS tube MP3 and the first end of the capacitor C1 are all connected with a VDD port;
the drain electrode of the P-type MOS tube MP1, the emitting electrode of the PNP triode Q1 and the second end of the resistor R3 are connected with the negative input end of the operational amplifier A1; the first output end of the band-gap reference source power supply starting circuit, the drain electrode of the P-type MOS tube MP2, the first end of the resistor R1 and the second end of the resistor R2 are connected with the positive input end of the operational amplifier A1; the second end of the resistor R1 is connected with an emitting electrode of the PNP triode Q2;
the second output end of the band-gap reference source power supply starting circuit, the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP2, the grid electrode of the P-type MOS tube MP3 and the second end of the capacitor C1 are connected with the output end of the operational amplifier A1;
the drain of the P-type MOS transistor MP3 and the second terminal of the resistor R4 are both connected to the VOUT port.
Further, the base of the PNP triode Q1, the collector of the PNP triode Q1, the base of the PNP triode Q2, the collector of the PNP triode Q2, the first end of the resistor R3, and the first end of the resistor R4 are all connected to GND.
Further, the area ratio of the PNP transistor Q1 to the PNP transistor Q2 is 8.
Further, the lowest supply voltage VDD of the VDD port min Is the sum of the overdrive voltage of the P-type MOS transistor MP1 and the P-type MOS transistor MP2 and the base emitter voltage of the PNP triode Q1.
Further, the operational amplifier A1 includes a P-type MOS transistor MP11, a P-type MOS transistor MP12, a P-type MOS transistor MP13, a P-type MOS transistor MP14, a P-type MOS transistor MP15, a P-type MOS transistor MP16, a transistor NP1, a transistor NP2, a transistor NP3, and a transistor NP4;
the source electrode of the P-type MOS tube MP11, the source electrode of the P-type MOS tube MP12, the source electrode of the P-type MOS tube MP13 and the source electrode of the P-type MOS tube MP16 are all connected with a VDD port; the source of the transistor NP1, the source of the transistor NP2, the source of the transistor NP3 and the source of the transistor NP4 are connected to GND;
the drain electrode of the P-type MOS tube MP11 and the grid electrode of the P-type MOS tube MP11 are both connected with the grid electrode of the P-type MOS tube MP13, and the drain electrode of the P-type MOS tube MP11 is also connected with a current input Ibias port; the drain electrode of the P-type MOS tube MP12, the grid electrode of the P-type MOS tube MP12 and the grid electrode of the P-type MOS tube MP16 are connected, and the drain electrode of the P-type MOS tube MP12 is also connected with the drain electrode of the transistor NP 1; the drain electrode of the P-type MOS tube MP13 is divided into two paths, wherein one path is connected with the source electrode of the P-type MOS tube MP14, and the other path is connected with the source electrode of the P-type MOS tube MP 15; the grid electrode of the P-type MOS tube MP14 is connected with the emitting electrode of the PNP triode Q1, and the grid electrode of the P-type MOS tube MP15 is connected with the drain electrode of the P-type MOS tube MP 2;
the grid of the transistor NP2 and the drain of the transistor NP2 are both connected with the grid of the transistor NP1, and the drain of the transistor NP2 is also connected with the drain of the P-type MOS transistor MP 14; the grid electrode of the transistor NP3 and the drain electrode of the transistor NP3 are connected with the grid electrode of the transistor NP4, and the drain electrode of the transistor NP3 is also connected with the drain electrode of the P-type MOS tube MP 15; the drain of the P-type MOS transistor MP16 and the drain of the transistor NP4 are connected to the OUT port.
Further, the sizes of the P-type MOS transistor MP11, the P-type MOS transistor MP12 and the P-type MOS transistor MP13 are equal.
The utility model also provides an electronic equipment, including electron device and band gap reference source circuit, band gap reference source circuit does a band gap reference source circuit.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model provides a band gap reference source circuit and electronic equipment, utilize band gap reference source power starting circuit control band gap reference core circuit to work the start and stop, utilize band gap reference core circuit to generate reference voltage; the output requirements of low power supply voltage and low band-gap voltage of the band-gap reference source circuit are met by arranging an additional current loop; the circuit structure is simple, and the flow sheet production under different processes can be met; meanwhile, the method can be applied to large-scale integrated circuits and low-chip voltage and low-power consumption circuit designs, and meets the requirements of high-precision chip production processes.
Drawings
Fig. 1 is a structural diagram of a bandgap reference source circuit according to the present invention;
fig. 2 is a circuit diagram of the operational amplifier A1 according to the present invention.
Detailed Description
In order to make the technical problem solved by the present invention, the technical solution and the beneficial effects thereof are more clearly understood, and the following detailed description is made for the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, the utility model provides a band gap reference source circuit, which comprises a band gap reference source power supply starting circuit and a band gap reference core circuit; the band-gap reference source power supply starting circuit is used for controlling the on-off of the band-gap reference core circuit; the band-gap reference core circuit is used for generating reference voltage.
The utility model discloses in, band gap reference source power supply starting circuit, including inverter INV1, inverter INV2, P type MOS pipe MP4, P type MOS pipe MP5, P type MOS pipe MP6, N type MOS pipe MN1, N type MOS pipe MN2 and resistance R5.
The input end of the inverter INV1 is connected with the EN port, and the output end of the inverter INV1 is divided into three paths; the first path is connected with the input end of the inverter INV2, the second path is connected with the grid electrode of the P-type MOS tube MP5, and the third path is connected with the grid electrode of the P-type MOS tube MP 6; the output end of the inverter INV2 is connected to the gate of the P-type MOS transistor MP 4.
The source electrode of the P-type MOS tube MP4 and the source electrode of the P-type MOS tube MP5 are connected with a VDD port; the drain electrode of the P-type MOS tube MP5 is connected with the source electrode of the P-type MOS tube MP 6; the drain electrode of the P-type MOS tube MP6 is divided into two paths, wherein one path is connected with the drain electrode of the N-type MOS tube MN1, and the other path is connected with the grid electrode of the N-type MOS tube MN 2.
The drain electrode of the P-type MOS tube MP4 is connected with the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP2, one end of the capacitor C1 and the output end of the operational amplifier A1 in the band gap reference core circuit; the drain electrode of the N-type MOS tube MN2 is connected with the grid electrode of the P-type MOS tube MP1 in the band gap reference core circuit, the grid electrode of the P-type MOS tube MP2, one end of the capacitor C1 and the output end of the operational amplifier A1;
the grid electrode of the N-type MOS tube MN1 is connected with the positive input end of the operational amplifier A1, the drain electrode of the P-type MOS tube MP2, the resistor R1 and the resistor R2 in the band gap reference core circuit; the source electrode of the N-type MOS tube MN2 is connected with the first end of the resistor R5; the source of the N-type MOS transistor MN1 and the second terminal of the resistor R5 are both connected to GND.
The utility model discloses in, band gap benchmark core circuit, including P type MOS pipe MP1, P type MOS pipe MP2, P type MOS pipe MP3, PNP triode Q1, PNP triode Q2, PNP triode Q3, PNP triode Q4, resistance R1, resistance R2, resistance R3, resistance R4, electric capacity C1 and operational amplifier A1.
The source electrode of the P-type MOS tube MP1, the source electrode of the P-type MOS tube MP2, the source electrode of the P-type MOS tube MP3 and the first end of the capacitor C1 are all connected with the VDD port; the base electrode of the PNP triode Q1, the collector electrode of the PNP triode Q1, the base electrode of the PNP triode Q2, the collector electrode of the PNP triode Q2, the first end of the resistor R3 and the first end of the resistor R4 are connected with the GND; the drain electrode of the P-type MOS tube MP1, the emitting electrode of the PNP triode Q1 and the second end of the resistor R3 are connected with the negative input end of the operational amplifier A1; the gate of an N-type MOS tube MN1, the drain of a P-type MOS tube MP2, the first end of a resistor R1 and the second end of the resistor R2 in the band-gap reference source power supply starting circuit are connected with the positive input end of an operational amplifier A1; the second end of the resistor R1 is connected with an emitting electrode of the PNP triode Q2; the drain electrode of a P-type MOS tube MP4 in the band-gap reference source power supply starting circuit, the drain electrode of an N-type MOS tube MN2 in the band-gap reference source power supply starting circuit, the grid electrode of a P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP2, the grid electrode of a P-type MOS tube MP3 and the second end of a capacitor C1 are connected with the output end of the operational amplifier A1; the drain of the P-type MOS transistor MP3 and the second terminal of the resistor R4 are both connected to the VOUT port.
As shown in fig. 2, the operational amplifier A1 includes a P-type MOS transistor MP11, a P-type MOS transistor MP12, a P-type MOS transistor MP13, a P-type MOS transistor MP14, a P-type MOS transistor MP15, a P-type MOS transistor MP16, a transistor NP1, a transistor NP2, a transistor NP3, and a transistor NP4.
The operational amplifier A1 comprises a P-type MOS tube MP11, a P-type MOS tube MP12, a P-type MOS tube MP13, a P-type MOS tube MP14, a P-type MOS tube MP15, a P-type MOS tube MP16, a transistor NP1, a transistor NP2, a transistor NP3 and a transistor NP4;
the source electrode of the P-type MOS tube MP11, the source electrode of the P-type MOS tube MP12, the source electrode of the P-type MOS tube MP13 and the source electrode of the P-type MOS tube MP16 are all connected with a VDD port; the source of the transistor NP1, the source of the transistor NP2, the source of the transistor NP3, and the source of the transistor NP4 are connected to GND;
the drain electrode of the P-type MOS tube MP11, the grid electrode of the P-type MOS tube MP11 and the grid electrode of the P-type MOS tube MP13 are connected, and the drain electrode of the P-type MOS tube MP11 is also connected with a current input Ibias port; the drain of the P-type MOS transistor MP12 and the gate of the P-type MOS transistor MP12 are both connected to the gate of the P-type MOS transistor MP16, and the drain of the P-type MOS transistor MP12 is also connected to the drain of the transistor NP 1.
The drain electrode of the P-type MOS tube MP13 is arranged in two paths, wherein one path is connected with the source electrode of the P-type MOS tube MP14, and the other path is connected with the source electrode of the P-type MOS tube MP 15; the grid electrode of the P-type MOS tube MP14 is connected with the emitting electrode of the PNP triode Q1; the grid electrode of the P-type MOS tube MP15 is connected with the drain electrode of the P-type MOS tube MP 2; the sizes of the P-type MOS tube MP11, the P-type MOS tube MP12 and the P-type MOS tube MP13 are equal.
The grid of the transistor NP2 and the drain of the transistor NP2 are both connected with the grid of the transistor NP1, and the drain of the transistor NP2 is also connected with the drain of the P-type MOS transistor MP 14; the grid of the transistor NP3 and the drain of the transistor NP3 are both connected with the grid of the transistor NP4, and the drain of the transistor NP3 is also connected with the drain of the P-type MOS tube MP 15; the drain of the P-type MOS transistor MP16 and the drain of the transistor NP4 are connected to the OUT port.
In the utility model, the output gain A of the operational amplifier A1 V Comprises the following steps:
A V =g m,MP4 (r o,MP6 ||r o,MN4 )
wherein, g m,MP4 The transconductance value of the P-type MOS tube MP4 is shown; r is o,MP6 Is the on-resistance of a P-type MOS tube MP 6; r is a radical of hydrogen o,MN4 Is the on-resistance of the N-type MOS transistor MN 4.
Gain-bandwidth product G of the operational amplifier A1 BW Comprises the following steps:
wherein, g m,MP4 The transconductance value of the P-type MOS tube MP4 is shown; c OUT Is the equivalent capacitance at the output OUT of the amplifier.
The working principle is as follows:
when EN is 0, the output of INV1 is HIGH, the output of INV2 is LOW, the MP4 tube is conducted, the MP5 tube and the MP6 tube are turned off, and the grids of MP1, MP2 and MP3 are pulled to be high band gaps and are not started; when EN is changed into 1, the output of INV1 is low, the output of INV2 is high, MP5 and MP6 tubes are started, MP4 tubes are turned off, the grid electrode of MN2 is pulled high, MN2 tubes are turned on, meanwhile, MP4 tubes are turned off, therefore, the grid electrode voltages of MP1, MP2 and MP3 are pulled low and turned on, a band gap circuit starts to start, the tubes are turned on after the grid voltage of MN1 tubes is gradually increased, the grid electrode node pull-down current of MN2 tubes is larger than the pull-up current, the node is turned off by pulling down the MN2 tubes, and the MP4 tubes and the MN2 tubes are both in a turn-off state after the start is completed, and no unnecessary influence is caused on the band gap reference circuit.
The operational amplifier A1 adjusts the gate voltages of MP1 and MP1 to make the voltages of the two input terminals equal, so as to obtain:
V BE1 =V BE2 +I 1 R 1
the current flowing through resistor R2 is:
the current flowing through MP2 is I 1 And I 2 And PM1, PM2, PM3 are equal in size, so the current flowing through R4 is:
I 4 =I 1 +I 2
the bandgap output voltage VOUT is therefore:
different zero-temperature voltages can be obtained by selecting resistors with proper resistance values.
Wherein, V BE1 Is the base emitter voltage, V, of the transistor Q1 BE2 Is the base emitter voltage, deltaV, of the triode Q2 BE The difference between the base emitter voltages of the transistor Q1 and the transistor Q2 is generally used for generating delta V BE And considering layout matching accuracy, the area ratio of Q1 to Q2 is designed to be 8.
As can be seen from the formula of VOUT, the band gap reference structure passes through V BE Negative temperature coefficient characteristic and Δ V BE The positive temperature coefficient characteristic of (2) generates a zero temperature coefficient current on the resistor, and then the current is mirrored and output on the resistor R4 through the PMOS current mirrors MP1, MP2 and MP3 to generate a zero temperature coefficient voltage. The lowest power supply voltage of the circuit which can normally work is as follows:
VDD min =V dsat1,2 +V BE1
wherein, V dsat1,2 Is PMOverdrive voltage, V, of the OS transistors MP1, MP2 BE1 Is the base emitter voltage of the transistor Q1. In modern CMOS processes, the Vbe2 voltage is typically 850 mv. Vdsat1,2 is designed to be 150 mV to ensure certain matching accuracy. In summary, the lowest supply voltage at which the conventional circuit can normally operate is 1V. The voltage can meet the requirements of low voltage and low power consumption in a low-voltage CMOS process.
The band gap reference source circuit and the electronic device of the utility model utilize the band gap reference source power supply starting circuit to control the on-off of the band gap reference core circuit, and utilize the band gap reference core circuit to generate the reference voltage; the output requirements of low power supply voltage and low band-gap voltage of the band-gap reference source circuit are met by arranging an additional current loop; meanwhile, a coefficient is introduced into a band gap voltage calculation formula, so that the purpose of low-voltage output is achieved by adjusting the traditional band gap output voltage, the operation under a smaller power supply voltage is met, and a smaller band gap reference voltage is output; the circuit structure is simple, and the flow sheet production under different processes can be met; meanwhile, the method can be applied to large-scale integrated circuits and low-chip voltage and low-power consumption circuit designs, and meets the requirements of high-precision chip production processes.
The above embodiment is only one of the embodiments that can realize the technical solution of the present invention, and the scope of the present invention is not limited by the embodiment, and includes any changes, substitutions and other embodiments that can be easily conceived by those skilled in the art within the technical scope of the present invention.
Claims (8)
1. A bandgap reference source circuit, comprising:
the band-gap reference source power supply starting circuit is used for controlling the on-off of the band-gap reference core circuit;
the band-gap reference core circuit is used for generating a reference voltage;
the band gap reference source power supply starting circuit comprises an inverter INV1, an inverter INV2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2 and a resistor R5;
the input end of the inverter INV1 is connected with the EN port, and the output end of the inverter INV1 is divided into three paths; the first path is connected with the input end of the inverter INV2, the second path is connected with the grid electrode of the P-type MOS tube MP5, and the third path is connected with the grid electrode of the P-type MOS tube MP 6; the output end of the inverter INV2 is connected with the grid electrode of the P-type MOS tube MP 4;
the source electrode of the P-type MOS tube MP4 and the source electrode of the P-type MOS tube MP5 are connected with a VDD port; the drain electrode of the P-type MOS tube MP5 is connected with the source electrode of the P-type MOS tube MP 6; the drain electrode of the P-type MOS tube MP6 is arranged in two paths, wherein one path is connected with the drain electrode of the N-type MOS tube MN1, and the other path is connected with the grid electrode of the N-type MOS tube MN 2; the source electrode of the N-type MOS tube MN2 is connected with the first end of the resistor R5;
the drain electrode of the P-type MOS tube MP4 and the drain electrode of the N-type MOS tube MN2 are connected with the first input end of the band-gap reference core circuit; the grid electrode of the N-type MOS tube MN1 is connected with the second input end of the band-gap reference core circuit;
the band gap reference core circuit comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP3, a PNP triode Q1, a PNP triode Q2, a PNP triode Q3, a PNP triode Q4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a capacitor C1 and an operational amplifier A1;
the source electrode of the P-type MOS tube MP1, the source electrode of the P-type MOS tube MP2, the source electrode of the P-type MOS tube MP3 and the first end of the capacitor C1 are all connected with a VDD port;
the drain electrode of the P-type MOS tube MP1, the emitting electrode of the PNP triode Q1 and the second end of the resistor R3 are connected with the negative input end of the operational amplifier A1; the first output end of the band-gap reference source power supply starting circuit, the drain electrode of the P-type MOS tube MP2, the first end of the resistor R1 and the second end of the resistor R2 are connected with the positive input end of the operational amplifier A1; the second end of the resistor R1 is connected with an emitting electrode of the PNP triode Q2;
the second output end of the band-gap reference source power supply starting circuit, the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP2, the grid electrode of the P-type MOS tube MP3 and the second end of the capacitor C1 are connected with the output end of the operational amplifier A1;
the drain of the P-type MOS transistor MP3 and the second end of the resistor R4 are both connected to the VOUT port.
2. The bandgap reference source circuit as claimed in claim 1, wherein the source of the N-type MOS transistor MN1 and the second terminal of the resistor R5 are both connected to GND.
3. The bandgap reference source circuit as claimed in claim 1, wherein the base of the PNP transistor Q1, the collector of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2, the first terminal of the resistor R3 and the first terminal of the resistor R4 are all connected to GND.
4. The bandgap reference source circuit as claimed in claim 1, wherein the ratio of the area of the PNP transistor Q1 to the area of the PNP transistor Q2 is 8.
5. The bandgap reference source circuit as claimed in claim 1, wherein the lowest supply voltage VDD at VDD port is VDD min Is the sum of the overdrive voltage of the P-type MOS transistor MP1 and the P-type MOS transistor MP2 and the base emitter voltage of the PNP triode Q1.
6. The bandgap reference source circuit according to claim 1, wherein the operational amplifier A1 comprises a P-type MOS transistor MP11, a P-type MOS transistor MP12, a P-type MOS transistor MP13, a P-type MOS transistor MP14, a P-type MOS transistor MP15, a P-type MOS transistor MP16, a transistor NP1, a transistor NP2, a transistor NP3 and a transistor NP4;
the source electrode of the P-type MOS tube MP11, the source electrode of the P-type MOS tube MP12, the source electrode of the P-type MOS tube MP13 and the source electrode of the P-type MOS tube MP16 are all connected with a VDD port; the source of the transistor NP1, the source of the transistor NP2, the source of the transistor NP3 and the source of the transistor NP4 are connected to GND;
the drain electrode of the P-type MOS tube MP11, the grid electrode of the P-type MOS tube MP11 and the grid electrode of the P-type MOS tube MP13 are connected, and the drain electrode of the P-type MOS tube MP11 is also connected with a current input Ibias port; the drain electrode of the P-type MOS transistor MP12 and the grid electrode of the P-type MOS transistor MP12 are connected with the grid electrode of the P-type MOS transistor MP16, and the drain electrode of the P-type MOS transistor MP12 is also connected with the drain electrode of the transistor NP 1; the drain electrode of the P-type MOS tube MP13 is divided into two paths, wherein one path is connected with the source electrode of the P-type MOS tube MP14, and the other path is connected with the source electrode of the P-type MOS tube MP 15; the grid electrode of the P-type MOS tube MP14 is connected with the emitting electrode of the PNP triode Q1, and the grid electrode of the P-type MOS tube MP15 is connected with the drain electrode of the P-type MOS tube MP 2;
the grid of the transistor NP2 and the drain of the transistor NP2 are both connected with the grid of the transistor NP1, and the drain of the transistor NP2 is also connected with the drain of the P-type MOS transistor MP 14; the grid of the transistor NP3 and the drain of the transistor NP3 are both connected with the grid of the transistor NP4, and the drain of the transistor NP3 is also connected with the drain of the P-type MOS tube MP 15; the drain of the P-type MOS transistor MP16 and the drain of the transistor NP4 are connected with the OUT port.
7. The bandgap reference source circuit as claimed in claim 6, wherein the P-type MOS transistors MP11, MP12 and MP13 have the same size.
8. An electronic device comprising an electronic device and a bandgap reference source circuit, wherein the bandgap reference source circuit is a bandgap reference source circuit as claimed in any one of claims 1 to 7.
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