CN218124699U

CN218124699U - Single-wire serial transceiving circuit

Info

Publication number: CN218124699U
Application number: CN202222620881.XU
Authority: CN
Inventors: 邱林生; 张振国
Original assignee: XIAMEN OLT CO Ltd
Current assignee: XIAMEN OLT CO Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2022-12-23
Anticipated expiration: 2032-09-30

Abstract

The utility model discloses a single-wire serial transceiving circuit, which comprises a sending terminal, a receiving terminal, a public data terminal and three switching tubes; the input electrode of the first switch tube is pulled to a power supply end, the control electrode of the first switch tube is pulled to the power supply end through the first resistor and is connected with the sending end through the second resistor, and the output electrode of the first switch tube is connected with the public data end through the third resistor; the input electrode of the second switching tube is connected with the receiving end and is pulled up to the power supply end through the sixth resistor; the output pole is grounded; the control electrode of the switch is connected to the common data end through a fourth resistor and is grounded through a fifth resistor; the third switch tube is arranged between the sending end and the second control electrode, and has the functions of: stopping when the transmitting end is at a high level; and when the transmitting end is at a low level, the transmitting end is switched on, and the voltage of the second control electrode is pulled down, so that the second switch tube is in an off state, and the following effects are achieved: when the native machine sends data, the native machine software is not required to close the receiving function module, and the software code is optimized, so that the system is more stable.

Description

Single-wire serial transceiving circuit

Technical Field

The utility model relates to a communication interface technical field especially relates to a single line serial transceiver circuit.

Background

In some applications, it is desirable to simplify the connection structure and employ single wire communication. However, conventional serial communication includes a pair of bidirectional signals TXD and RXD, and the TXD and RXD need to be combined to a common data line through a hardware circuit, and it is ensured that the transmission data of the local TXD is not received by the local RXD in a software control manner, thereby generating crosstalk. However, when the TXD and the RXD on the same device side are not effectively isolated, the fault-tolerant processing requirement of software on the RXD received data can be improved, the transmission performance is influenced, and the system stability is influenced.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks of the prior art, the present invention provides a single-wire serial transceiver circuit, which employs single-wire communication; when the native machine sends data, the native machine software is not required to close the receiving function module, thereby achieving the purpose of optimizing software codes.

In order to achieve the above purpose, the utility model provides a following technical scheme:

a single-wire serial transceiver circuit comprises a transmitting terminal, a receiving terminal, a common data terminal, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a third switch tube,

the first switch tube comprises a first input electrode, a first output electrode and a first control electrode, and the first input electrode is pulled to a power supply end; the first control electrode is pulled up to a power supply end through a first resistor and is connected with the sending end through a second resistor; the first output electrode is connected with the public data terminal through a third resistor;

the second switch tube comprises a second input electrode, a second output electrode and a second control electrode, wherein the second input electrode is connected with the receiving end and is pulled up to the power supply end through a sixth resistor; the second output electrode is grounded; the second control electrode is connected to the common data end through a fourth resistor and is grounded through a fifth resistor;

the third switching tube is arranged between the sending end and the second control electrode, and is used for: stopping when the sending end is in a high level; and when the transmitting end is at a low level, the transmitting end is switched on, and the voltage of the second control electrode is pulled down, so that the second switching tube is in an off state.

Further, the first switch tube is a PNP type triode or a PMOS tube; the second switch tube is an NPN type triode or an NMOS tube.

Further, the third switching tube is a schottky diode, and an anode of the schottky diode is connected with the second control electrode; and the cathode of the Schottky diode is connected with the transmitting end.

Further, the third switch tube is an NMOS tube and includes a source, a drain, and a gate, where the source is connected to the sending terminal, the gate is connected to the common data terminal, and the second control electrode of the drain is connected to the gate.

Further, the third switch tube is an NMOS tube and includes a source electrode, a drain electrode and a gate electrode, the source electrode is connected to the second control terminal, the drain electrode is connected to the common data terminal through a fourth resistor, and the gate electrode is connected to the transmitting terminal.

Compared with the prior art, the utility model discloses a single line serial transceiver circuit has following advantage:

1. serial ports are communicated with one wire, one wire is omitted, and cost can be reduced;

2. when the native machine sends data, the receiving function module is not required to be closed by the native machine software, and the software code is optimized, so that the system is more stable;

3. the device has a level conversion function, so that products with different working voltages can normally communicate without damaging components;

4. the triode is isolated, so that signals with interference signals lower than the triode starting voltage and higher than the triode starting frequency can be filtered, and the anti-interference performance of the product is enhanced.

5. When the communication is not carried out, the public data end outputs low level, no current is consumed, and the method is particularly suitable for battery supply products.

Drawings

Fig. 1 is a first embodiment of a single-wire serial transceiver circuit of the present invention;

fig. 2 is a second embodiment of the single-wire serial transceiver circuit of the present invention;

fig. 3 is a third embodiment of the single-wire serial transceiver circuit of the present invention;

fig. 4 shows a fourth embodiment of the single-wire serial transceiver circuit of the present invention.

Detailed Description

To further illustrate the embodiments, the present invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention.

The present invention will now be further described with reference to the accompanying drawings and detailed description.

Example 1:

as shown in fig. 1, the utility model provides a single line serial transceiver circuit comprises devices such as resistance R1, R2, R3, R4, R5, R6, NPN triode Q6, PNP triode Q1 and diode D1, including three signal interface: a TX terminal, an RX terminal and a Data terminal. Wherein, TX and RX are connected with I/O port of single chip, and Data end is connected with transmission cable. The Data end is connected to the base electrode of the transistor Q6 through a resistor R4 and is connected to the collector electrode of the triode Q1 through a resistor R3; the TX end is connected to the base electrode of the triode Q1 through a resistor R2; the base electrode of the triode Q1 is pulled up to a power supply VDD through the resistor R1, and the emitting electrode of the triode Q1 is connected to the power supply VDD; the RX end is connected to the collector of the triode Q6 and is connected with the power supply VDD through the resistor R6; the collector of the transistor Q6 is grounded, and the base of the transistor Q6 is grounded through a resistor R5.

In this circuit, the diode D1 functions to keep the voltage at the RX side constant (high level) when the TX side transmits.

The working description is as follows:

in this embodiment, the diode D1 is a schottky diode, the low current conduction voltage drop is about 0.2V, and the turn-on voltage of the transistors Q1 and Q2 is 0.7V.

1. When the circuit is idle, the TX end is pulled up to output a high level, Q1 is cut off, the Data end is released, at the moment, R5 is pulled down, and the Data end outputs a low level; the triode Q6 is cut off, the RX end is pulled up, and a high level signal is input.

2. Data transmission (the TX end is a transmitting end, and the Data end is a public Data end):

A. the Data end outputs a low level signal: a TX end needs to send a high level signal, the TX end is pulled up to VDD, Q1 is cut off, a Data end is pulled down by resistors R4 and R5 to output a low level signal, Q6 is cut off, and an RX end inputs the high level signal;

B. the Data end outputs a high-level signal: when a TX end needs to send a level signal, outputs of the TX end are 0V, Q1 is conducted, a Data end is connected with VDD to output a high level signal, meanwhile, a diode D1 is conducted, the conducting voltage is 0.2V, the base voltage of Q6 is reduced, Q6 is cut off, and a RX end inputs a high level signal.

Therefore, the circuit can transmit data without influencing the receiving signal of the RX end, so that local software is not needed to close a receiving function module, software codes are optimized, and the system is more stable.

3. The circuit receives:

at this time, the TX end keeps outputting a high level signal (pulled up to VDD), Q1 is cut off, and the Data end control authority is released.

A. The Data terminal is high. Since the TX output is VDD voltage, Q6 is turned on earlier than D1, the voltage of the positive electrode of D1 is maintained at 0.7V after Q6 is turned on, and is 0.7V regardless of the voltage at the Data terminal and is turned off, so that the TX output has a communication level conversion function. Q6 is conducted, and the input of the RX terminal is low level.

B. The Data terminal is low. At this time, Q6 and D1 are turned off, and the RX input is high.

The resistances of the resistors R1 to R6 in fig. 1 may be set by a person skilled in the art according to the common general knowledge in the art, and are not limited herein.

The circuit also has the following advantages:

2. the device has a level conversion function, so that products with different working voltages can normally communicate without damaging components;

3. the triode is isolated, so that signals with interference signals lower than the triode starting voltage and higher than the triode starting frequency can be filtered, and the anti-interference performance of the product is enhanced.

4. When the communication is not carried out, the Data end outputs low level, no current is consumed, and the method is particularly suitable for battery supply products.

Preferably, based on the basic circuit in embodiment 1, the following modified example is given.

Example 2:

as shown in fig. 2, in the present embodiment, the following modifications are made with respect to embodiment 1:

a PMOS transistor Q1A is used instead of the transistor Q1 in fig. 1.

The diode D1 in fig. 1 is replaced by an NMOS transistor D1A. Specifically, the source of the NMOS transistor D1A is connected to the base of the transistor Q6A, the drain is connected to the Data terminal through a resistor R4A, and the gate is connected to the TX terminal.

When Q6A is an NMOS transistor, since the MOS transistor is a voltage control type switching transistor, the resistance of the pull-down resistor R5A connected thereto can be a little larger, and communication can be very power-saving. Specifically, it is possible to realize: no communication is performed, and the communication power consumption is less than 1uA; the method is very suitable for strong interference communication and long-time communication.

Example 3:

as shown in fig. 3, in the present embodiment, the following modifications are made with respect to embodiment 1:

(1) The transistor Q6 in fig. 1 is replaced by an NMOS transistor Q6B.

(2) An NMOS transistor D1B is used instead of the diode D1 in fig. 1. The connection relation of the NMOS tube D1B is as follows: the grid electrode of the D1B is connected with the Data end; the source electrode of the D1B is connected with the TX end; the drain of DIB is connected to the gate of Q6B.

Example 4:

as shown in fig. 4, in the present embodiment, the following modifications are made with respect to embodiment 1:

an NMOS tube D1C is adopted to replace the diode D1 in the figure 1, and a diode D2 is added. The connection relationship between the NMOS tube D1C and the diode D2C is as follows: the grid electrode of the D1C is connected with the anode electrode of the D2C and is connected to the Data end through a resistor R4C; the drain of D1C and the cathode of D2C are connected together and connected to the base of Q6C.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A single-wire serial transceiver circuit is characterized by comprising a transmitting end, a receiving end, a common data end, a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a third switch tube,

the first switch tube comprises a first input electrode, a first output electrode and a first control electrode, and the first input electrode is pulled to a power supply end; the first control electrode is pulled up to a power supply end through a first resistor and is connected with the sending end through a second resistor; the first output electrode is connected with a common data terminal through a third resistor;

the third switching tube is arranged between the sending end and the second control electrode, and is used for: stopping when the sending end is at a high level; and when the transmitting end is at a low level, the transmitting end is switched on, and the voltage of the second control electrode is pulled down, so that the second switching tube is in an off state.

2. The single-wire serial transceiver circuit of claim 1, wherein the first switch tube is a PNP triode or a PMOS tube; the second switch tube is an NPN type triode or an NMOS tube.

3. The single-wire serial transceiver circuit of claim 2, wherein said third switching transistor is a schottky diode, and an anode of said schottky diode is connected to said second gate; and the cathode of the Schottky diode is connected with the transmitting terminal.

4. The single-wire serial transceiver circuit of claim 2, wherein said third switch is an NMOS transistor, and comprises a source, a drain and a gate, said source is connected to said transmitter, said gate is connected to said common data terminal, and said drain is connected to said second gate.

5. The single-wire serial transceiver circuit of claim 2, wherein said third switch is an NMOS transistor, and comprises a source, a drain and a gate, said source is connected to said second control terminal, said drain is connected to a common data terminal through a fourth resistor, and said gate is connected to said transmitting terminal.