CN218006229U - Phase-locked loop circuit and electronic device - Google Patents

Abstract

The application provides a phase-locked loop circuit and electronic equipment, wherein the phase-locked loop circuit comprises a voltage-controlled oscillator and a frequency division and noise reduction module; the voltage-controlled oscillator is provided with a first input end and an output end, the first input end of the voltage-controlled oscillator is electrically connected with the first voltage source, and the voltage-controlled oscillator is used for converting the voltage output by the first voltage source into an oscillating voltage; the frequency division noise reduction module is provided with an input end, the input end of the frequency division noise reduction module is electrically connected with the output end of the voltage-controlled oscillator, the frequency division noise reduction module is used for dividing the frequency of the oscillating voltage and reducing the noise, a feedback phase is output, the frequency division noise reduction module divides the frequency of the oscillating voltage and reduces the noise, the feedback phase is output, the purpose of reducing the noise can be achieved, and the problem of large noise caused by fractional frequency division in a phase-locked loop circuit of the existing scheme is solved.

Description

Phase-locked loop circuit and electronic device

Technical Field

The application relates to the technical field of phase-locked loops, in particular to a phase-locked loop circuit and electronic equipment.

Background

With the improvement of integrated circuit technology and the rapid development of communication technology, phase-locked loops are widely applied in various fields. Phase-locked loops play an important role in the fields of high-speed wired communication, radio frequency wireless communication, optical fiber communication, high-performance logic circuits and the like. The phase-locked loop is divided into an integer mode and a decimal mode, and under the integer frequency division mode, the output frequency precision of the phase-locked loop is equal to the frequency multiplication of a certain reference clock frequency, but the frequency precision is far from meeting the communication protocol commonly used by a receiver. Therefore, fractional division is used in general communication. The fractional frequency-division phase-locked loop can obtain higher output frequency precision and meet the conventional receiving protocol. But the introduction of fractional division brings extra fractional division quantization noise. In order to reduce the noise caused by the introduction of fractional frequency division, the bandwidth of the phase-locked loop is usually reduced, but the noise of the voltage-controlled oscillator of the phase-locked loop itself is increased as a result of the reduced bandwidth. At present, in order to compromise fractional frequency division noise and noise of a voltage-controlled oscillator, a conventional solution is to use an inductance-capacitance voltage-controlled oscillator, and the noise of the inductance-capacitance voltage-controlled oscillator is very small, so that the noise requirement can be met only by reducing the bandwidth voltage of a phase-locked loop and reducing the fractional frequency division noise. However, the use of the lc vco brings additional problems, that is, the area of the lc vco is very large, which puts a great cost pressure on the chip.

Therefore, a need exists for a pll circuit that is capable of fractional division and has a small size and low noise.

SUMMERY OF THE UTILITY MODEL

The application mainly aims to provide a phase-locked loop circuit and electronic equipment to solve the problem that noise is large when fractional frequency division is adopted in the phase-locked loop circuit of the existing scheme.

According to an aspect of the embodiments of the present invention, there is provided a phase-locked loop circuit, including a voltage-controlled oscillator and a frequency-division noise-reduction module; the voltage-controlled oscillator is provided with a first input end and an output end, the first input end of the voltage-controlled oscillator is electrically connected with a first voltage source, and the voltage-controlled oscillator is used for converting the voltage output by the first voltage source into an oscillating voltage; the frequency division and noise reduction module is provided with an input end, the input end of the frequency division and noise reduction module is electrically connected with the output end of the voltage-controlled oscillator, and the frequency division and noise reduction module is used for outputting a feedback phase after frequency division and noise reduction are carried out on the oscillating voltage.

Optionally, the voltage controlled oscillator still has the second input, the frequency division noise reduction module still has the output, phase-locked loop circuit still includes phase frequency detector, and phase frequency detector has first input, second input and output, phase frequency detector's first input is used for the input reference phase place, phase frequency detector's second input with the output electricity of frequency division noise reduction module is connected, phase frequency detector's output respectively with the second voltage source with voltage controlled oscillator's second input electricity is connected, phase frequency detector be used for the basis reference phase place with the repayment phase place, control second voltage source is to voltage controlled oscillator charges or discharges or noninterference.

Optionally, the frequency division and noise reduction module includes a frequency divider, a phase interpolator, and a logic circuit, where the frequency divider has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal of the frequency divider is electrically connected to the output terminal of the voltage-controlled oscillator, and the frequency divider is configured to distribute the oscillating voltage; the phase interpolator is provided with a first input end, a second input end and an output end, the first input end of the phase interpolator is electrically connected with the first output end of the frequency divider, the output end of the phase interpolator is electrically connected with the second input end of the phase frequency detector, and the phase interpolator is used for assisting the frequency divider in frequency division so as to reduce noise and output the feedback phase; the logic circuit is provided with an input end, a first output end and a second output end, the input end of the logic circuit is electrically connected with the second output end of the frequency divider, the first output end of the logic circuit is electrically connected with the second input end of the frequency divider, the second output end of the logic circuit is electrically connected with the second input end of the phase interpolator, and the logic circuit is used for processing the phase output by the frequency divider and feeding the processed phase back to the frequency divider and the phase interpolator respectively.

Optionally, the phase-locked loop circuit further includes a voltage stabilizing module electrically connected to the output terminal of the phase frequency detector.

Optionally, the voltage stabilizing module includes a first voltage stabilizing module and a second voltage stabilizing module, the first voltage stabilizing module has a first end and a second end, the first end of the first voltage stabilizing module is electrically connected to the output end of the phase frequency detector, and the second end of the first voltage stabilizing module is grounded; the second voltage stabilizing module is provided with a first end and a second end, the first end of the second voltage stabilizing module is electrically connected with the output end of the phase frequency detector, and the second end of the second voltage stabilizing module is grounded.

Optionally, the first voltage stabilizing module is a first capacitor module, a first end of the first capacitor module is electrically connected to the output end of the phase frequency detector, and a second end of the first capacitor module is grounded.

Optionally, the second voltage stabilizing module includes a resistor module and a second capacitor module, a first end of the resistor module is electrically connected to the output end of the phase frequency detector, a second end of the resistor module is electrically connected to the first end of the second capacitor module, and a second end of the second capacitor module is grounded.

Optionally, the voltage stabilizing module is a third capacitor module, a first end of the third capacitor module is electrically connected to the output end of the phase frequency detector, and a second end of the third capacitor module is grounded.

Optionally, the phase-locked loop circuit further includes a low dropout regulator, the low dropout regulator has an input and an output, the input of the low dropout regulator is electrically connected to the first voltage source, the output of the low dropout regulator is electrically connected to the first input of the voltage-controlled oscillator, the low dropout regulator is used for filtering the noise of the voltage output by the first voltage source, and for the voltage-controlled oscillator provides stable voltage.

According to the utility model discloses on the other hand of the embodiment, still provide an electronic equipment, this electronic equipment includes the phase-locked loop circuit of any one of right.

The embodiment of the utility model provides an in, it will to fall the module of making an uproar through the frequency division the voltage of oscillation carries out the frequency division and falls the back of making an uproar, output repayment phase place to can reach the purpose that reduces the noise, and then solve the great problem of noise that leads to when adopting the decimal frequency division in the phase-locked loop circuit of solving current scheme.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 shows a schematic diagram of a phase locked loop circuit according to an embodiment of the present application;

fig. 2 shows a schematic diagram of another phase-locked loop circuit according to an embodiment of the application.

Wherein the figures include the following reference numerals:

10. a voltage controlled oscillator; 20. a frequency division and noise reduction module; 21. a frequency divider; 22. a phase interpolator; 23. a logic circuit; 30. a phase frequency detector; 40. a voltage stabilizing module; 41. a first voltage stabilization module; 42. a second voltage stabilization module; 50. a low dropout linear regulator.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the accompanying drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As mentioned in the background art, in order to reduce noise caused by introducing fractional frequency division in the prior art, the bandwidth of the phase-locked loop is usually reduced, but the result of reducing the bandwidth is that noise of a voltage-controlled oscillator of the phase-locked loop itself is increased, and in order to solve the problem of large noise caused when fractional frequency division is adopted in the phase-locked loop circuit of the prior art, in a typical embodiment of the present application, a phase-locked loop circuit and an electronic device are provided.

According to an embodiment of the present application, there is provided a phase-locked loop circuit, as shown in fig. 1, including a voltage-controlled oscillator 10 and a frequency-division noise reduction module 20; the voltage controlled oscillator 10 has a first input terminal and an output terminal, the first input terminal of the voltage controlled oscillator 10 is electrically connected to a first voltage source VCC1, and the voltage controlled oscillator 10 is configured to convert a voltage output by the first voltage source VCC1 into an oscillating voltage; the frequency division noise reduction module 20 has an input end, the input end of the frequency division noise reduction module 20 is electrically connected to the output end of the voltage-controlled oscillator 10, and the frequency division noise reduction module 20 is configured to output a feedback phase after frequency division and noise reduction are performed on the oscillating voltage.

The phase-locked loop circuit divides the frequency of the oscillating voltage and reduces the noise through the frequency division and noise reduction module 20, and then outputs the feedback phase, so that the purpose of reducing the noise can be achieved, and the problem of large noise caused by fractional frequency division in the phase-locked loop circuit of the prior scheme is solved.

In an embodiment of the present application, as shown in fig. 1, the voltage-controlled oscillator 10 further has a second input end, the frequency division noise reduction module 20 further has an output end, the phase-locked loop circuit further includes a phase frequency detector 30, the phase frequency detector 30 has a first input end, a second input end and an output end, the first input end of the phase frequency detector 30 is used for inputting a reference phase, the second input end of the phase frequency detector 30 is electrically connected to the output end of the frequency division noise reduction module 20, the output end of the phase frequency detector 30 is electrically connected to a second voltage source VCC2 and the second input end of the voltage-controlled oscillator 10, and the phase frequency detector 30 is used for controlling the second voltage source VCC2 to charge or discharge or not interfere with the voltage-controlled oscillator 10 according to the reference phase and the feedback phase. The phase frequency detector 30 controls the second voltage source VCC2 to operate the voltage controlled oscillator 10 by comparing the reference phase with the feedback phase, i.e. to charge or discharge or not interfere with the voltage controlled oscillator 10, and controls the second voltage source VCC2 not to interfere with the voltage controlled oscillator 10 when the reference phase is the same as the feedback phase, and if the VCO output frequency is lower than the first predetermined frequency, the first voltage source VCC1 charges the location VC, thereby increasing the VCO frequency, and if the VCO output frequency is higher than the second predetermined frequency, the first voltage source VCC1 discharges the location VC, thereby decreasing the VCO frequency, and the second predetermined frequency is higher than the first predetermined frequency.

In an embodiment of the present application, as shown in fig. 1, the frequency division and noise reduction module 20 includes a frequency divider 21, a phase interpolator 22, and a logic circuit 23, where the frequency divider 21 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal of the frequency divider 21 is electrically connected to the output terminal of the voltage controlled oscillator 10, and the frequency divider 21 is configured to perform a distribution process on the oscillating voltage; a phase interpolator 22 having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the phase interpolator 22 is electrically connected to the first output terminal of the frequency divider 21, the output terminal of the phase interpolator 22 is electrically connected to the second input terminal of the phase frequency detector 30, and the phase interpolator 22 is configured to assist the frequency divider 21 in frequency division to reduce noise and output the feedback phase; the logic circuit 23 has an input terminal, a first output terminal and a second output terminal, the input terminal of the logic circuit 23 is electrically connected to the second output terminal of the frequency divider 21, the first output terminal of the logic circuit 23 is electrically connected to the second input terminal of the frequency divider 21, the second output terminal of the logic circuit 23 is electrically connected to the second input terminal of the phase interpolator 22, and the logic circuit 23 is configured to process the phase output by the frequency divider 21 and feed back the processed phase to the frequency divider 21 and the phase interpolator 22, respectively. The phase interpolator 22 and the frequency divider 21 share the task of frequency division, so that the quantization noise of the equivalent fractional frequency division is reduced, and thus the fractional frequency division noise is reduced, because the fractional frequency division noise is effectively reduced. X is the control word given by logic circuit 23 to divider 21, Y is the control word given by logic circuit 23 to phase interpolator 22, and CLK is the clock given by the divider to convert the output clock Fout into the clock to the logic circuit.

Specifically, as shown in fig. 1, the logic circuit 23 is an Error Feedback Modulator (i.e., EFM), and the Error Feedback Modulator is configured to input a number of a 7-bit controlled integer frequency division and a number of a 21-bit controlled fractional frequency division, perform modulation processing, output a plurality of digital results, for example, the digital results are 50 and 50.2, and feed 50 back to the frequency divider 21 and 50.2 back to the phase interpolator 22.

In an embodiment of the present application, as shown in fig. 1, the phase locked loop circuit further includes a voltage stabilizing module 40, and the voltage stabilizing module 40 is electrically connected to the output terminal of the phase frequency detector 30. The voltage stabilizing module 40 is used for stabilizing voltage.

In an embodiment of the present application, the voltage stabilizing module 40 includes a first voltage stabilizing module 41 and a second voltage stabilizing module 42, the first voltage stabilizing module 41 has a first end and a second end, the first end of the first voltage stabilizing module 41 is electrically connected to the output end of the phase frequency detector 30, and the second end of the first voltage stabilizing module 41 is grounded; the second voltage stabilizing module 42 has a first terminal and a second terminal, the first terminal of the second voltage stabilizing module 42 is electrically connected to the output terminal of the phase frequency detector 30, and the second terminal of the second voltage stabilizing module 42 is grounded. The first and second voltage stabilization modules 41 and 42 are used for voltage stabilization.

In an embodiment of the present application, as shown in fig. 1, the first voltage stabilizing module 41 is a first capacitor module C1, a first end of the first capacitor module C1 is electrically connected to the output end of the phase frequency detector 30, and a second end of the first capacitor module C1 is grounded. The first capacitor module C1 is used for voltage stabilization.

In an embodiment of the present application, as shown in fig. 1, the second voltage stabilizing module 42 includes a resistor module R1 and a second capacitor module C2, a first end of the resistor module R1 is electrically connected to the output end of the phase frequency detector 30, a second end of the resistor module R1 is electrically connected to a first end of the second capacitor module C2, and a second end of the second capacitor module C2 is grounded. The resistor module R1 and the second capacitor module C2 are used for voltage stabilization.

In an embodiment of the present application, as shown in fig. 2, the voltage stabilizing module 40 is a third capacitor module C3, a first end of the third capacitor module C3 is electrically connected to the output end of the phase frequency detector 30, and a second end of the third capacitor module C3 is grounded. The third capacitor module C3 is used for voltage stabilization.

In an embodiment of the present application, as shown in fig. 1, the phase-locked loop circuit further includes a low dropout regulator 50, the low dropout regulator 50 has an input terminal and an output terminal, the input terminal of the low dropout regulator 50 is electrically connected to the first voltage source VCC1, the output terminal of the low dropout regulator 50 is electrically connected to the first input terminal of the voltage-controlled oscillator 10, and the low dropout regulator 50 is configured to filter noise of the voltage output by the first voltage source VCC1 and provide a stable voltage for the voltage-controlled oscillator 10. The voltage controlled oscillator 10 is provided with a stable voltage by filtering noise of the voltage outputted from the first voltage source VCC 1.

The working principle of the phase-locked loop circuit is as follows: as shown in fig. 1, when the pll circuit works, the phase frequency detector 30 compares the reference phase 25M with another feedback phase to control charging and discharging of the second voltage source VCC2, and then the charging and discharging charges are filtered by the voltage stabilizing module to obtain a relatively stable voltage VC, which controls the voltage controlled oscillator 10 to obtain a stable output clock Fout, which is divided by the phase interpolator 22 and the frequency divider 21 controlled by the logic circuit 23 to obtain the feedback phase Ffb, and when the Ffb and the reference phase 25M have the same frequency and the same phase, the pll circuit is locked.

According to another aspect of the embodiments of the present invention, there is provided an electronic device including the phase-locked loop circuit according to any one of the above embodiments. The frequency division and noise reduction module divides the frequency of the oscillating voltage and reduces the noise, and then outputs a feedback phase, so that the purpose of reducing the noise can be achieved, and the problem of large noise caused by decimal frequency division in the phase-locked loop circuit of the existing scheme is solved.

It should be noted that the above electrical connection may be a direct electrical connection or an indirect electrical connection, where a direct electrical connection means that two devices are directly connected, and an indirect electrical connection means that other devices, such as a capacitor and a resistor, are also connected between a and B that are connected.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) The utility model provides a phase-locked loop circuit, fall the voltage that the module of making an uproar will the aforesaid vibrate through the frequency division and fall the back of making an uproar, output repayment phase place to can reach the purpose that reduces the noise, and then solved the great problem of noise that leads to when adopting the decimal frequency division in the phase-locked loop circuit of current scheme.

2) The electronic equipment of this application, fall the voltage that the module of making an uproar will the aforesaid vibrate through the frequency division and fall the back of making an uproar, output repayment phase place to can reach the purpose that reduces the noise, and then solved the great problem of noise that leads to when adopting the decimal frequency division in the phase-locked loop circuit of current scheme.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A phase-locked loop circuit, comprising:

the voltage-controlled oscillator is provided with a first input end and an output end, the first input end of the voltage-controlled oscillator is electrically connected with a first voltage source, and the voltage-controlled oscillator is used for converting the voltage output by the first voltage source into an oscillating voltage;

the frequency division and noise reduction module is provided with an input end, the input end of the frequency division and noise reduction module is electrically connected with the output end of the voltage-controlled oscillator, and the frequency division and noise reduction module is used for outputting a feedback phase after frequency division and noise reduction are carried out on the oscillating voltage.

2. The pll circuit of claim 1, wherein the voltage controlled oscillator further has a second input, wherein the frequency division noise reduction module further has an output, and wherein the pll circuit further comprises:

the phase frequency detector has first input, second input and output, the first input of phase frequency detector is used for inputing reference phase, the second input of phase frequency detector with the output electricity of the module of making an uproar is fallen in the frequency division is connected, the output of phase frequency detector respectively with the second voltage source with the second input electricity of voltage controlled oscillator is connected, the phase frequency detector be used for according to reference phase with repay the phase, control the second voltage source is to voltage controlled oscillator charges or discharges or noninterfere.

3. The phase-locked loop circuit of claim 2, wherein the frequency-division noise reduction module comprises:

the frequency divider is provided with a first input end, a second input end, a first output end and a second output end, the first input end of the frequency divider is electrically connected with the output end of the voltage-controlled oscillator, and the frequency divider is used for distributing the oscillating voltage;

the phase interpolator is provided with a first input end, a second input end and an output end, the first input end of the phase interpolator is electrically connected with the first output end of the frequency divider, the output end of the phase interpolator is electrically connected with the second input end of the phase frequency detector, and the phase interpolator is used for assisting the frequency divider in frequency division so as to reduce noise and output the feedback phase;

the input end of the logic circuit is electrically connected with the second output end of the frequency divider, the first output end of the logic circuit is electrically connected with the second input end of the frequency divider, the second output end of the logic circuit is electrically connected with the second input end of the phase interpolator, and the logic circuit is used for processing the phase output by the frequency divider and feeding back the processed phase to the frequency divider and the phase interpolator respectively.

4. The phase-locked loop circuit of claim 2, further comprising:

and the voltage stabilizing module is electrically connected with the output end of the phase frequency detector.

5. The phase-locked loop circuit of claim 4, wherein the voltage regulation module comprises:

the first voltage stabilizing module is provided with a first end and a second end, the first end of the first voltage stabilizing module is electrically connected with the output end of the phase frequency detector, and the second end of the first voltage stabilizing module is grounded;

the second voltage stabilizing module is provided with a first end and a second end, the first end of the second voltage stabilizing module is electrically connected with the output end of the phase frequency detector, and the second end of the second voltage stabilizing module is grounded.

6. The phase-locked loop circuit of claim 5, wherein the first voltage regulation module is a first capacitor module, a first terminal of the first capacitor module is electrically connected to the output terminal of the phase frequency detector, and a second terminal of the first capacitor module is grounded.

7. The phase-locked loop circuit of claim 5, wherein the second voltage regulation module comprises a resistor module and a second capacitor module, a first terminal of the resistor module is electrically connected to the output terminal of the phase frequency detector, a second terminal of the resistor module is electrically connected to the first terminal of the second capacitor module, and a second terminal of the second capacitor module is grounded.

8. The phase-locked loop circuit of claim 4, wherein the voltage regulator module is a third capacitor module, a first terminal of the third capacitor module is electrically connected to the output terminal of the phase frequency detector, and a second terminal of the third capacitor module is grounded.

9. The phase-locked loop circuit of claim 1, further comprising:

the low dropout linear regulator is provided with an input end and an output end, the input end of the low dropout linear regulator is electrically connected with the first voltage source, the output end of the low dropout linear regulator is electrically connected with the first input end of the voltage-controlled oscillator, and the low dropout linear regulator is used for filtering the noise of the voltage output by the first voltage source and providing stable voltage for the voltage-controlled oscillator.

10. An electronic device, comprising: a phase locked loop circuit as claimed in any one of claims 1 to 9.

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