CN217768380U - CMOS image sensor pixel structure and image sensor thereof - Google Patents
CMOS image sensor pixel structure and image sensor thereof Download PDFInfo
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- CN217768380U CN217768380U CN202221681728.1U CN202221681728U CN217768380U CN 217768380 U CN217768380 U CN 217768380U CN 202221681728 U CN202221681728 U CN 202221681728U CN 217768380 U CN217768380 U CN 217768380U
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Abstract
The utility model provides a CMOS image sensor pixel structure and image sensor thereof, this pixel structure includes: a photoelectric conversion element, a charge transfer transistor, and a floating diffusion active region; a charge transfer transistor coupled to the floating diffusion active region to transfer charges accumulated by the photoelectric conversion element to the floating diffusion active region; the photoelectric conversion element and the floating diffusion active region are arranged in the semiconductor substrate; a P-type doped layer is formed on the upper surface of the N-type region of the photoelectric conversion element; and the upper surface of the P-type doped layer is higher than the upper surface of the floating diffusion active region. The pixel structure of the image sensor can reduce the transmission potential barrier of photocurrent, slow down the image smear problem, and simultaneously can ensure that the generation of dark current on the surface of a photosensitive area of a photoelectric conversion element can be effectively prevented.
Description
Technical Field
The utility model relates to an image sensor field especially relates to a CMOS image sensor pixel structure and image sensor based on CMOS image sensor pixel structure.
Background
Image sensors include both CMOS (complementary metal oxide semiconductor) and CCD (charge coupled device) types and are widely used in digital cameras, mobile phones, medical devices, automobiles, and other applications. Especially, the rapid development of the technology for manufacturing CMOS (complementary metal oxide semiconductor) image sensors has made higher demands on the output image quality of the image sensors.
A typical CMOS image sensor has an image sensor pixel array comprising thousands or even millions of pixel structures. Each pixel structure typically includes a photoelectric conversion element and a transfer transistor connected thereto. The photoelectric conversion element receives light incident from the outside, converts an optical signal into a photoelectric signal, turns on the transfer transistor, transfers the photoelectric signal to the Floating diffusion active region FD (Floating diffusion), and turns off the transfer transistor, and then the photoelectric signal is read out by a subsequent circuit.
In general, in order to prevent the generation of dark current on the surface of the photosensitive region of the photoelectric conversion element, a P-type doped Pin layer is formed on the surface of the N-type region of the photoelectric conversion element by ion implantation, and the suppression effect on the dark current is more obvious when the doping concentration of the Pin layer is larger.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention provides a CMOS image sensor pixel structure and an image sensor thereof, which are used to solve the problem that the CMOS image sensor pixel structure in the prior art cannot simultaneously satisfy the requirements of reducing or even avoiding image smear and the like while preventing dark current.
To achieve the above and other related objects, the present invention provides a CMOS image sensor pixel structure, including: a photoelectric conversion element, a charge transfer transistor, and a floating diffusion active region;
the charge transfer transistor is coupled to the floating diffusion active region to transfer charges accumulated by the photoelectric conversion element to the floating diffusion active region;
the photoelectric conversion element and the floating diffusion active region are both arranged in a semiconductor substrate;
a P-type doped layer is formed on the upper surface of the N-type region of the photoelectric conversion element; and the upper surface of the P-type doped layer is higher than the upper surface of the floating diffusion active region.
Optionally, gate side walls are formed on two sides of the gate of the charge transfer transistor; and the grid side wall on one side is formed on the surface of the floating diffusion active region, and the grid side wall on the other side is formed on the surface of the P-type doped layer.
Optionally, gate side walls are formed on two sides of the gate of the charge transfer transistor; the grid side wall on one side is formed on the surface of the floating diffusion active region, and the grid side wall on the other side is formed on the surface of the semiconductor substrate, and the side wall of one side, which is far away from the grid of the charge transfer transistor, is in contact with the P-type doped layer.
Optionally, an upper surface of the N-type region of the photoelectric conversion element is lower than an upper surface of the floating diffusion active region.
Optionally, an upper surface of the N-type region of the photoelectric conversion element is flush with an upper surface of the floating diffusion active region
Further, the thickness of the P-type doped layer is between 0.05 and 0.20 μm; and/or the doping concentration of the P-type doping layer is between 1e13/cm 2 ～4e13/cm 2 In the meantime.
In addition, the utility model also provides an image sensor, include the pixel structure in any one of above-mentioned scheme.
As described above, the utility model discloses a CMOS image sensor pixel structure and image sensor thereof, upper surface through making P type doping layer is higher than the upper surface that floats the diffusion active area, under the thickness condition of same P type doping layer, the physical position of P type doping layer has been improved in other words, make the implantation degree of depth of P type doping layer shallow to make it keep away from the photocurrent transmission barrier region, thereby reduce the transmission barrier of photocurrent, slow down the image smear problem, can also guarantee effectively to prevent photoelectric conversion element photosensitive area surface dark current's production simultaneously.
Drawings
Fig. 1 and fig. 2 are schematic cross-sectional views illustrating a pixel structure of a CMOS image sensor according to a first embodiment of the present invention.
Fig. 3 to fig. 13 are schematic cross-sectional structural diagrams showing steps in a method for manufacturing a pixel structure of a CMOS image sensor according to a second embodiment of the present invention.
Fig. 14 to fig. 26 are schematic cross-sectional structural diagrams showing steps in a method for manufacturing a pixel structure of a CMOS image sensor according to a third embodiment of the present invention.
Description of the element reference numerals
10. Semiconductor substrate
11. N-type region of photoelectric conversion element
12. Charge transfer transistor
13 P-type doped layer
14. Floating diffusion active region
15. Grid side wall
16. Epitaxial layer
17. Semiconductor substrate on N-type region of photoelectric conversion element
18. Charge transfer transistor gate
20. Photoelectric conversion element region
21. Gate region of charge transfer transistor
22. Floating diffusion active region
Upper surface of A P type doped layer
Upper surface of B floating diffusion active region
Upper surface of N-type region of C photoelectric conversion element
D semiconductor substrate with preset thickness
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 26. It should be noted that the drawings provided in the present embodiment are only schematic illustrations for explaining the basic concept of the present invention, and only the components related to the present invention are shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.
Example one
As shown in fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional structure diagram of an example of a pixel structure of a CMOS image sensor, in which a gate sidewall on one side is formed on a surface of a floating diffusion active region, and a gate sidewall on the other side is formed on a surface of a P-type doped layer; fig. 2 is a schematic cross-sectional structure diagram of another example of a pixel structure of a CMOS image sensor, in which a gate sidewall on one side is formed on the surface of a floating diffusion active region, and a gate sidewall on the other side is formed on the surface of a semiconductor substrate, and a sidewall on a side away from a gate of a charge transfer transistor is in contact with a P-type doped layer. The present embodiment provides a CMOS image sensor pixel structure, including: a photoelectric conversion element, a charge transfer transistor 12, and a floating diffusion active region 14;
the charge transfer transistor is coupled to the floating diffusion active region 14 to transfer charges accumulated by the photoelectric conversion element to the floating diffusion active region 14;
the photoelectric conversion element and the floating diffusion active region 14 are both disposed in the semiconductor substrate 10;
a P-type doped layer 13 is formed on the upper surface of the N-type region 11 of the photoelectric conversion element; and the upper surface a of the P-type doped layer 13 is higher than the upper surface B of the floating diffusion active region 14.
It should be noted here that P-type doped layer 13 is used to reduce dark current of the pixel structure. The photoelectric conversion element may be a conventional photosensitive element that converts light into electricity, such as a photodiode preferably used in the present embodiment. In addition, the main structure of the CMOS image sensor pixel of the present embodiment is the conventional structure, so the connection manner, the position relationship, etc. between these structures are not detailed herein, and other conventional structures may also be included, for example: pixel signal reading structure and logic circuit, etc. Further, in the CMOS image sensor pixel structure of the present invention, it is generally considered that the surfaces of the P-type doped layer 13, the floating diffusion active region 14, the semiconductor substrate 10, and the N-type region of the photoelectric conversion element are all planes, but the absolute plane cannot be reached based on the error of the actual process, and those skilled in the art can understand that the surface of the present invention should be a plane within the error range.
In the prior art, in order to prevent the generation of dark current on the surface of the photosensitive region of the photoelectric conversion element, a P-type doped layer (generally referred to as a P-type doped Pin layer) is formed on the surface of an N-type region of the photoelectric conversion element, but in the photoelectric conversion and transportation process of the pixel structure of the image sensor, a transmission barrier is generated on a transmission path between the photoelectric conversion element and a gate electrode of a charge transfer transistor, that is, a path through which photoelectrons are transmitted from the photoelectric conversion element to a channel below the gate electrode of the charge transfer transistor, so that the image sensor image smear problem is caused. In this embodiment, by making the upper surface of the P-type doped layer 13 higher than the upper surface of the floating diffusion active region 14, under the same thickness of the P-type doped layer, the physical position of the P-type doped layer 13 is increased, and the implantation depth of the P-type doped layer 13 is made shallow, so that the P-type doped layer is far away from the region where the photocurrent transmission barrier is located, thereby reducing the photocurrent transmission barrier, alleviating the image smear problem, and simultaneously ensuring that the generation of dark current on the surface of the photosensitive region of the photoelectric conversion element can be effectively prevented.
As a specific example, the semiconductor substrate 10 is a P-type doped semiconductor substrate, the photoelectric conversion element is a photodiode, an N-type region of the photodiode is formed by performing N-type ion implantation on the semiconductor substrate, and the photodiode is configured with the P-type doped semiconductor substrate 10. However, the present invention is not limited thereto, and the photoelectric conversion device may be other types of photosensitive devices, as long as it needs to form the P-type doped layer 13 on the surface of the N-type region, which may cause the problem of the dark current and the image smear that are not consistent with each other in the present embodiment.
In principle, the present embodiment can reduce the transmission barrier of photoelectrons as long as the upper surface of the P-type doped layer 13 is higher than the upper surface of the floating diffusion active region 14. Therefore, the upper surface C of the N-type region of the photoelectric conversion element (i.e., the lower surface of the P-type doped layer 13) may be lower than the upper surface B of the floating diffusion active region (as shown in fig. 1 and 2), or the upper surface C of the N-type region of the photoelectric conversion element may be flush with the upper surface B of the floating diffusion active region (not shown). In this embodiment, it is preferable that the upper surface C of the N-type region of the photoelectric conversion element may be lower than the upper surface B of the floating diffusion active region.
As shown in fig. 1, as an example, gate spacers 15 are formed on two sides of the charge transfer transistor gate 18; the gate sidewall 15 on one side is formed on the surface B of the floating diffusion active region, and the gate sidewall 15 on the other side is formed on the upper surface a of the P-type doped layer.
As shown in fig. 2, as another example, gate spacers 15 are formed on two sides of the charge transfer transistor gate 18; the gate sidewall 15 on one side is formed on the surface B of the floating diffusion active region, and the gate sidewall 15 on the other side is formed on the surface of the semiconductor substrate 10, and the sidewall of one side, which is far away from the charge transfer transistor gate 18, is in contact with the P-type doped layer 13, so that the electrical insulation performance between the P-type doped layer 13 and the charge transfer transistor gate 18 is effectively improved.
Here, when the upper surface C of the N-type region of the photoelectric conversion element is lower than the upper surface B of the floating diffusion active region, the semiconductor substrate 10 is located below the position where the gate sidewall 15 on the other side is formed; when the upper surface C of the N-type region of the photoelectric conversion element is flush with the upper surface B of the floating diffusion active region, the semiconductor substrate 10 below the position where the gate sidewall 15 on the other side is formed is the upper surface C of the N-type region of the photoelectric conversion element, which is equivalent to the gate sidewall 15 on the other side formed on the upper surface of the N-type region of the photoelectric conversion element.
The parameters of the P-type doped layer can be selected according to actual needs, and are not limited too much here. In this embodiment, the thickness of the P-type doped layer 13 is preferably between 0.05 μm and 0.20 μm, inclusive, and may be selected to be, for example, 0.10 μm, 0.12 μm, 0.15 μm, etc.; in another example, the doping concentration of the P-type doping layer 13 is between 1e13/cm 2 ～4e13/cm 2 Inclusive, e.g. 2e13/cm, can be chosen 2 、3e13/cm 2 And the like.
As an example, the semiconductor substrate 10 may be made of conventional semiconductor materials suitable for fabricating CMOS image sensors, such as silicon, germanium, silicon-on-insulator, germanium-on-insulator, and the like. In addition, an epitaxial layer can be deposited on the semiconductor substrate 10 through an epitaxial process, various devices can be formed in the epitaxial layer, various devices can be directly formed in the semiconductor substrate 10, P-type ion doping is firstly carried out on the epitaxial layer or the semiconductor substrate before various devices are formed, and the doping concentration is selected according to the actual situation without being limited excessively.
The present embodiment also provides an image sensor including the pixel structure as described in the above embodiments. The image sensor in this embodiment may be a CMOS image sensor, but may be any other image sensor that can use the pixel structure described in the foregoing embodiments.
Example two
As shown in fig. 3 to 13, this embodiment provides a method for manufacturing a pixel structure of a CMOS image sensor, and the pixel structure of the CMOS image sensor according to the first embodiment can be manufactured by the method. For the pixel structure manufactured by the manufacturing method of the present embodiment, please refer to embodiment one, which will not be described in detail below.
As shown in fig. 3-5, step S1 is performed to provide a semiconductor substrate 10, and a photoelectric conversion element and a charge transfer transistor 12 are formed on the semiconductor substrate 10; wherein the photoelectric conversion element is formed on the basis of an ion implantation process performed on the semiconductor substrate 10.
As a specific example, the step of forming the photoelectric conversion element includes: forming a P-type semiconductor substrate; then, N-type ion implantation is performed on a predetermined region of the P-type semiconductor substrate by an ion implantation process to form an N-type region 11 of the photoelectric conversion element (as shown in fig. 4), so that the P-type semiconductor substrate and the N-type region 11 of the photoelectric conversion element constitute the photoelectric conversion element. It should be noted that the doping concentrations of the P-type semiconductor substrate and the N-type region 11 of the photoelectric conversion element are specifically selected according to actual needs, and parameters such as the implantation depth and the implantation position of the N-type region 11 of the photoelectric conversion element are not limited too, for example: the N-type region 11 of the photoelectric conversion element may be formed below the surface of the semiconductor substrate 10 (as shown in fig. 4) or may be flush with the surface of the semiconductor substrate 10.
Further, as shown in fig. 5, a charge transfer transistor 12 is formed on the surface of the semiconductor substrate 10 where the N-type region 11 of the photoelectric conversion element is formed, and a gate of the charge transfer transistor 12 is formed as will be understood by those skilled in the art. For example, it may be a gate structure commonly used in the field of image sensors, including a gate dielectric layer and a polysilicon gate.
As shown in fig. 6-7, step S2 is performed to form a P-type doped layer 13 on the upper surface of the N-type region 11 of the photoelectric conversion device by using an epitaxy process and an ion implantation process.
As a specific example, the step of forming the P-type doped layer 13 includes: as shown in fig. 6, an epitaxial layer 16 is formed on the surface of the semiconductor substrate 10 on the N-type region 11 of the photoelectric conversion element by an epitaxial process, wherein the temperature of the epitaxial process is selected to be between 900 ℃ and 1200 ℃, inclusive, for example, 1000 ℃ and 1100 ℃; generally, in order to facilitate control of the concentration distribution of the subsequently formed P-type doped layer 13, the doping type and the doping concentration of the epitaxially formed epitaxial layer 16 are as close as possible to those of the semiconductor substrate 10, and preferably are the same; then, P-type ion implantation is performed on the structural layer on the N-type region 11 of the photoelectric conversion element, so as to form the P-type doped layer 13. It should be noted that, in each case, when the upper surface of the N-type region 11 of the photoelectric conversion element is flush with the upper surface of the semiconductor substrate 10, the epitaxial layer 16 is only required to be P-type ion-implanted to form the P-type doped layer 13, and when the upper surface of the N-type region 11 of the photoelectric conversion element is lower than the upper surface of the semiconductor substrate 10, the semiconductor substrate 10 and the epitaxial layer 16 on the N-type region 11 of the photoelectric conversion element are required to be ion-implanted to form the P-type doped layer 13.
As an example, after the P-type doped layer 13 is formed, a step of forming gate spacers 15 on both sides of the gate 18 of the charge transfer transistor is further included. The gate spacers 15 formed here have two forms: first, as shown in fig. 8, the gate sidewall 15 on one side is formed on the surface of the subsequently formed floating diffusion active region 14, and the gate sidewall 15 on the other side is formed on the surface of the P-type doping layer 13; secondly, as shown in fig. 12, the gate sidewall 15 on one side is formed on the surface of the floating diffusion active region 14, and the gate sidewall 15 on the other side is formed on the surface of the semiconductor substrate 10, and the sidewall on the side far away from the charge transfer transistor gate 18 is in contact with the P-type doped layer 13.
As a specific example, as shown in fig. 6 to 8, steps for forming the gate sidewall spacers 15 in the first case are as follows: as shown in fig. 6, an epitaxial layer 16 is formed on the surface of the semiconductor substrate 10 on the N-type region 11 of the photoelectric conversion element by an epitaxial process; as shown in fig. 7, then, performing ion implantation on the epitaxial layer 16, or performing ion implantation on the semiconductor substrate 10 and the epitaxial layer 16 on the N-type region 11 of the photoelectric conversion element, to form the P-type doped layer 13; finally, the gate spacers 15 are formed on two sides of the charge transfer transistor gate 18, wherein the gate spacer 15 on one side is formed on the surface of the floating diffusion active region 14 to be formed later, and the gate spacer 15 on the other side is formed on the surface of the P-type doping layer 13.
As another specific example, as shown in fig. 10 to 12, in order to form the gate sidewall spacers 15 in the second case, the steps of: firstly, forming an epitaxial layer 16 on the surface of the semiconductor substrate on an N-type region of the photoelectric conversion element by adopting an epitaxial process; then, as shown in fig. 10, etching a part of the P-type doped layer 16 close to one side of the charge transfer transistor gate 18 until the surface of the semiconductor substrate 10 is exposed; next, as shown in fig. 11, gate spacers 15 are formed on two sides of the charge transfer transistor gate 18; finally, as shown in fig. 12, ion implantation is performed on the remaining epitaxial layer 16, or ion implantation is performed on the semiconductor substrate 10 on the N-type region 11 of the photoelectric conversion element and the remaining epitaxial layer 16, so as to form the P-type doped layer 13; the gate sidewall 15 on one side is formed on the surface of the floating diffusion active region 14, and the gate sidewall 15 on the other side is formed on the surface of the semiconductor substrate 10, and the sidewall of one side far away from the charge transfer transistor gate 18 is in contact with the P-type doped layer 13.
As shown in fig. 9 and 13, step S3 is finally performed to form a floating diffusion active region 14 on the semiconductor substrate 10; wherein the charge transfer transistor 12 is coupled to the floating diffusion active region 14 to transfer charges accumulated in the photoelectric conversion element to the floating diffusion active region 14, and the floating diffusion active region 14 is formed based on an ion implantation process performed on the semiconductor substrate 10. The upper surface a of the P-type doped layer 13 thus formed is certainly higher than the upper surface B of the floating diffusion active region 14.
EXAMPLE III
As shown in fig. 14 to 26, this embodiment also provides a method for manufacturing a pixel structure of a CMOS image sensor, and the pixel structure of the CMOS image sensor according to the first embodiment can be manufactured by this method. For the pixel structure manufactured by the manufacturing method of the present embodiment, please refer to embodiment one, which will not be described in detail below.
As shown in fig. 14, step S1 is performed to provide a semiconductor substrate 10, and define a photoelectric conversion element region 20, a gate region 21 of a charge transfer transistor, and a floating diffusion active region 22 in the semiconductor substrate 10.
As shown in fig. 15, step S2 is then performed to etch a semiconductor substrate D with a predetermined thickness in the floating diffusion active region 22 and the gate region 21 of the charge transfer transistor. The size of the semiconductor substrate D with the preset thickness is set according to actual needs, and is not limited excessively herein.
As shown in fig. 16 to 25, step S3 is performed to form the charge transfer transistor gate 18 in a region corresponding to the charge transfer transistor gate 18, form the photoelectric conversion element in a region corresponding to the photoelectric conversion element by using an ion implantation process, and form a P-type doped layer 13 on the N-type region 11 of the photoelectric conversion element.
As a specific example, the step of forming the photoelectric conversion element includes: forming a P-type semiconductor substrate; then, N-type ion implantation is performed on the photoelectric conversion element region 20 of the P-type semiconductor substrate by an ion implantation process to form an N-type region 11 of the photoelectric conversion element (as shown in fig. 16), so that the P-type semiconductor substrate and the N-type region 11 of the photoelectric conversion element constitute the photoelectric conversion element. It should be noted that the doping concentrations of the P-type semiconductor substrate and the N-type region 11 of the photoelectric conversion element are specifically selected according to actual needs, and parameters such as the implantation depth and the implantation position of the N-type region 11 of the photoelectric conversion element are not limited too much, for example: the N-type region 11 of the photoelectric conversion element may be formed below the surface of the semiconductor substrate 10 (as shown in fig. 16) or may be flush with the surface of the semiconductor substrate 10.
As shown in fig. 20 and 26, step S4 is finally performed to form the floating diffusion active region 14 in the region corresponding to the floating diffusion active region. The upper surface a of the P-type doped layer 13 thus formed is certainly higher than the upper surface B of the floating diffusion active region 14.
As an example, the CMOS image sensor pixel structure formed by the manufacturing method of this embodiment further includes gate spacers 15 formed on two sides of the charge transfer transistor gate 18. The gate spacers 15 formed here have two forms: first, as shown in fig. 19 and 20, the gate sidewall 15 on one side is formed on the surface of the floating diffusion active region 14, and the gate sidewall 15 on the other side is formed on the surface of the P-type doped layer 13; secondly, as shown in fig. 25 and 26, the gate sidewall 15 on one side is formed on the surface of the floating diffusion active region 14, and the gate sidewall 15 on the other side is formed on the surface of the semiconductor substrate 10, and the sidewall of one side far away from the charge transfer transistor gate 18 is in contact with the P-type doped layer 13.
As a specific example, as shown in fig. 16 to 19, in order to form the gate sidewall spacers 15 of the first case: as shown in fig. 16, firstly, an ion implantation process is used to form a photoelectric conversion element in the photoelectric conversion element region 20, wherein an N-type region 11 of the photoelectric conversion element is formed by performing N-type ion implantation on the semiconductor substrate 10, and the N-type region 11 of the photoelectric conversion element may be formed below the surface of the semiconductor substrate 10 (as shown in fig. 16) or may be flush with the surface of the semiconductor substrate 10; as shown in fig. 17, a charge transfer transistor gate 18 is then formed in the charge transfer transistor gate region 21; as shown in fig. 18, then, forming gate spacers 15 on two sides of the charge transfer transistor gate 18, so that the gate spacers 15 on one side are formed on the semiconductor substrate 10 in the floating diffusion active region 22, the part of the semiconductor substrate 10 is formed into the floating diffusion active region 14 by an ion implantation process, the gate spacers 15 on the other side are formed on the semiconductor substrate 10 in the photoelectric conversion element region 20, and the part of the semiconductor substrate 10 is formed into the P-type doped layer 13 by an ion implantation process; as shown in fig. 19, finally, ion implantation is performed on the semiconductor substrate on the N-type region 11 of the photoelectric conversion element to form a P-type doped layer 13.
As another specific example, as shown in fig. 21 to 25, in order to form the gate sidewall spacers 15 in the second case: as shown in fig. 21, first, when the semiconductor substrate D with the preset thickness is etched in the floating diffusion active region 22 and the gate region 21 of the charge transfer transistor, the semiconductor substrate D with the preset thickness is also etched in a part of the photoelectric conversion element region 20, and the part of the photoelectric conversion element region 20 is etched to be subsequently used as a region for forming a gate sidewall on one side; as shown in fig. 22, then, forming a photoelectric conversion element in the photoelectric conversion element region 20 by using an ion implantation process, wherein an N-type region 11 of the photoelectric conversion element is formed by performing N-type ion implantation on the semiconductor substrate 10, and the N-type region 11 of the photoelectric conversion element may be formed below the surface of the semiconductor substrate 10 (as shown in fig. 22) or may be flush with the surface of the semiconductor substrate 10; as shown in fig. 23, a charge transfer transistor gate 18 is then formed in the charge transfer transistor gate region 21; as shown in fig. 24, next, gate spacers 15 are formed on two sides of the charge transfer transistor gate 18, so that the gate spacer 15 on one side is formed on the semiconductor substrate 10 of the floating diffusion active region 22, the part of the semiconductor substrate 10 is formed into the floating diffusion active region 14 by an ion implantation process, and the gate spacer 15 on the other side is formed on the part of the semiconductor substrate 10 of the photoelectric conversion element region 20; as shown in fig. 25, finally, ion implantation is performed on the semiconductor substrate 10 on the N-type region 11 of the photoelectric conversion element to form a P-type doped layer 13, and the sidewall of the gate sidewall 15 on the side away from the charge transfer transistor gate 18 is in contact with the P-type doped layer 13.
To sum up, the utility model provides a CMOS image sensor pixel structure and preparation method, image sensor, upper surface through making P type doping layer is higher than the upper surface that floats the diffusion active area, under the thickness condition of same P type doping layer, the physical position of P type doping layer has been improved in other words, the implantation depth that makes P type doping layer becomes shallow, so that it keeps away from photocurrent transmission barrier area, thereby reduce the transmission barrier of photocurrent, slow down the image smear problem, can also guarantee effectively to prevent the production of photoelectric conversion element sensitive area surface dark current simultaneously. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A CMOS image sensor pixel structure, comprising: a photoelectric conversion element, a charge transfer transistor, and a floating diffusion active region;
the charge transfer transistor is coupled to the floating diffusion active region to transfer charges accumulated by the photoelectric conversion element to the floating diffusion active region;
the photoelectric conversion element and the floating diffusion active region are both arranged in a semiconductor substrate;
a P-type doped layer is formed on the upper surface of the N-type region of the photoelectric conversion element; and the upper surface of the P-type doped layer is higher than the upper surface of the floating diffusion active region.
2. The CMOS image sensor pixel structure of claim 1, wherein: grid side walls are formed on two sides of the grid of the charge transfer transistor; and the grid side wall on one side is formed on the surface of the floating diffusion active region, and the grid side wall on the other side is formed on the surface of the P-type doped layer.
3. The CMOS image sensor pixel structure of claim 1, wherein: grid side walls are formed on two sides of the grid of the charge transfer transistor; the grid side wall on one side is formed on the surface of the floating diffusion active region, and the grid side wall on the other side is formed on the surface of the semiconductor substrate, and the side wall of one side, which is far away from the grid of the charge transfer transistor, is in contact with the P-type doped layer.
4. The CMOS image sensor pixel structure of claim 1, wherein: the lower surface of the P-type doped layer is lower than the upper surface of the floating diffusion active region.
5. The CMOS image sensor pixel structure of claim 1, wherein: the lower surface of the P-type doped layer is flush with the upper surface of the floating diffusion active region.
6. The CMOS image sensor pixel structure of any one of claims 1-5, wherein: the thickness of the P-type doped layer is between 0.05 and 0.20 mu m.
7. The CMOS image sensor pixel structure of claim 6, wherein: the doping concentration of the P-type doping layer is between 1e13/cm 2 ～4e13/cm 2 In the meantime.
8. The CMOS image sensor pixel structure of any one of claims 1-5, wherein: the doping concentration of the P-type doping layer is between 1e13/cm 2 ～4e13/cm 2 In the meantime.
9. An image sensor comprising a CMOS image sensor pixel structure according to any one of claims 1 to 8.
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