CN217444400U

CN217444400U - Integrated circuit

Info

Publication number: CN217444400U
Application number: CN202221222853.6U
Authority: CN
Inventors: 雷天飞; 李卓
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-09-16
Anticipated expiration: 2032-05-19

Abstract

The utility model provides an integrated circuit, wherein, this integrated circuit includes a plurality of memory cell, and memory cell includes: an active region and a gate layer disposed on the substrate, the active region including a source terminal at one side of the gate layer and a drain terminal at the other side of the gate layer: the source electrode and the gate electrode are respectively communicated to the source end and the gate layer by multiplexing the first lead through hole, and the drain electrode is communicated to the drain end by the second lead through hole. Therefore, the ohmic contact of the common electrode can be formed by multiplexing the same lead through hole by the adjacent electrodes in the same storage unit, so that the distance between the two adjacent electrodes is reduced, the area of a single storage unit is further reduced, and/or the ohmic contact of the common electrode is formed by multiplexing the same lead through hole by the adjacent electrodes between the adjacent storage units, the areas of the two adjacent storage units are further reduced, the area of a semiconductor chip is further reduced, and the storage density is improved.

Description

Integrated circuit

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly to an integrated circuit.

Background

Today, the continuing demand for better performance (e.g., increased processing speed, memory space, etc.), shrinking form factors, extended battery life, and lower cost have driven the semiconductor manufacturing industry. In response to the demand, the industry has continued to reduce the size of semiconductor device components so that modern integrated chips may include millions or billions of semiconductor devices arranged on a single semiconductor die.

In the fabrication of high-density semiconductor devices on an integrated circuit chip, it is necessary to consider how to reduce the size of each Memory Cell (Memory Cell) and the power consumption, thereby reducing the lateral area of the Memory Cell. As shown in fig. 1 to 2b (in the drawings, structural layers such as doped regions and/or well regions of active regions are omitted, and only structural layers representing different electrodes are shown), in the semiconductor element shown in fig. 1 in the prior art, metal electrodes connected through metal wires between the gate and the drain are shorted within the same element (for example, a Grounded Gate Metal Oxide Semiconductor (GGMOS)). Fig. 2a is a circuit structure diagram of a Bit cell (SRAM Bit cell) of an SRAM, and fig. 2b is a partial connection diagram of a part of transistor devices in the cell of fig. 2 a. As can be seen from fig. 2a, the drain of the transistor M1 and the drain of the transistor M3 are shorted together, and the drain connection is shorted together with the gates of the transistor M4 and the transistor M2, the drain of the transistor M2 and the drain of the transistor M4 are shorted together, and the drain connection is shorted together with the gates of the transistor M3 and the transistor M1, and the connections therebetween are typically in the manner of fig. 2b, and referring to fig. 2b, the connections between the gates and the drains between the different elements are also shorted by metal electrodes that are in communication through metal leads. In the method, the size of the polysilicon gate layer packaging hole and the size of the active region packaging hole need to be considered, so that the distance between the polysilicon gate layer through hole and the active region through hole is overlarge, and the element size and the chip area are increased.

Therefore, in a conventional code type flash memory element layout, the drain electrode, the source electrode and the grid electrode of the conventional code type flash memory element are led out through contact holes, and the function of fast random reading can be well realized. But with the attendant chip size being too large and costly. The main reason is that the size of the active region is increased due to the introduction of the contact holes of the source/drain region and the polysilicon gate layer, and the area of the whole chip is affected.

Therefore, a method is needed to solve the above problems.

SUMMERY OF THE UTILITY MODEL

To the deficiency of the prior art, the utility model provides an integrated circuit to promote semiconductor chip's miniaturization.

In one aspect the present disclosure provides an integrated circuit comprising a plurality of memory cells, wherein a memory cell comprises:

an active region and a gate layer disposed on the substrate, the active region including a source terminal at one side of the gate layer and a drain terminal at the other side of the gate layer:

the source electrode and the gate electrode are respectively communicated to the source end and the gate layer by multiplexing the first lead through hole, and the drain electrode is communicated to the drain end by the second lead through hole.

Further, the gate layer includes:

a gate oxide layer and a polysilicon layer, which are sequentially stacked on the substrate,

the first lead through hole exposes a part of the source end and a part of the surface of the polysilicon layer.

Further, the integrated circuit further includes:

the first lead through hole penetrates through the dielectric layer to communicate the source electrode and the source end; and

and the grid side walls are positioned on two sides of the grid layer on the surface of the substrate, and the grid side walls close to the second lead through holes are used for transversely isolating the grid layer from the side walls of the second lead through holes.

Furthermore, the adjacent electrodes between at least one group of adjacent memory cells in the integrated circuit are multiplexed with the same lead through hole to form ohmic contact of the common electrode,

wherein, the gate layers of at least one group of adjacent memory units have an isolation region therebetween.

Furthermore, the isolation region is disposed between the gate layer of the memory cell and the substrate, and covers the gate layer and the bottom of the gate sidewall, so as to isolate the gate layer from the substrate.

Furthermore, the isolation region is arranged between the gate layer of the memory unit and the substrate, and wraps a part of the bottom of the gate layer and the bottom of the gate side wall on one side, and a part of the gate oxide layer is communicated with the isolation region to form isolation between the gate layer and the substrate.

The utility model has the advantages that: the present disclosure provides an integrated circuit and an electrode connection method of an active region and a gate region thereof, wherein the integrated circuit comprises a plurality of memory cells, and the memory cells comprise: an active region and a gate layer disposed on the substrate, the active region including a source terminal at one side of the gate layer and a drain terminal at the other side of the gate layer: the source electrode and the gate electrode are respectively communicated to the source end and the gate layer by multiplexing the first lead through hole, and the drain electrode is communicated to the drain end by the second lead through hole. The ohmic contact of the common electrode is formed by multiplexing the same lead through hole by the adjacent electrodes in the same storage unit, so that the distance between the two adjacent electrodes is reduced, the area of a single storage unit is further reduced, and/or the ohmic contact of the common electrode is formed by multiplexing the same lead through hole by the adjacent electrodes between the adjacent storage units, the areas of the two adjacent storage units are further reduced, the area of a semiconductor chip is further reduced, and the storage density is improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of the connection of an active area electrode and a gate area electrode in the same transistor element in a prior art semiconductor element;

FIG. 2a is a diagram of an integrated circuit structure in a bitcell of an SRAM;

FIG. 2b is a schematic diagram of the connection of the active area electrode and the gate area electrode in adjacent transistor elements in the bitcell of FIG. 2 a;

fig. 3 is a schematic diagram illustrating connection of an active region electrode and a gate region electrode in the same transistor device in a semiconductor device provided by an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating connection of an active region electrode and a gate region electrode in adjacent transistor elements in one embodiment of a semiconductor element provided by an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating connection of an active region electrode and a gate region electrode in adjacent transistor elements in another implementation manner of the semiconductor element provided by the embodiment of the present disclosure.

Reference numerals:

1: substrate 2: gate oxide layer 3: grid side wall

4: polysilicon layer 5: dielectric layer 6: lead through hole

61: first lead through hole 62: second lead through hole

7: metal electrode (source electrode S, gate electrode G, drain electrode D) 8: insulating layer

Detailed Description

To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

Flash memory has become a hot point of research in non-volatile memories due to its advantages of convenience, high storage density, good reliability and the like. Since the first flash memory product appeared in the eighties of the twentieth century, with the development of technology and the demand of various electronic products for storage, flash memory is widely used in mobile and communication devices such as mobile phones, notebooks, palm computers, U disks and the like, the flash memory is a non-volatile memory, the operation principle of which is to control the on-off of a gate channel by changing the threshold voltage of a transistor or a memory cell so as to achieve the purpose of storing data, so that the data stored in the memory cannot disappear due to power interruption, and the flash memory is a special structure of an electrically erasable and programmable read-only memory. Flash memory now occupies a large portion of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory.

Static Random Access Memory (SRAM) is a widely used memory device, and in order to increase the density of devices arranged on a chip and reduce the manufacturing cost, the feature size of the memory device needs to be reduced. However, further reduction of the feature size of the memory cells of the memory device becomes very difficult, as is the limitation of further reduction of the feature size of the contact regions, the polysilicon gates, and the source regions.

Therefore, in the prior art, local interconnection between the gate structures or between the gate structures and the source/drain regions in the memory cells is realized by removing the side walls on the side walls of the gate structures and depositing an interconnection polysilicon layer, so that the number of contact holes to be formed can be reduced, and the area of the memory cells can be reduced. However, as the device size is reduced, the space between the interconnected polysilicon layers becomes smaller, and it is difficult for the conventional photolithography process to complete the fabrication of the interconnected polysilicon layers.

Based on this, the utility model discloses under the prerequisite that does not change the technology processing procedure, reduce the interval of through-hole on the polycrystalline silicon gate and the through-hole on the active area to zero or overlap partly to reduce the component area and reduce the chip area.

The present disclosure is described in detail below with reference to the accompanying drawings.

The first embodiment is as follows:

fig. 3 is a schematic diagram illustrating connection between an active region electrode and a gate region electrode in the same transistor device in a semiconductor device according to an embodiment of the present disclosure.

In one aspect, the present disclosure provides an integrated circuit, which may be any one of a monolithic integrated circuit based on a silicon planar process, a thin film integrated circuit based on a thin film technology, and a thick film integrated circuit based on a screen printing technology, such as: CMOS chip, SRAM _ bitcell, etc. In the concrete selection, various monolithic integrated circuits and thick film and thin film integrated processes can be combined together to form a complex complete circuit.

Referring to fig. 3 (omitting the structural layers such as the doped regions and/or well regions of the active region, only the structural layers representing different electrodes are shown, the same applies below), the integrated circuit 100 includes a plurality of memory cells, wherein the memory cells include:

an active region (not shown) and a gate layer (2 and 4 are collectively not shown) disposed on the substrate 1, the active region including a source terminal at one side of the gate layer and a drain terminal at the other side of the gate layer;

the source electrode S and the gate electrode G are respectively communicated to the source end and the gate layer by the first lead through hole 61, and the drain electrode D is communicated to the drain end by the second lead through hole 62. The multiplexed first lead via 61 reduces the current density within the metal interconnect lead that fills the via to form the short by increasing the cross-sectional area in a direction parallel to the surface of the substrate 1. In various embodiments, the conductive material of the metal interconnect leads may include materials such as: copper, aluminum, titanium, tungsten, and the like.

In some alternative embodiments, the substrate 1 may be any type of semiconductor body, such as a semiconductor wafer and/or one or more dies located on the wafer, as well as any other type of metal layer, device, semiconductor, and/or epitaxial layer, etc., associated therewith. The substrate 1 may comprise an intrinsically doped substrate having a first doping type (e.g. n-type doping or p-type doping). The substrate 1 may be formed of undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, single crystal silicon is selected as a constituent material of the substrate 1.

In some alternative embodiments, the source/drain regions may be formed by selectively implanting dopant species into the substrate 1. In various embodiments, the dopant species may include a p-type dopant (e.g., boron, gallium, etc.) or an n-type dopant (e.g., phosphorus, arsenic, etc.). In some embodiments, dopant species may be driven into the substrate 1 by performing a subsequent high temperature anneal. In some alternative embodiments, the aforementioned source/drain regions may be formed at locations within or above the substrate 1 by etching and epitaxial growth processes.

In some alternative embodiments, the conductive material may be formed by first depositing a seed layer within first/

second wire vias

61, 62, followed by a subsequent plating process (e.g., an electroplating process, an electroless plating process, etc.) to fill the wire vias (with conductive filler). In some embodiments, a Chemical Mechanical Polishing (CMP) process may be subsequently performed.

In some alternative embodiments, the gate layer comprises: a gate oxide layer 2 and a polysilicon layer 4, the gate oxide layer 2 and the polysilicon layer 4 being sequentially stacked on the substrate 1,

the first lead through hole 61 exposes a portion of the source terminal and a portion of the surface of the polysilicon layer 2.

In some optional embodiments, the foregoing integrated circuit 100 further includes:

a dielectric layer 5 located between the substrate 1 and the metal electrode 7, wherein the first lead through hole 61 penetrates through the dielectric layer 5 to communicate the source electrode S and the source end; and

and the gate side walls 3 are positioned on two sides of the gate layer on the surface of the substrate 1, and the gate side walls 3 close to the second lead through holes 62 are used for transversely isolating the gate layer from the side walls of the second lead through holes 62.

In some optional embodiments, the dielectric layer 5 may be a single-layer structure or a multi-layer structure, and the material thereof may be, for example: low-k dielectric materials, oxide materials, undoped silicon dioxide (SiO2), fluorosilicate glasses, and the like.

Therefore, in the integrated circuit 100 provided in the first embodiment of the present disclosure, the adjacent electrodes in the same memory cell may reuse the same lead through hole to form ohmic contact of the common electrode, so that the distance between the two adjacent electrodes is reduced, the area of a single memory cell is further reduced, the area of a semiconductor chip is further reduced, and the storage density is improved.

To implement the integrated circuit 100, the present embodiment optionally adopts the following electrode connection method for the active region and the gate region in the integrated circuit:

depositing an active region and a gate layer on the substrate 1, wherein the active region forms a source end on one side of the gate layer and a drain end on the other side of the gate layer;

depositing to form a dielectric layer 5 covering the gate layer and the active region;

etching the dielectric layer 5 to form a first lead through hole 61 and a second lead through hole 62, wherein the first lead through hole 61 is formed to expose a part of the source terminal and a part of the surface of the gate layer, and the second lead through hole 62 is formed to expose a part of the drain terminal;

the deposited metal layer fills the first lead through hole 61 and extends transversely on the surface of the dielectric layer 5 to form a source electrode S, which is reused as a gate electrode G, and the deposited metal layer fills the second lead through hole 62 and extends transversely on the surface of the dielectric layer 5 to form a drain electrode D, and an isolation is formed between the source electrode S and the drain electrode D, as shown in fig. 3.

In some optional embodiments, the step of depositing and forming the active region and the gate layer on the substrate 1 includes:

respectively carrying out ion implantation on an active region on the surface of the substrate 1 to form a source end doped region and a drain end doped region; and

and sequentially depositing a gate oxide layer 2 and a polysilicon layer 4 between the source end doped region and the drain end doped region on the surface of the substrate 1.

In some optional embodiments, after the step of depositing and forming the active region and the gate layer on the substrate 1, the electrode connection method further includes:

depositing a side wall material layer to cover the side wall of the gate layer; and

the spacer material layer is etched to form the gate spacer 3.

It should be noted that the remaining structure of the memory cell, the process details thereof, and the overall process flow are well known in the art and are not described herein.

Example two:

fig. 4 shows a schematic connection diagram of an active area electrode and a gate area electrode in an adjacent transistor element in a semiconductor element in one implementation, and fig. 5 shows a schematic connection diagram of an active area electrode and a gate area electrode in an adjacent transistor element in another implementation, which is provided by the embodiment of the present disclosure.

Referring to fig. 4, a second embodiment of the disclosure provides an integrated circuit 200 having a single memory cell with the same structural composition as the first embodiment, except that:

on the basis of the first embodiment, the same lead via 61 is multiplexed to form an ohmic contact of the common electrode between adjacent electrodes (the drain electrode D of the first memory cell and the gate electrode G of the second memory cell, the same applies hereinafter) of at least one group of adjacent memory cells in the integrated circuit 200, wherein the gate layers of the at least one group of adjacent memory cells have the isolation region 8 therebetween.

In some alternative embodiments, the aforementioned isolation region 8 is disposed between the gate layer of the memory cell and the substrate 1, and covers the gate layer and the bottom of the aforementioned gate sidewall 3, so as to isolate the gate layer from the substrate 1, as shown in fig. 4.

In other alternative embodiments, the aforementioned isolation region 8 is disposed between the gate layer of the memory cell and the substrate 1, and wraps a portion of the bottom of the gate layer and the bottom of the gate sidewall 3 on the side away from the lead through hole 61, and a portion of the gate oxide layer 2 communicates with the aforementioned isolation region 8 to form isolation between the gate layer and the substrate 1, as shown in fig. 5.

Therefore, the integrated circuit 200 provided in the second embodiment of the present disclosure can not only form the ohmic contact of the common electrode by multiplexing the same lead through hole through the adjacent electrodes in the same memory cell, thereby reducing the distance between the two adjacent electrodes to reduce the area of a single memory cell, but also form the ohmic contact of the common electrode by multiplexing the same lead through hole through the adjacent electrodes between the adjacent memory cells to further reduce the area of two adjacent memory cells, thereby reducing the area of the semiconductor chip and improving the storage density.

To implement the integrated circuit 200, the present embodiment optionally adopts the following electrode connection method for the active region and the gate region in the integrated circuit:

the deposited metal layer fills the first lead through hole 61 and extends laterally on the surface of the dielectric layer 5 to form a source electrode S, which is reused as a gate electrode G, and the deposited metal layer fills the second lead through hole 62 and extends laterally on the surface of the dielectric layer 5 to form a drain electrode D, and an isolation is formed between the source electrode S and the drain electrode D, as will be understood with reference to fig. 3.

the spacer material layer is etched to form the gate spacer 3.

In some alternative embodiments, the adjacent electrodes between at least one group of adjacent memory cells in the integrated circuit 200 are multiplexed with the same wire via to form an ohmic contact of the common electrode, wherein the gate layer of the multiplexed electrode in the at least one group of adjacent memory cells is formed with the isolation region 8 therebetween.

In some optional embodiments, the step of forming an isolation region between the gate layers of the multiplexing electrodes in at least one group of adjacent memory cells includes:

isolation regions 8 are formed on the substrate 1 in the regions before the memory cells are formed into the gate layers,

the isolation region 8 is formed to cover the gate layer and the bottom of the gate sidewall spacer 3, and isolate the gate layer from the substrate 1, as shown in fig. 4.

In further alternative embodiments, the step of forming an isolation region between the gate layers of the multiplexing electrodes in at least one group of adjacent memory cells includes:

wherein, the isolation region 8 is formed to cover a part of the bottom of the gate layer and the bottom of the gate sidewall 3 at the side far from the common electrode, and a part of the gate oxide layer 2 is communicated with the isolation region 8 to form the isolation between the gate layer and the substrate 1, as shown in fig. 5.

In some optional embodiments, the aforementioned process for forming the isolation region 8 is selected from: any one of a shallow trench isolation process, a local silicon oxidation isolation process, and a field oxide process. In various embodiments, the isolation regions 8 formed in the substrate 1 are Shallow Trench Isolation (STI) structures or local oxidation of silicon (LOCOS) isolation structures. As an example, in the present embodiment, the isolation region 8 is a shallow trench isolation structure. Various well structures or doped regions are also formed in the substrate 1, and are omitted from the drawings for simplicity.

It should be noted that the remaining structures, the process details thereof, and the overall process flow in the integrated circuit are well known in the art and are not described herein.

In addition, in each of the foregoing embodiments, before depositing the polysilicon layer 4, a step of removing the gate sidewall 3 located on a portion of the gate layer sidewall may be further included, where the portion of the gate layer structure is interconnected with the polysilicon layer by removing the exposed portion of the gate sidewall 3.

It is understood that the method for connecting electrodes in the active area and the gate area of an integrated circuit described in the present embodiment includes not only the above steps, but also other required manufacturing steps before, during or after the above steps, which are included in the scope of the manufacturing method of the present embodiment.

It can be understood that the electrode connection method in the active region and the gate region provided by the present invention can be used not only for the static random access memory device, but also for manufacturing other devices with interconnected polysilicon layers.

Example three:

the present disclosure also provides an electronic device including the integrated circuit provided in the foregoing exemplary embodiments of the present disclosure. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device is more beneficial to the miniaturization of a chip due to the use of the integrated circuit, and has better performance on the same size of the chip.

In summary, various embodiments of the present disclosure provide an integrated circuit and an electrode connection method for an active region and a gate region thereof, wherein the integrated circuit includes a plurality of memory cells, and the memory cells include: an active region and a gate layer disposed on the substrate 1, the active region including a source terminal at one side of the gate layer and a drain terminal at the other side of the gate layer: the source electrode S and the gate electrode G are respectively communicated to the source end and the gate electrode layer by multiplexing the first lead through hole 61, and the drain electrode D is communicated to the drain end by the second lead through hole 62. Therefore, the ohmic contact of the common electrode can be formed by multiplexing the same lead through hole 61 by the adjacent electrodes in the same storage unit, so that the distance between the two adjacent electrodes is reduced, the area of a single storage unit is further reduced, and/or the ohmic contact of the common electrode is formed by multiplexing the same lead through hole by the adjacent electrodes between the two adjacent storage units, the areas of the two adjacent storage units are further reduced, the area of a semiconductor chip is reduced, and the storage density is improved.

It is to be understood that the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.

Claims

1. An integrated circuit comprising a plurality of memory cells, the memory cells comprising:

the semiconductor device comprises an active region and a grid layer, wherein the active region and the grid layer are arranged on a substrate, the active region comprises a source end positioned on one side of the grid layer and a drain end positioned on the other side of the grid layer:

the source electrode and the gate electrode are respectively communicated to the source end and the gate layer by multiplexing a first lead through hole, and the drain electrode is communicated to the drain end by a second lead through hole.

2. The integrated circuit of claim 1, wherein the gate layer comprises:

the first lead through hole exposes a part of the source end and a part of the surface of the polycrystalline silicon layer.

3. The integrated circuit of claim 2, further comprising:

the dielectric layer is positioned between the substrate and the source electrode, and the first lead through hole penetrates through the dielectric layer to be communicated with the source electrode and the source end; and

4. The integrated circuit of claim 3, wherein adjacent electrodes between at least one group of adjacent memory cells in the integrated circuit are in ohmic contact with a common electrode by multiplexing the same lead through hole,

5. The integrated circuit of claim 4, wherein the isolation region is disposed between a gate layer of the memory cell and a substrate, and covers the gate layer and a bottom of the gate sidewall to isolate the gate layer from the substrate.

6. The integrated circuit of claim 4, wherein the isolation region is disposed between a gate layer of the memory cell and a substrate, and covers a portion of a bottom of the gate layer and a bottom of a gate sidewall on one side, and a portion of the gate oxide communicates with the isolation region to form an isolation between the gate layer and the substrate.