CN216981896U - Analog-to-digital converter, integrated circuit, and electronic device - Google Patents
Analog-to-digital converter, integrated circuit, and electronic device Download PDFInfo
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- CN216981896U CN216981896U CN202123416574.1U CN202123416574U CN216981896U CN 216981896 U CN216981896 U CN 216981896U CN 202123416574 U CN202123416574 U CN 202123416574U CN 216981896 U CN216981896 U CN 216981896U
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Abstract
The embodiment of the application provides an analog-to-digital converter, an integrated circuit and electronic equipment, wherein the analog-to-digital converter comprises a reference generating circuit, a reference switching circuit, an integrating circuit and a comparison circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter provided by the application can effectively reduce the circuit area.
Description
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to an analog-to-digital converter, an integrated circuit, and an electronic device.
Background
Flash Analog to Digital Converter (Flash ADC) is also called full parallel ADC, and is characterized by being capable of converting a sampling signal into binary data in one step and having high conversion rate. The conventional Flash ADC completes voltage conversion in one clock cycle in a fully parallel manner, and specifically, a plurality of comparators compare a sampling signal with a unique reference signal at the same time. Therefore, the conventional Flash ADC needs to use more comparators, resulting in a larger circuit area.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, embodiments of the present application provide an analog-to-digital converter, an integrated circuit, and an electronic device to solve the above technical problems.
The embodiment of the application adopts the following technical scheme to solve the technical problems.
An analog-to-digital converter comprises a reference generating circuit, a reference switching circuit, an integrating circuit and a comparing circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit.
In some embodiments, the reference switching circuit comprises a first at least two switching circuits, the integrating circuit comprises at least two switched-capacitor integrating circuits, and the comparing circuit comprises at least two comparators; the first end of each switch circuit is connected to the output end of the reference generating circuit, one end of each integration circuit is correspondingly connected to the first end of one switch circuit, and the other end of each integration circuit is correspondingly connected to the input end of one comparator.
In some embodiments, the at least two switching circuits include a first switching circuit and a second switching circuit; the at least two switched-capacitor integrating circuits comprise a first switched-capacitor integrating circuit and a second switched-capacitor integrating circuit; the at least two comparison circuits comprise a first comparator and a second comparator; the first end of the first switch circuit is connected with the output end of the reference generating circuit, the second end of the first switch circuit is connected with the first end of the first switch capacitance integrating circuit, and the second end of the first switch capacitance integrating circuit is connected with the input end of the first comparator; the first end of the second switch circuit is connected with the output end of the reference generating circuit, the second end of the second switch circuit is connected with the first end of the second switch capacitance integrating circuit, and the second end of the second switch capacitance integrating circuit is connected with the input end of the second comparator.
In some embodiments, the first switch circuit includes a first switch set and a second switch set; one end of the first switch group is connected with the output end of the reference generating circuit, and the other end of the first switch group is connected with the first switched capacitor integrating circuit; one end of the second switch group is connected with the output end of the reference generating circuit, and the other end is connected with the first switch capacitance integrating circuit.
In some embodiments, the second switch circuit includes a third switch group and a fourth switch group; one end of the third switch group is connected with the output end of the reference generating circuit, and the other end of the third switch group is connected with the second switched capacitor integrating circuit; one end of the fourth switch group is connected with the output end of the reference generating circuit, and the other end of the fourth switch group is connected with the second switched capacitance integrating circuit.
In some embodiments, the first comparator comprises a first input and a second input; the first switch capacitance integrating circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor and a second capacitor; the first end of the first switch is used for receiving a first input signal, the second end of the first switch is connected to one end of a first capacitor, the second end of the first capacitor is connected to the first end of a second switch, the second end of the second switch is connected to the first input end of a first comparator, and the second end of the first switch is also connected to a first switch circuit; the first end of the third switch is used for receiving a second input signal, the second end of the third switch is connected to one end of the second capacitor, the second end of the second capacitor is connected to the first end of the fourth switch, the second end of the second switch is connected to the second input end of the second comparator, and the second end of the third switch is also connected to the first switch circuit; the first end of the fifth switch is connected to the first end of the second switch, the first end of the sixth switch is connected to the first end of the fourth switch, the second end of the fifth switch is connected to the second end of the sixth switch, and the connection node of the fifth switch and the sixth switch is used for receiving the common-mode signal.
In some embodiments, the second comparator comprises a first input and a second input; the second switch capacitance integrating circuit comprises a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a third capacitor and a fourth capacitor; the first end of the seventh switch is used for receiving the first input signal, the second end of the seventh switch is connected to one end of the second capacitor, the second end of the second capacitor is connected to the first end of the eighth switch, the second end of the eighth switch is connected to the first input end of the second comparator, and the second end of the seventh switch is also connected to the second switch circuit; a first end of the ninth switch is used for receiving a second input signal, a second end of the ninth switch is connected to one end of the second capacitor, a second end of the second capacitor is connected to a first end of the tenth switch, a second end of the tenth switch is connected to a second input end of the second comparator, and a second end of the ninth switch is further connected to the second switch circuit; the first end of the eleventh switch is connected to the first end of the eighth switch, the first end of the twelfth switch is connected to the first end of the tenth switch, the second end of the eleventh switch is connected to the second end of the twelfth switch, and a connection node between the eleventh switch and the twelfth switch is used for receiving the common mode signal.
In some embodiments, the analog-to-digital converter further includes a first reset switch, one end of the first reset switch is connected to the first input terminal of the first comparator, and the other end of the first reset switch is connected to the second input terminal of the first comparator.
In some embodiments, the analog-to-digital converter further comprises a second reset switch, one end of the second reset switch is connected to the first input end of the second comparator, and the other end of the second reset switch is connected to the second input end of the second comparator.
An integrated circuit comprising an analog-to-digital converter as described above.
An electronic device comprises a device body and the integrated circuit arranged on the device body.
The analog-to-digital converter, the integrated circuit and the analog-to-digital converter provided by the embodiment of the application comprise a reference generating circuit, a reference switching circuit, an integrating circuit and a comparing circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter switches different reference signals to the integrating circuit in different clock periods and sends the reference signals to the comparator for comparison, and therefore the analog-to-digital converter does not need to use a plurality of comparators in the conversion process, and the circuit area can be effectively reduced.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a block diagram of an analog-to-digital converter according to an embodiment of the present application.
Fig. 2 shows another block diagram of an analog-to-digital converter according to an embodiment of the present application.
Fig. 3 shows a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present application.
Fig. 4 is a schematic diagram illustrating an operation principle of an analog-to-digital converter according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Flash Analog to Digital Converter (Flash ADC) is also called full parallel ADC, and is characterized by being capable of converting a sampling signal into binary data in one step and having high conversion rate. The conventional Flash ADC usually adopts a parallel integration mode, i.e., a plurality of different integration circuits and comparators are used for integration, and each integration circuit receives a reference signal, so that multiple times of integration can be completed within one clock cycle, and conversion from an analog voltage signal to a digital voltage signal is completed. Although the conversion time of the traditional FlashADC is short, the circuit area is overlarge and the cost is high due to the fact that a plurality of integrating circuits and comparators are used.
In order to solve the above technical problem, the inventors have made a long-term study to provide an analog-to-digital converter, an integrated circuit, and an electronic device in the embodiments of the present application, the analog-to-digital converter including a reference generating circuit, a reference switching circuit, an integrating circuit, and a comparing circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter switches different reference signals to the integrating circuit in different clock periods and sends the reference signals to the comparator for comparison, and therefore the analog-to-digital converter does not need to use a plurality of comparators in the conversion process, and the circuit area can be effectively reduced.
As shown in fig. 1, fig. 1 shows a block diagram of an analog-to-digital converter 100 provided in an embodiment of the present application. The analog-to-digital converter 100 includes a reference generating circuit 110, a reference switching circuit 120, an integrating circuit 130, and a comparing circuit 140. Wherein, one end of the reference switching circuit 120 is connected to the reference generating circuit 110, and the other end is connected to the integrating circuit 130; the comparator circuit 140 is connected to the output of the integrator circuit 130.
In this embodiment, the reference generating circuit 110 is configured to generate a plurality of reference signals, and the reference switching circuit 120 is configured to switch different reference signals to the input end of the integrating circuit 130 in different clock cycles, and then input the different reference signals to the comparing circuit 140 through the integrating circuit 130, so that the comparing circuit 140 has different comparison references in different clock cycles. For example, if the input signal of the comparison circuit 140 is a differential signal, the reference switching circuit 120 may switch the first reference signal and the second reference signal to the integration circuit 130 in the first clock cycle, and then input the first reference signal and the second reference signal to the comparison circuit 140 through the integration circuit 130, so that the reference signals of the comparison circuit 140 in the first clock cycle are the first reference signal and the second reference signal; and the third reference signal and the fourth reference signal may be switched to the integrating circuit 130 in the second clock cycle, and then input to the comparing circuit 140 through the integrating circuit 130, so that the reference signals of the comparing circuit 140 in the second clock cycle are the third reference signal and the fourth reference signal. If the input signal of the comparing circuit 140 is a single-ended signal, the reference switching circuit 120 may switch the first reference signal to the integrating circuit 130 in the first clock cycle, and input the first reference signal to the comparing circuit 140 through the integrating circuit 130, so that the reference signal of the comparing circuit 140 in the first clock cycle is the first reference signal; and the third reference signal may be switched to the integrating circuit 130 in the second clock cycle and input to the comparing circuit 140 through the integrating circuit 130, so that the reference signal of the comparing circuit 140 in the second clock cycle is the third reference signal.
Therefore, the analog-to-digital converter 100 of the present application can complete multiple integrations without using multiple integrating circuits 130 and comparison circuits 140 by switching different reference signals to the integrating circuit 130 in different clock periods, thereby effectively reducing the circuit size and circuit cost.
In some embodiments, reference switching circuit 120 comprises at least two switching circuits, integrating circuit 130 comprises at least two switched-capacitor integrating circuits, and comparing circuit 140 comprises at least two comparators. A first terminal of each switch circuit is connected to the output terminal of the reference generating circuit 110, one terminal of each integrating circuit 130 is correspondingly connected to a first terminal of one switch circuit, and the other terminal of each integrating circuit 130 is correspondingly connected to an input terminal of one comparator.
In this embodiment, a 4-bit Flash ADC is taken as an example. As shown in fig. 2, the at least two switching circuits include a first switching circuit 121 and a second switching circuit 122; the at least two switched-capacitor integrating circuits comprise a first switched-capacitor integrating circuit 131 and a second switched-capacitor integrating circuit 132; the at least two comparison circuits 140 include a first comparator 141 and a second comparator 142.
A first terminal of the first switching circuit 121 is connected to the output terminal of the reference generating circuit 110, a second terminal thereof is connected to a first terminal of the first switched-capacitor integrating circuit 131, and a second terminal of the first switched-capacitor integrating circuit 131 is connected to the input terminal of the first comparator 141; a first terminal of the second switching circuit 122 is connected to the output terminal of the reference generating circuit 110, a second terminal thereof is connected to a first terminal of the second switched-capacitor integrating circuit 132, and a second terminal of the second switched-capacitor integrating circuit 132 is connected to the input terminal of the second comparator 142.
Further, the first switch circuit 121 includes a first switch group 1211 and a second switch group 1212. One end of the first switch group 1211 is connected to the output end of the reference generating circuit 110, and the other end is connected to the first switched-capacitor integrating circuit 131; one end of the second switch 1212 is connected to the output terminal of the reference generating circuit 110, and the other end is connected to the first switched capacitor integrating circuit 131.
The second switch circuit 122 includes a third switch group 1221 and a fourth switch group 1222. One end of the third switch group 1221 is connected to the output end of the reference generating circuit 110, and the other end is connected to the second switched capacitor integrating circuit 132; one end of the fourth switch set 1222 is connected to the output end of the reference generating circuit 110, and the other end is connected to the second switched-capacitor integrating circuit 132.
Specifically, as shown in fig. 3, the first comparator 141 includes a first input terminal and a second input terminal; the first switched capacitor integrator 131 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a first capacitor C1, and a second capacitor C2; a first terminal of the first switch S1 is configured to receive the first input signal VIP, a second terminal of the first switch S1 is connected to a terminal of the first capacitor C1, a second terminal of the first capacitor C1 is connected to a first terminal of the second switch S2, a second terminal of the second switch S2 is connected to a first input terminal of the first comparator 141, and a second terminal of the first switch S1 is further connected to the first switch group 1211; a first terminal of the third switch S3 is configured to receive the second input signal VIN, a second terminal of the third switch S3 is connected to a terminal of the second capacitor C2, a second terminal of the second capacitor C2 is connected to a first terminal of the fourth switch S4, a second terminal of the fourth switch S4 is connected to the second input terminal of the second comparator 142, and a second terminal of the third switch S3 is further connected to the second switch group 1212; a first terminal of the fifth switch S5 is connected to a first terminal of the second switch S2, a first terminal of the sixth switch S6 is connected to a first terminal of the fourth switch S4, a second terminal of the fifth switch S5 is connected to a second terminal of the sixth switch S6, and a connection node of the fifth switch S5 and the sixth switch S6 is configured to receive the common-mode signal VCM.
The second comparator 142 includes a first input terminal and a second input terminal; the second switched-capacitor integrator circuit 132 includes a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a third capacitor C3, and a fourth capacitor C4; a first terminal of the seventh switch S7 is configured to receive the first input signal VIP, a second terminal of the seventh switch S7 is connected to one terminal of a third capacitor C3, a second terminal of the third capacitor C3 is connected to a first terminal of an eighth switch S8, a second terminal of the eighth switch S8 is connected to the first input terminal of the second comparator 142, and a second terminal of the seventh switch S7 is further connected to the third switch group 1221; a first terminal of the ninth switch S9 is configured to receive the second input signal VIN, a second terminal of the ninth switch S9 is connected to one terminal of the fourth capacitor C4, a second terminal of the fourth capacitor C4 is connected to a first terminal of the tenth switch S10, a second terminal of the tenth switch S10 is connected to the second input terminal of the second comparator 142, and a second terminal of the ninth switch S9 is further connected to the fourth switch group 1222; a first terminal of the eleventh switch S11 is connected to a first terminal of the eighth switch S8, a first terminal of the twelfth switch S12 is connected to a first terminal of the tenth switch S10, a second terminal of the eleventh switch S11 is connected to a second terminal of the twelfth switch S12, and a connection node of the eleventh switch S11 and the twelfth switch S12 is configured to receive the common mode signal VCM.
As shown in fig. 4, each of the first switch group 1211, the second switch group 1212, the third switch group 1221 and the fourth switch group 1222 may include a plurality of switches, and the specific number of switches may be adjusted according to the number of reference signals generated by the reference generating circuit 110. In the 4-bit Flash ADC, the reference generating circuit 110 may generate a plurality of reference signals (VREF 1-VREF 15) by dividing voltages of the resistor string, each of the first switch set 1211 and the second switch set 1212 may include 8 switches, and the 8 switches may be controlled by external phase selection signals (Φ 1- Φ 8) to switch different reference signals to the first switched capacitor integrating circuit 131 and the first comparator 141 in 8 different clock cycles, where the phases Φ 1- Φ 8 are 8 clock cycles; the third switch group 1221 and the fourth switch group 1222 may include 7 switches, respectively, and the 7 switches may be controlled by an external phase selection signal (Φ 1- Φ 7) to switch different reference signals to the second switched capacitor integrating circuit 131 and the second comparator 142 in 7 different clock cycles, where the phases Φ 1- Φ 7 are 7 clock cycles.
For example, the reference switching circuit 120 switches the reference signal VREF1 and the reference signal VREF15 to the first switched capacitance integrating circuit 131 by the phase selection signal Φ 1 during the clock cycle of the phase Φ 1, and takes the reference signals VREF1 and VREF15 as the reference signals of the input signal VIP and the input signal VIN, and at the same time, the reference switching circuit 1201122 also switches the reference signal VREF2 and the reference signal VREF14 to the second switched capacitance integrating circuit 132 by the phase selection signal Φ 1 during the clock cycle of the phase Φ 1, and takes the reference signal VREF2 and the reference signal VREF14 as the reference signals of the input signal VIP and the input signal VIN; the reference switching circuit 120 switches the reference signal VREF3 and the reference signal VREF13 to the first switched capacitance integrating circuit 131 by the phase selection signal Φ 2 in the clock cycle of the phase Φ 2, and takes the reference signal VREF3 and the reference signal VREF13 as the reference signals of the input signal VIP and the input signal VIN, and at the same time, the reference switching circuit 120 also switches the reference signal VREF4 and the reference signal VREF12 to the second switched capacitance integrating circuit 132 by the phase selection signal Φ 2 in the clock cycle of the phase Φ 2, and takes the reference signal VREF3 and the reference signal VREF13 as the reference signals of the input signal VIP and the input signal VIN. And finally, storing the comparison result of the first comparator 141 and the second comparator 142 every time according to the phase (phi 1-phi 8) to form a 15-bit thermometer code, thereby realizing the function of a 4-bit Flash ADC.
Compared with the traditional 4-bit Flash ADC, the 4-bit Flash ADC has the advantages that 15 comparators 1124 are needed for comparison operation when the 15-bit thermometer code is formed, and compared with the traditional 4-bit Flash ADC, the number of the comparators 1124 is reduced to 2 from 15, so that the circuit area is effectively reduced, and the circuit cost is greatly reduced.
In some embodiments, the analog-to-digital converter 100 further includes a first reset switch SR1 and a second reset switch SR2, wherein one end of the first reset switch SR1 is connected to the first input terminal of the first comparator 141, and the other end thereof is connected to the second input terminal of the first comparator 141; the second reset switch SR2 has one end connected to the first input terminal of the second comparator 142 and the other end connected to the second input terminal of the second comparator 142. The first and second reset switches SR1 and SR2 may reset the first and second comparators 141 and 142, respectively.
The analog-to-digital converter provided by the embodiment of the application comprises a reference generating circuit, a reference switching circuit, an integrating circuit and a comparison circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter switches different reference signals to the integrating circuit in different clock periods and sends the reference signals to the comparator for comparison, and therefore the analog-to-digital converter does not need to use a plurality of comparators in the conversion process, and the circuit area can be effectively reduced.
Embodiments of the present application further provide an integrated circuit, which includes any one of the analog-to-digital converters described above.
The analog-to-digital converter in the integrated circuit provided by the embodiment of the application comprises a reference generating circuit, a reference switching circuit, an integrating circuit and a comparison circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter switches different reference signals to the integrating circuit in different clock cycles and sends the reference signals to the comparator for comparison, and therefore the analog-to-digital converter does not need to use a plurality of comparators in the conversion process, and the circuit area can be effectively reduced.
The embodiment of the application also provides electronic equipment which comprises an equipment main body and the analog-to-digital converter arranged on the equipment main body.
In this embodiment, the electronic device includes, but is not limited to, smart bracelet, smart watch, steering wheel, electronic scale, electrocardio check out test set.
The analog-to-digital converter in the electronic equipment provided by the embodiment of the application comprises a reference generating circuit, a reference switching circuit, an integrating circuit and a comparison circuit; the reference generating circuit is used for generating a plurality of reference signals; one end of the reference switching circuit is connected with the reference generating circuit, the other end of the reference switching circuit is connected with the integrating circuit, and the reference switching circuit is used for switching different reference signals to the input end of the integrating circuit in different clock periods; the comparison circuit is connected to the output end of the integration circuit. The analog-to-digital converter switches different reference signals to the integrating circuit in different clock cycles and sends the reference signals to the comparator for comparison, and therefore the analog-to-digital converter does not need to use a plurality of comparators in the conversion process, and the circuit area can be effectively reduced.
Although the present application has been described with reference to the preferred embodiments, it is to be understood that the present application is not limited to the disclosed embodiments, but rather, the present application is intended to cover various modifications, equivalents and alternatives falling within the spirit and scope of the present application.
Claims (11)
1. An analog-to-digital converter, comprising: a reference generating circuit, a reference switching circuit, an integrating circuit and a comparing circuit;
the reference generating circuit is used for generating a plurality of reference signals;
one end of the reference switching circuit is connected with the reference generating circuit, and the other end of the reference switching circuit is connected with the integrating circuit so as to switch different reference signals to the input end of the integrating circuit in different clock cycles;
the comparison circuit is connected to the output end of the integration circuit.
2. The analog-to-digital converter of claim 1, wherein the reference switching circuit comprises at least two switching circuits, the integrating circuit comprises at least two switched-capacitor integrating circuits, and the comparing circuit comprises at least two comparators; the first end of each switch circuit is connected to the output end of the reference generation circuit, one end of each integration circuit is correspondingly connected to the first end of one switch circuit, and the other end of each integration circuit is correspondingly connected to the input end of one comparator.
3. The analog-to-digital converter of claim 2, wherein the at least two switching circuits comprise a first switching circuit and a second switching circuit; the at least two switched capacitance integration circuits comprise a first switched capacitance integration circuit and a second switched capacitance integration circuit; the at least two comparison circuits comprise a first comparator and a second comparator;
a first end of the first switch circuit is connected to the output end of the reference generating circuit, a second end of the first switch circuit is connected to the first end of the first switch capacitance integrating circuit, and the second end of the first switch capacitance integrating circuit is connected to the input end of the first comparator;
the first end of the second switch circuit is connected to the output end of the reference generating circuit, the second end of the second switch circuit is connected to the first end of the second switch capacitance integrating circuit, and the second end of the second switch capacitance integrating circuit is connected to the input end of the second comparator.
4. The analog-to-digital converter of claim 3, wherein the first switching circuit comprises:
a first switch group, one end of which is connected to the output end of the reference generating circuit, and the other end of which is connected to the first switched capacitor integrating circuit; and
and one end of the second switch group is connected to the output end of the reference generating circuit, and the other end of the second switch group is connected to the first switched capacitor integrating circuit.
5. The analog-to-digital converter of claim 3, wherein the second switching circuit comprises:
a third switch group, one end of which is connected to the output end of the reference generating circuit, and the other end of which is connected to the second switched capacitance integrating circuit; and
and one end of the fourth switch group is connected to the output end of the reference generating circuit, and the other end of the fourth switch group is connected to the second switched capacitor integrating circuit.
6. The analog-to-digital converter of claim 3, wherein the first comparator comprises a first input and a second input; the first switch capacitance integrating circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor and a second capacitor;
the first end of the first switch is used for receiving a first input signal, the second end of the first switch is connected to one end of the first capacitor, the second end of the first capacitor is connected to the first end of the second switch, the second end of the second switch is connected to the first input end of the first comparator, and the second end of the first switch is further connected to the first switch circuit;
a first end of the third switch is configured to receive a second input signal, a second end of the third switch is connected to one end of the second capacitor, a second end of the second capacitor is connected to a first end of the fourth switch, a second end of the fourth switch is connected to a second input end of the second comparator, and a second end of the third switch is further connected to the first switch circuit;
the first end of the fifth switch is connected to the first end of the second switch, the first end of the sixth switch is connected to the first end of the fourth switch, the second end of the fifth switch is connected to the second end of the sixth switch, and the connection node of the fifth switch and the sixth switch is used for receiving the common-mode signal.
7. The analog-to-digital converter of claim 3, wherein the second comparator comprises a first input and a second input; the second switch capacitance integrating circuit comprises a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a third capacitor and a fourth capacitor;
a first end of the seventh switch is configured to receive a first input signal, a second end of the seventh switch is connected to one end of the third capacitor, a second end of the third capacitor is connected to a first end of the eighth switch, a second end of the eighth switch is connected to the first input end of the second comparator, and a second end of the seventh switch is further connected to the second switch circuit;
a first end of the ninth switch is configured to receive a second input signal, a second end of the ninth switch is connected to one end of the fourth capacitor, a second end of the fourth capacitor is connected to a first end of the tenth switch, a second end of the tenth switch is connected to the second input end of the second comparator, and a second end of the ninth switch is further connected to the second switch circuit;
a first end of the eleventh switch is connected to a first end of the eighth switch, a first end of the twelfth switch is connected to a first end of the tenth switch, a second end of the eleventh switch is connected to a second end of the twelfth switch, and a connection node between the eleventh switch and the twelfth switch is configured to receive a common mode signal.
8. An analog-to-digital converter as claimed in any of claims 3 to 7, further comprising a first reset switch having one end connected to the first input of the first comparator and the other end connected to the second input of the first comparator.
9. An analog-to-digital converter as claimed in any of claims 3 to 7, further comprising a second reset switch having one end connected to the first input of the second comparator and the other end connected to the second input of the second comparator.
10. An integrated circuit comprising an analog-to-digital converter according to any of claims 1 to 9.
11. An electronic device comprising a device body and the integrated circuit according to claim 10 provided in the device body.
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| CN116185119A (en) * | 2023-04-23 | 2023-05-30 | 深圳市九天睿芯科技有限公司 | CIM-based voltage regulating circuit, chip and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116185119A (en) * | 2023-04-23 | 2023-05-30 | 深圳市九天睿芯科技有限公司 | CIM-based voltage regulating circuit, chip and electronic equipment |
| CN116185119B (en) * | 2023-04-23 | 2023-07-21 | 深圳市九天睿芯科技有限公司 | CIM-based voltage regulating circuit, chip and electronic equipment |
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