CN216904669U - LCD power circuit with controllable up and down electric time sequence and device - Google Patents
LCD power circuit with controllable up and down electric time sequence and device Download PDFInfo
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- CN216904669U CN216904669U CN202220456391.8U CN202220456391U CN216904669U CN 216904669 U CN216904669 U CN 216904669U CN 202220456391 U CN202220456391 U CN 202220456391U CN 216904669 U CN216904669 U CN 216904669U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model discloses a power supply circuit and a power supply device of a liquid crystal display with controllable power-on and power-off time sequences. The liquid crystal display power supply circuit comprises a controllable DC-DC booster circuit, a controllable charge pump booster circuit and a controllable charge pump negative pressure circuit, wherein the controllable charge pump booster circuit and the controllable charge pump negative pressure circuit are electrically connected with the controllable DC-DC booster circuit, the controllable DC-DC booster circuit boosts an external input voltage VCC _5V0_ SYS and outputs a voltage VCC _ LX as the input voltage of the controllable charge pump booster circuit and the controllable charge pump negative pressure circuit, and an external time sequence signal output device respectively outputs a time sequence signal AVDDEN _ H, VGHEN _ H, VGLEN _ H to the controllable DC-DC booster circuit, the controllable charge pump booster circuit and the controllable charge pump negative pressure circuit so as to respectively control the power-up and power-down of the controllable DC-DC booster circuit, the controllable charge pump booster circuit and the controllable charge pump negative pressure circuit. The power supply circuit of the liquid crystal display with controllable power-up and power-down time sequence, provided by the utility model, has a simple structure and can carry out time sequence control on the power-up and power-down of multiple power supplies of the liquid crystal display according to the requirements of the liquid crystal display.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a power supply circuit and a power supply device of a liquid crystal display with controllable power-on and power-off time sequences.
Background
The power supply circuit of the liquid crystal display mainly converts an external input voltage into a driving power supply and a positive and negative bias power supply required by the liquid crystal display, and the working stability of the power supply circuit directly influences whether the liquid crystal display can work normally. The power supply circuit of the liquid crystal display works strictly according to the power-on and power-off time sequence required by the liquid crystal display, can effectively solve the problems of screen flashing and screen blurring of the liquid crystal display, and is beneficial to prolonging the service life of the liquid crystal display. However, the power supply circuit of the liquid crystal display on the market at present has a complex structure, and is difficult to carry out time sequence control on multi-power supply power-up and power-down strictly according to the requirements of the liquid crystal display, or only can realize single power-up and power-down time sequence control.
SUMMERY OF THE UTILITY MODEL
The utility model aims to realize the control of the up-down power sequence of multiple power supplies of the liquid crystal display and solve the problems of screen flashing and screen blurring of the liquid crystal display, and provides the power supply circuit and the device of the liquid crystal display with controllable up-down power sequence, which have simple structures.
In order to achieve the purpose, the utility model adopts the following technical scheme:
provides a power supply circuit of a liquid crystal display with controllable power-up and power-down time sequences, which comprises a controllable DC-DC booster circuit, a controllable charge pump booster circuit and a controllable charge pump negative voltage circuit, wherein the controllable charge pump booster circuit and the controllable charge pump negative voltage circuit are electrically connected with the controllable DC-DC booster circuit, the controllable DC-DC booster circuit boosts an external input voltage VCC-5V 0-SYS, and outputs a voltage VCC _ LX as an input voltage of the controllable charge pump voltage-boosting circuit and the controllable charge pump negative voltage circuit, and an external timing signal output device outputs a timing signal AVDDEN _ H, VGHEN _ H, VGLEN _ H to the controllable DC-DC voltage-boosting circuit, the controllable charge pump voltage-boosting circuit, and the controllable charge pump negative voltage circuit, respectively, so as to respectively control the power-up and power-down of the controllable DC-DC booster circuit, the controllable charge pump booster circuit and the controllable charge pump negative voltage circuit.
As a preferable scheme of the present invention, the controllable DC-DC boost circuit includes a boost IC chip U1, a MOS transistor Q1, Q2, an inductor L1, a resistor R1, R2, R3, R4, R5, R6, a capacitor C1, C2, C3, C4, and a zener diode D1, an interface 5 of the boost IC chip U1 is connected to a drain of the MOS transistor Q1, a source of the MOS transistor Q1 is connected to the ground after being connected to the capacitor C1 and is externally connected to the external input voltage VCC _5V0_ SYS, and a gate of the MOS transistor Q1 is connected to the drain of the MOS transistor Q2 after being connected to the resistor R2 in series; the source electrode of the MOS tube Q2 is grounded, and the grid electrode is externally connected with the timing signal AVDDEN _ H;
the capacitor C2 is connected between the source and the gate of the MOS transistor Q1; the resistor R1 is connected in parallel with two ends of the capacitor C2;
one end of each of the capacitors C3, C4 and R6 is connected with the cathode of the voltage stabilizing diode D1, and the other end of each of the capacitors is grounded; the cathode voltage of the zener diode D1 is used as the output voltage AVDD obtained by the controllable DC-DC boost circuit after boosting the voltage VCC _5V0_ SYS input from the outside.
In a preferred embodiment of the present invention, the boost IC chip U1 is of the type MT 3608.
As a preferred aspect of the present invention, the controllable charge pump voltage boost circuit includes MOS transistors Q3, Q4, resistors R7-R11, capacitors C5-C11, diodes D21, D22, and a zener diode D4, one end of the capacitor C5 is connected to the voltage VCC _ LX output by the controllable DC-DC voltage boost circuit, and the other end of the capacitor C5 is connected in series to the diode D22 connected in the positive direction, the resistor R8 is connected to the source of the MOS transistor Q3 in sequence, and is connected in series to the diode D21 connected in the reverse direction, and the capacitor C6 is connected to the ground in sequence; the drain voltage of the MOS transistor Q3 is used as the output voltage VGH _ LCD of the controllable charge pump booster circuit, the gate of the MOS transistor Q3 is connected in series with the resistor R11 and then is connected with the drain of the MOS transistor Q4, the source of the MOS transistor Q4 is grounded, and the gate is externally connected with the timing signal VGHEN _ H;
the capacitor C11 is connected between the source and the gate of the MOS transistor Q3; the resistor R10 is connected in parallel with two ends of the capacitor C11;
one end of the capacitor C7 is connected to the intersection B of the diode D22 and the resistor R8, and the other end is grounded; one end of the resistor R9 is connected to the intersection point C of the resistor R8 and the source electrode of the MOS transistor Q3, and the other end is grounded; the cathode of the voltage stabilizing diode D4 is connected to the intersection point C, and the anode is grounded; one end of each capacitor C9 and C10 is connected to the intersection point C, and the other end of each capacitor is grounded; one end of the capacitor C8 is connected to the intersection C, the other end is connected to the output voltage AVDD of the controllable DC-DC boost circuit and to one end of the resistor R7, and the other end of the resistor R7 is connected to the anode of the diode D21.
As a preferable aspect of the present invention, the controllable charge pump voltage boost circuit further includes an adjustable resistor R12, one end of the adjustable resistor R12 is connected to the drain of the MOS transistor Q3, and the other end is grounded.
As a preferable scheme of the present invention, the controllable charge pump negative voltage circuit includes MOS transistors Q5, Q6, Q7, resistors R13-R15, R18, R19, capacitors C12-C15, diodes D31, D32, and a zener diode D5, wherein one end of the capacitor C12 is connected to the voltage VCC _ LX output by the controllable DC-DC voltage boost circuit, and the other end of the capacitor C12 is connected in series to the diode D32 and the resistor R13 in series, then connected to the source of the MOS transistor Q5, and connected in series to the diode D31 in reverse connection, and then grounded; one end of the capacitor C13 is connected to the intersection point D of the diode D32 and the resistor R13, and the other end is grounded;
the drain voltage of the MOS transistor Q5 is used as the output voltage VGL _ LCD of the controllable charge pump negative voltage circuit, the gate of the MOS transistor Q5 is connected in series with the resistor R16 and then is connected with the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is externally connected with the voltage VCC3V3_ SYS, the gate of the MOS transistor Q5 is connected in series with the resistor R19 and then is connected with the drain of the MOS transistor Q7, the source of the MOS transistor Q7 is grounded, and the gate is externally connected with the timing signal VGLEN _ H;
the resistor R18 is connected between the gate and the source of the MOS transistor Q6; the resistor R15 is connected between the source and the gate of the MOS transistor Q5; the capacitor C15 is connected in parallel with two ends of the resistor R15; one end of the capacitor C14 is connected with the source electrode of the MOS transistor Q5, and the other end of the capacitor C14 is grounded; the anode of the voltage stabilizing diode D5 is connected with the source electrode of the MOS transistor Q5, and the cathode of the voltage stabilizing diode D5 is grounded; one end of the resistor R14 is connected with the source electrode of the MOS transistor Q5, and the other end is grounded.
As a preferable aspect of the present invention, the charge pump negative voltage further includes an adjustable resistor R17, one end of the adjustable resistor R17 is connected to the drain of the MOS transistor Q5, and the other end is grounded.
The utility model also provides a device, wherein the power supply circuit of the liquid crystal display with the controllable power-up and power-down time sequence is arranged in the device.
The liquid crystal display power supply circuit with the controllable power-on and power-off time sequence, provided by the utility model, has a simple structure, can carry out time sequence control on the power-on and power-off of multiple power supplies of the liquid crystal display according to the requirements of the liquid crystal display, effectively solves the problems of screen flashing and screen blurring of the liquid crystal display caused by the fact that the existing liquid crystal display power supply circuit does not work according to the power-on and power-off time sequence required by the liquid crystal display strictly, and prolongs the service life of the liquid crystal display.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the utility model, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a block diagram of a controllable DC-DC boost circuit;
FIG. 2 is a block diagram of a controllable charge pump boost circuit;
fig. 3 is a block diagram of a controllable charge pump negative voltage circuit.
Detailed Description
The technical scheme of the utility model is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The power supply circuit of the liquid crystal display with controllable power-up and power-down time sequence provided by the embodiment of the utility model comprises a controllable DC-DC booster circuit, a controllable charge pump booster circuit electrically connected with the controllable DC-DC booster circuit and a controllable charge pump negative voltage circuit, wherein the controllable DC-DC booster circuit boosts an external input voltage VCC _5V0_ SYS and outputs a voltage VCC _ LX as the input voltage of the controllable charge pump booster circuit and the controllable charge pump negative voltage circuit, and an external time sequence signal output device CPU respectively outputs a time sequence signal AVDDEN _ H, VGHEN _ H, VGLEN _ H to the controllable DC-DC booster circuit, the controllable charge pump booster circuit and the controllable charge pump negative voltage circuit so as to respectively control power-up and power-down of AVDD, VGH _ LCD and VGL _ LCDD.
As for the specific structure of the controllable DC-DC boost circuit, as shown in fig. 1, the controllable DC-DC boost circuit includes a boost IC chip U1 (preferably, a boost IC chip with a model of MT3608, which is a boost IC chip that is relatively common to the western space and aviation civilian chips), MOS transistors Q1, Q2, an inductor L1, a resistor R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3, C4, and a zener diode D1, an interface 5 of the boost IC chip U1 is connected to a drain of the MOS transistor Q1, a source of the MOS transistor Q1 is connected to the capacitor C1 and then grounded and externally connected to the external input voltage VCC _5V0_ SYS, and a gate of the MOS transistor Q1 is connected to a drain of the MOS transistor Q2 after being connected to the resistor R2; the source electrode of the MOS tube Q2 is grounded, and the grid electrode is externally connected with the timing signal AVDDEN _ H;
the capacitor C2 is connected between the source and the gate of the MOS transistor Q1; the resistor R1 is connected in parallel with two ends of the capacitor C2;
one end of each of the capacitors C3, C4 and R6 is connected with the cathode of the voltage stabilizing diode D1, and the other end of each of the capacitors is grounded; the cathode voltage of the zener diode D1 is used as the output voltage AVDD obtained by boosting the voltage VCC _5V0_ SYS input from the controllable DC-DC boost circuit.
The working principle of controlling the power-on and power-off of the AVDD power supply by the timing signal AVDDEN _ H is as follows:
the CPU outputs AVDDEN _ H high level to control Q2 to be conducted, thereby controlling Q1 to be conducted, VCC5V0_ SYS is connected as an input power supply of a boost IC U1, the boost IC U1 starts to work, and VCC _ LX is output as the input of a positive and negative charge pump circuit while AVDD is controlled to be powered on. The CPU outputs AVDDEN _ H low level to control Q2 to be cut off, thereby controlling Q1 to be cut off, VCC5V0_ SYS is cut off as the input power supply of the boost IC U1, the boost IC U1 stops working, and VCC _ LX is interrupted as the input of the positive and negative charge pump circuits while AVDD is controlled to be powered down. R6 is used as an adjustable analog load resistor and can be used for adjusting the slope of the power-up and power-down of the AVDD, so that the timing error caused by the power-up and power-down rate of the AVDD is eliminated.
As shown in fig. 2, the controllable charge pump voltage boost circuit includes MOS transistors Q3, Q4, resistors R7-R11, capacitors C5-C11, diodes D21, D22, and a zener diode D4, wherein one end of the capacitor C5 is connected to the voltage VCC _ LX output by the controllable DC-DC voltage boost circuit, and the other end is connected in series to the diode D22 and the resistor R8 connected in series in sequence, and is connected to the source of the MOS transistor Q3 in series in sequence, and is connected in series to the diode D21 and the capacitor C6 connected in reverse in sequence and then grounded; the drain voltage of the MOS transistor Q3 is used as the output voltage VGH _ LCD of the controllable charge pump booster circuit, the gate of the MOS transistor Q3 is connected in series with the resistor R11 and then is connected with the drain of the MOS transistor Q4, the source of the MOS transistor Q4 is grounded, and the gate is externally connected with the timing signal VGHEN _ H;
the capacitor C11 is also connected between the source and the gate of the MOS transistor Q3; the resistor R10 is connected in parallel with two ends of the capacitor C11;
one end of the capacitor C7 is connected to the intersection B of the diode D22 and the resistor R8, and the other end is grounded; one end of the resistor R9 is connected to the intersection point C of the resistor R8 and the source electrode of the MOS transistor Q3, and the other end is grounded; the cathode of the voltage-stabilizing diode D4 is connected to the intersection point C, and the anode is grounded; one end of each of the capacitors C9 and C10 is connected to the intersection point C, and the other end is grounded; one end of the capacitor C8 is connected to the intersection C, the other end is connected to the output voltage AVDD of the controllable DC-DC boost circuit and to one end of the resistor R7, and the other end of the resistor R7 is connected to the anode of the diode D21.
In order to adjust the power-up and power-down slope of the VGH _ LCD, preferably, as shown in fig. 2, the controllable charge pump boost circuit further includes an adjustable resistor R12, one end of the adjustable resistor R12 is connected to the drain of the MOS transistor Q3, and the other end is grounded. The power-up and power-down slope of the VGH _ LCD can be adjusted by adjusting the resistance value of the resistor R12.
The principle that the VGHEN _ H controls the power-on and power-off of the VGH _ LCD power supply is as follows:
as shown in fig. 2, Q4 is controlled to be turned on by the high level of the CPU output VGHEN _ H, so that Q3 is controlled to be turned on, and the VGH _ LCD is controlled to be powered on; q4 is controlled to be turned off by the low level of the CPU output VGHEN _ H, so that Q3 is controlled to be turned off, and the VGH _ LCD is controlled to be powered down. Wherein, R12 is used as an adjustable analog load resistor for adjusting the slope of the power-up and power-down of the VGH _ LCD, thereby eliminating the timing error caused by the power-up and power-down rate of the VGH _ LCD.
As shown in fig. 3, the controllable charge pump negative voltage circuit includes MOS transistors Q5, Q6, Q7, resistors R13-R15, R18, R19, capacitors C12-C15, diodes D31, D32, and a zener diode D5, wherein one end of the capacitor C12 is connected to a voltage VCC _ LX output by the controllable DC-DC voltage boost circuit, and the other end of the capacitor C12 is connected in series with the diode D32 and the resistor R13 in series, then connected to the source of the MOS transistor Q5, and connected in series with the diode D31 in reverse connection, and then grounded; one end of the capacitor C13 is connected to the intersection point D of the diode D32 and the resistor R13, and the other end is grounded;
the drain voltage of the MOS tube Q5 is used as the output voltage VGL _ LCD of the controllable charge pump negative voltage circuit, the grid of the MOS tube Q5 is connected with the drain of the MOS tube Q6 after being connected with the resistor R16 in series, the source of the MOS tube Q6 is externally connected with the voltage VCC3V3_ SYS, the grid of the MOS tube Q5 is connected with the drain of the MOS tube Q7 after being connected with the resistor R19 in series, the source of the MOS tube Q7 is grounded, and the grid is externally connected with the timing signal VGLEN _ H;
the resistor R18 is connected between the gate and the source of the MOS transistor Q6; the resistor R15 is connected between the source and the gate of the MOS transistor Q5; the capacitor C15 is connected in parallel with two ends of the resistor R15; one end of the capacitor C14 is connected with the source electrode of the MOS transistor Q5, and the other end of the capacitor C14 is grounded; the anode of the voltage stabilizing diode D5 is connected with the source electrode of the MOS tube Q5, and the cathode is grounded; one end of the resistor R14 is connected with the source of the MOS transistor Q5, and the other end is grounded.
In order to adjust the power-up and power-down slope of the VGL _ LCD, preferably, as shown in fig. 3, the charge pump negative voltage further includes an adjustable resistor R17, one end of the adjustable resistor R17 is connected to the drain of the MOS transistor Q5, and the other end is grounded. The power-up and power-down slope of the VGL _ LCD can be adjusted by adjusting the resistance value of the resistor R17.
The principle that the VGLEN _ H controls the power-on and power-off of the VGL _ LCD power supply is as follows:
the Q7 is controlled to be conducted by the high level of the CPU output VGLEN _ H, so that the Q6 is controlled to be conducted, the Q5 is controlled to be conducted, and the VGL _ LCD is controlled to be powered on; q7 is controlled to be cut off by the low level of the CPU output VGLEN _ H, so that Q6 is controlled to be cut off, and Q5 is controlled to be cut off, so that VGL _ LCD is controlled to be powered down. Wherein R17 is used as an adjustable analog load resistor for adjusting the slope of the power-up and power-down of the VGL _ LCD, thereby eliminating the timing error caused by the power-up and power-down rate of the VGL _ LCD.
In summary, the power supply circuit of the liquid crystal display provided by the utility model realizes the accurate control of the power-on and power-off of the power supplies AVDD, VGH _ LCD and VGL _ LCD by matching with the timing signal AVDDEN _ H, VGHEN _ H, VGLEN _ H input by the external CPU, and meets the power-on and power-off timing required by the liquid crystal display.
The liquid crystal display power supply circuit with the controllable power-on and power-off time sequence can be arranged on the fire-fighting controller main board and the domestic panel main board, and the accurate control of power-on and power-off of the liquid crystal display power supplies AVDD, VGH _ LCD and VGL _ LCD can be realized by outputting the time sequence signal AVDDEN _ H, VGHEN _ H, VGLEN _ H through the CPU. The power-on time sequence of the CPU configuration time sequence signal AVDDEN _ H, VGHEN _ H, VGLEN _ H can meet the power-on and power-off time sequences required by different liquid crystal displays, thereby being compatible with various liquid crystal displays.
The utility model also provides a device, wherein the power supply circuit of the liquid crystal display with controllable power-up and power-down time sequence is arranged in the device.
It should be understood that the above-described embodiments are merely preferred embodiments of the utility model and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the utility model as long as they do not depart from the spirit of the utility model. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (8)
1. A power supply circuit of a liquid crystal display with controllable power-up and power-down time sequences is characterized by comprising a controllable DC-DC booster circuit, a controllable charge pump booster circuit and a controllable charge pump negative voltage circuit which are electrically connected with the controllable DC-DC booster circuit, the controllable DC-DC boost circuit boosts an external input voltage VCC _5V0_ SYS, and outputs a voltage VCC _ LX as an input voltage of the controllable charge pump voltage-boosting circuit and the controllable charge pump negative voltage circuit, and an external timing signal output device outputs a timing signal AVDDEN _ H, VGHEN _ H, VGLEN _ H to the controllable DC-DC voltage-boosting circuit, the controllable charge pump voltage-boosting circuit, and the controllable charge pump negative voltage circuit, respectively, so as to respectively control the power-up and power-down of the controllable DC-DC booster circuit, the controllable charge pump booster circuit and the controllable charge pump negative voltage circuit.
2. The LCD power supply circuit with controllable power-up and power-down time sequences of claim 1, wherein the controllable DC-DC boost circuit comprises a boost IC chip U1, MOS transistors Q1, Q2, an inductor L1, a resistor R1, R2, R3, R4, R5, R6, capacitors C1, C2, C3, C4 and a zener diode D1, an interface 5 of the boost IC chip U1 is connected with a drain of the MOS transistor Q1, a source of the MOS transistor Q1 is connected with the capacitor C1 and then grounded and externally connected with the external input voltage VCC _5V0_ SYS, and a gate of the MOS transistor Q1 is connected with the resistor R2 and then connected with a drain of the MOS transistor Q2; the source electrode of the MOS tube Q2 is grounded, and the grid electrode is externally connected with the timing signal AVDDEN _ H;
the capacitor C2 is connected between the source and the gate of the MOS transistor Q1; the resistor R1 is connected in parallel with two ends of the capacitor C2;
interface 2 of the boost IC chip U1 is grounded, interface 4 is connected with the drain of the MOS transistor Q1 after being connected with the resistor R3 in series, interface 6 is suspended, and interface 3 outputs the voltage VCC _ LX; the interface 5 of the boost IC chip U1 is further connected in series with the inductor L1, the zener diode D1, the resistor R4, and the resistor R5 in the positive direction in sequence and then grounded, and the interface 3 is connected to the intersection a of the resistor R4 and the resistor R5;
one end of each of the capacitors C3, C4 and the resistor R6 is connected with the cathode of the voltage stabilizing diode D1, and the other end of each of the capacitors C3, C4 and the resistor R6 is grounded; the cathode voltage of the zener diode D1 is used as the output voltage AVDD obtained by the controllable DC-DC boost circuit after boosting the voltage VCC _5V0_ SYS input from the outside.
3. The LCD power circuit with controllable power-on and power-off sequence of claim 2, wherein the voltage boost IC chip U1 is MT3608 type.
4. The power supply circuit of claim 1-3, wherein the controllable charge pump voltage boost circuit comprises MOS transistors Q3 and Q4, resistors R7 to R11, capacitors C5 to C11, diodes D21 and D22, and a Zener diode D4, one end of the capacitor C5 is connected to the voltage VCC _ LX outputted by the controllable DC-DC voltage boost circuit, the other end is connected in series with the diode D22 connected in the positive direction, the resistor R8 is connected to the source of the MOS transistor Q3, and the diode D21 and the capacitor C6 connected in the reverse direction are connected in series and then connected to the ground; the drain voltage of the MOS transistor Q3 is used as the output voltage VGH _ LCD of the controllable charge pump booster circuit, the gate of the MOS transistor Q3 is connected in series with the resistor R11 and then is connected with the drain of the MOS transistor Q4, the source of the MOS transistor Q4 is grounded, and the gate is externally connected with the timing signal VGHEN _ H;
the capacitor C11 is connected between the source and the gate of the MOS transistor Q3; the resistor R10 is connected in parallel with two ends of the capacitor C11;
one end of the capacitor C7 is connected to the intersection B of the diode D22 and the resistor R8, and the other end is grounded; one end of the resistor R9 is connected to the intersection point C of the resistor R8 and the source electrode of the MOS transistor Q3, and the other end is grounded; the cathode of the voltage stabilizing diode D4 is connected to the intersection point C, and the anode is grounded; one end of each capacitor C9 and C10 is connected to the intersection point C, and the other end of each capacitor is grounded; one end of the capacitor C8 is connected to the intersection C, the other end is connected to the output voltage AVDD of the controllable DC-DC boost circuit and to one end of the resistor R7, and the other end of the resistor R7 is connected to the anode of the diode D21.
5. The power supply circuit of claim 4, wherein the controllable charge pump voltage boost circuit further comprises an adjustable resistor R12, one end of the adjustable resistor R12 is connected to the drain of the MOS transistor Q3, and the other end is connected to ground.
6. The power supply circuit of LCD according to any of claims 1-3, wherein the controllable charge pump negative voltage circuit comprises MOS transistor Q5, Q6, Q7, resistors R13-R15, R18, R19, capacitors C12-C15, diodes D31, D32, and a zener diode D5, one end of the capacitor C12 is connected to the voltage VCC _ LX outputted by the controllable DC-DC voltage boost circuit, and the other end is connected in series to the diode D32 in positive connection, the resistor R13 is connected to the source of the MOS transistor Q5 in back, and the diode D31 in reverse connection is connected to ground; one end of the capacitor C13 is connected to the intersection point D of the diode D32 and the resistor R13, and the other end is grounded;
the drain voltage of the MOS transistor Q5 is used as the output voltage VGL _ LCD of the controllable charge pump negative voltage circuit, the gate of the MOS transistor Q5 is connected in series with the resistor R16 and then is connected with the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is externally connected with the voltage VCC3V3_ SYS, the gate of the MOS transistor Q5 is connected in series with the resistor R19 and then is connected with the drain of the MOS transistor Q7, the source of the MOS transistor Q7 is grounded, and the gate is externally connected with the timing signal VGLEN _ H;
the resistor R18 is connected between the gate and the source of the MOS transistor Q6; the resistor R15 is connected between the source and the gate of the MOS transistor Q5; the capacitor C15 is connected in parallel with two ends of the resistor R15; one end of the capacitor C14 is connected with the source electrode of the MOS transistor Q5, and the other end of the capacitor C14 is grounded; the anode of the voltage stabilizing diode D5 is connected with the source electrode of the MOS transistor Q5, and the cathode of the voltage stabilizing diode D5 is grounded; one end of the resistor R14 is connected with the source electrode of the MOS transistor Q5, and the other end is grounded.
7. The power supply circuit of claim 6, wherein the charge pump negative voltage further comprises an adjustable resistor R17, one end of the adjustable resistor R17 is connected to the drain of the MOS transistor Q5, and the other end is connected to ground.
8. A device in which a power supply circuit for a liquid crystal display whose power-up and power-down timings are controllable as claimed in any one of claims 1 to 7 is disposed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220456391.8U CN216904669U (en) | 2022-03-01 | 2022-03-01 | LCD power circuit with controllable up and down electric time sequence and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220456391.8U CN216904669U (en) | 2022-03-01 | 2022-03-01 | LCD power circuit with controllable up and down electric time sequence and device |
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| CN216904669U true CN216904669U (en) | 2022-07-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220456391.8U Active CN216904669U (en) | 2022-03-01 | 2022-03-01 | LCD power circuit with controllable up and down electric time sequence and device |
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| CN (1) | CN216904669U (en) |
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