CN216564661U - A transceiver circuit for two-way wireless charging - Google Patents
A transceiver circuit for two-way wireless charging Download PDFInfo
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- CN216564661U CN216564661U CN202122928756.0U CN202122928756U CN216564661U CN 216564661 U CN216564661 U CN 216564661U CN 202122928756 U CN202122928756 U CN 202122928756U CN 216564661 U CN216564661 U CN 216564661U
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract
The utility model discloses a transceiver circuit for bidirectional wireless charging, which comprises a resonance module, a rectification inversion module, a filtering module, a rectification control module, an inversion control module and a driving module, wherein the rectification inversion module is a full-bridge circuit formed by four field-effect tubes, two field-effect tubes form an upper bridge arm, the other two field-effect tubes form a lower bridge arm; when the transceiver circuit works in a transmitting state, the inverter control circuit detects the current of a coil in the resonant module and then outputs a driving signal to the driving module, and the driving module respectively controls the on and off of the four field effect transistors according to the received driving signal; the utility model can realize bidirectional wireless charging.
Description
Technical Field
The utility model belongs to the technical field of wireless charging, and particularly relates to a transceiver circuit for bidirectional wireless charging.
Background
Along with the development and progress of science, more and more electronic equipment appears in people's life, and electronic equipment needs to consume the electric energy when using, when the electric energy exhausts, needs to charge electronic equipment. When the charging mode is selected, the wireless charging can solve the problems existing in a plurality of wired power supplies, such as poor flexibility and convenience, easy abrasion of a conductor contact part, easy generation of sparks, potential safety hazards possibly caused by exposed power supply lines and the like. In particular, in some scenarios, it is necessary to wirelessly charge the storage battery carried by the device, and it is also necessary to wirelessly charge the storage battery carried by the device for other devices. For example, with the increasing application demand of the underwater unmanned underwater vehicle, and the energy supply of the underwater unmanned underwater vehicle to the sea buoy becomes a real problem which needs to be solved urgently, so that the charging and discharging problems of the battery carried in the underwater unmanned underwater vehicle are concerned by many researchers. The energy of the underwater unmanned underwater vehicle is supplied by a battery carried by the underwater unmanned underwater vehicle, and when the electric energy is about to be exhausted, the battery needs to be charged to supplement the energy. At present, the only mode is to carry out the wet-drawing operation, and the mode brings great potential safety hazard and inconvenience. When need carry out energy supply for showy intelligent monitoring equipment in the sea, current mode is with trading equipment and carry out incessant monitoring, and this mode needs manual operation to take trouble hard. Therefore, the traditional methods are seriously lagged, and some methods cannot be implemented, so that the continuous working condition of the underwater unmanned underwater vehicle is seriously influenced.
Disclosure of Invention
The utility model aims to solve the problem of bidirectional wireless charging and provides a transceiver circuit for bidirectional wireless charging.
In order to achieve the purpose, the utility model adopts the following technical scheme:
a transceiver circuit for bidirectional wireless charging comprises a resonance module, a rectification inversion module, a filtering module, a rectification control module, an inversion control module and a driving module, wherein the resonance module, the rectification inversion module and the filtering module are sequentially connected; the receiving and transmitting circuit has two working states of receiving and transmitting, when the receiving circuit works in the receiving state, the resonance module is used for receiving alternating electric energy, the rectification inversion module is used for converting the alternating electric energy into direct current electric energy, and the filtering module is used for filtering the direct current electric energy; when the wireless power transmission device works in a transmitting state, the filtering module is used for filtering received direct current electric energy, the rectifying and inverting module is used for converting the direct current electric energy into alternating electric energy, and the resonance module is used for transmitting the alternating electric energy; the rectification inversion module is a full-bridge circuit formed by four field effect transistors, wherein two field effect transistors form an upper bridge arm of the full-bridge circuit, the other two field effect transistors form a lower bridge arm of the full-bridge circuit, when the transceiver circuit works in a receiving state, the rectification control module detects voltages of source electrodes and drain electrodes of the two field effect transistors of the lower bridge arm and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the four field effect transistors to be switched on and off according to the received driving signal; the resonance module comprises a coil and a second capacitor which are connected in series, when the transceiver circuit works in a transmitting state, the inverter control circuit detects the current of the coil and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the on and off of the four field effect transistors according to the received driving signal. The wireless charging device is provided with the resonance module, the rectification inversion module and the filtering module, the receiving working state and the transmitting working state are controlled through the rectification control module and the inversion control module, and in the specific implementation, the storage battery of the device is connected behind the filtering module, so that the alternating current electric energy provided by external wireless charging equipment is converted into the direct current electric energy to charge the storage battery in the receiving state, and the direct current electric energy provided by the storage battery is converted into the alternating current electric energy to wirelessly charge other devices in the transmitting state.
The technical scheme of the utility model is further limited, the four field effect transistors are respectively a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor, the four field effect transistors are all N-type insulated gate bipolar transistors with damping diodes, the first field effect transistor and the second field effect transistor form an upper bridge arm, and the third field effect transistor and the fourth field effect transistor form a lower bridge arm; resistors and diodes which are connected in parallel are connected between the grid electrodes and the source electrodes of the four field effect transistors, and the diodes are bidirectional transient suppression diodes; the grid electrodes of the four field effect tubes are connected in series with resistors and then serve as the grid electrode input end of each field effect tube; the drain electrode of the fourth field effect tube is connected with the source electrode of the second field effect tube to serve as the first input end of the bidirectional synchronous rectification circuit, the drain electrode of the second field effect tube is connected with the drain electrode of the first field effect tube to serve as the positive output end of the bidirectional synchronous rectification circuit, the source electrode of the first field effect tube is connected with the drain electrode of the third field effect tube to serve as the second input end of the bidirectional synchronous rectification circuit, and the source electrode of the third field effect tube is connected with the source electrode of the fourth field effect tube to serve as the negative output end of the bidirectional synchronous rectification circuit; and the first end of the coil is connected with the first input end of the synchronous rectification circuit after being connected with the second capacitor in series, and the second end of the coil is connected with the second input end of the synchronous rectification circuit. The field effect transistor adopts an N-type insulated gate bipolar transistor with a damping diode, and has the advantages of small driving power and low saturation voltage drop; the resistors and the diodes which are connected in parallel are connected between the grid electrodes and the source electrodes of the four field effect transistors, so that the field effect transistors can be prevented from generating high-voltage breakdown, and the effect of protecting the field effect transistors is achieved. When the circuit is used, one pair of field effect transistors is turned off, and the other pair of field effect transistors is turned on, so that a corresponding loop is formed.
The technical scheme of the utility model is further limited, the driving module comprises a first driving chip and a second driving chip, the first driving chip and the second driving chip are both MOS field effect transistor driving chips, a high-end output pin of the first driving chip is connected with a gate input end of a first field effect transistor, a high-end floating power offset voltage pin of the first driving chip is connected with a source electrode of the first field effect transistor, a low-end output pin of the first driving chip is connected with a gate input end of a second field effect transistor, and a common end pin of the first driving chip is connected with a source electrode of the second field effect transistor; the high-end output pin of the second driving chip is connected with the grid input end of the third field effect transistor, the high-end floating power supply offset voltage pin of the second driving chip is connected with the source electrode of the third field effect transistor, the low-end output pin of the second driving chip is connected with the grid input end of the fourth field effect transistor, and the public end pin of the second driving chip is connected with the source electrode of the fourth field effect transistor. According to the utility model, the first driving chip and the second driving chip respectively control two field effect transistors in the upper bridge arm and the lower bridge arm.
The technical scheme of the utility model is further limited, the rectification control module comprises a first synchronous rectification control chip and a second synchronous rectification control chip, a drain voltage detection end of the first synchronous rectification control chip is connected with a drain of a fourth field effect transistor, a source voltage detection end of the first synchronous rectification control chip is connected with a source of the fourth field effect transistor, a drain voltage detection end of the second synchronous rectification control chip is connected with a drain of a third field effect transistor, and a source voltage detection end of the second synchronous rectification control chip is connected with a source of the third field effect transistor. The first synchronous rectification control chip detects the voltage of a source electrode and a drain electrode of a fourth field effect transistor in the lower bridge arm, and the second synchronous rectification control chip detects the voltage of the source electrode and the drain electrode of a third field effect transistor in the lower bridge arm.
The technical scheme of the utility model is further limited, the first synchronous rectification control chip and the second synchronous rectification control chip are both in IR11672 type, and the rectification control module further comprises a fourth capacitor, an eighth capacitor, an eleventh resistor, a thirteenth resistor, a third capacitor, a seventh capacitor, a ninth resistor and a tenth resistor; the enabling end of the first synchronous rectification control chip is connected with the fourth capacitor in series and then grounded, the minimum on-time adjusting end of the first synchronous rectification control chip is connected with the eleventh resistor in series and then grounded, the first end of the eighth capacitor is connected with the power supply end of the first synchronous rectification control chip, the second end of the eighth capacitor is grounded, the common end of the first synchronous rectification control chip is grounded, and the gate driving output end of the first synchronous rectification control chip is connected with the thirteenth resistor in series and then serves as the output end of the first synchronous rectification control chip; the enabling end of the second synchronous rectification control chip is connected with the third capacitor in series and then grounded, the minimum on-time adjusting end of the second synchronous rectification control chip is connected with the ninth resistor in series and then grounded, the first end of the seventh capacitor is connected with the power supply end of the second synchronous rectification control chip, the second end of the seventh capacitor is grounded, the common end of the second synchronous rectification control chip is grounded, and the gate driving output end of the second synchronous rectification control chip is connected with the tenth resistor in series and then serves as the output end of the second synchronous rectification control chip. The first synchronous rectification control chip and the second synchronous rectification control chip both adopt IR11672, so that the control mode is simple, the rectification control efficiency can be improved, the peripheral circuit is simple, and the reliability is good.
In a further limitation of the technical solution of the present invention, the logic low-side input pin of the first driver chip and the logic high-side input pin of the second driver chip are both connected to the output terminal of the first synchronous rectification control chip, and the logic high-side input pin of the first driver chip and the logic low-side input pin of the second driver chip are both connected to the output terminal of the second synchronous rectification control chip. In the utility model, the output ends of the first synchronous rectification control chip and the second driving chip output driving signals to the first driving chip and the second driving chip, so that the four field effect transistors are respectively controlled to be switched on and switched off by the first driving chip and the second driving chip in a receiving state to form a corresponding rectification loop.
The technical scheme of the utility model is further limited, the inversion control module comprises a coil current sampling unit and an inversion control chip, the coil current sampling unit is connected with the inversion control chip, and the inversion control chip is respectively connected with the first driving chip and the second driving chip; the coil current sampling unit comprises an operational amplifier, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eighth resistor, a sixteenth capacitor, a twenty-fifth capacitor, a twenty-seventh capacitor and a twenty-eighth capacitor; the first end of the coil is connected with the anti-phase input end of the operational amplifier after being connected with the twenty-fifth capacitor and the twenty-sixth resistor in series, the first end of the sixty-eighth resistor is connected with the first end of the coil, the second end of the sixty-eighth resistor is connected with the second end of the coil and grounded, the twenty-eighth resistor and the twenty-ninth resistor are connected with the ground after being connected with each other in series, a node of the twenty-eighth resistor and the twenty-ninth resistor is connected with the non-phase input end of the operational amplifier, the twenty-seventh resistor is connected between the anti-phase input end and the output end of the operational amplifier, the first end of the twenty-seventh capacitor is connected with the output end of the operational amplifier, the second end of the twenty-seventh capacitor is grounded, the output end of the operational amplifier is connected with the thirty resistor in series and then serves as the output end of the coil current sampling unit, the first end of the twenty-eighth capacitor is connected with the output end of the coil current sampling unit, and the second end of the twenty-eighth capacitor is grounded. According to the utility model, a coil current sampling unit inputs a collected coil current signal into an inversion control chip, the inversion control chip performs frequency conversion regulation control according to the received coil current signal so as to generate a driving signal, and the driving signal is transmitted to a first driving chip and a second driving chip, so that in a transmitting state, the first driving chip and the second driving chip respectively control the on and off of four field effect transistors, and a corresponding inversion loop is formed; meanwhile, the coil current is introduced into the inversion control chip, so that the running stability of the inversion control chip can be improved, and the resonance peak value of the resonance module can be correspondingly reduced.
The technical scheme of the utility model is further limited, and the inversion control chip is a DSP chip. The utility model adopts the DSP chip, has the digital signal processing capability and the embedded control function, can realize the inversion control function and has low cost.
In a further limitation of the technical solution of the present invention, the models of the first driving chip and the second driving chip are both IR2110, and the driving module further includes a tenth capacitor, a twelfth capacitor, a fourteenth capacitor, a fifth diode, a sixth diode, an eleventh capacitor, a thirteenth capacitor, and a fifteenth capacitor; the first end of the tenth capacitor is connected with a logic power supply voltage pin of the first driving chip, the second end of the tenth capacitor is grounded, the first end of the fourteenth capacitor is connected with a low-end fixed power supply voltage pin of the first driving chip, the second end of the fourteenth capacitor is connected with a common end pin of the first driving chip and grounded, the first end of the twelfth capacitor is connected with a high-end floating power supply voltage pin of the first driving chip, the second end of the twelfth capacitor is connected with a high-end floating power supply offset voltage pin of the first driving chip, the anode of the fifth diode is connected with the low-end fixed power supply voltage pin of the first driving chip, the cathode of the fifth diode is connected with the high-end floating power supply voltage pin of the first driving chip, and a logic circuit ground potential end pin of the first driving chip is grounded; the first end of the eleventh capacitor is connected with a logic power supply voltage pin of the second driving chip, the second end of the eleventh capacitor is grounded, the low end of the fifteenth capacitor is connected with a low-end fixed power supply voltage pin of the second driving chip, the second end of the fifteenth capacitor is connected with a common end pin of the second driving chip and grounded, the first end of the thirteenth capacitor is connected with a high-end floating power supply voltage pin of the second driving chip, the second end of the thirteenth capacitor is connected with a high-end floating power supply offset voltage pin of the second driving chip, the anode of the sixth diode is connected with the low-end fixed power supply voltage pin of the second driving chip, the cathode of the sixth diode is connected with the high-end floating power supply voltage pin of the second driving chip, and a logic circuit ground potential end pin of the second driving chip is grounded. The first driving chip and the second driving chip both adopt IR2110, have the advantages of optical coupling isolation and electromagnetic isolation, and are good in driving effect.
In a further limitation of the technical solution of the present invention, the filtering module is composed of a first capacitor, the first capacitor is an electrolytic capacitor, and the first capacitor is connected in parallel between the positive output end and the negative output end of the rectification inverter module.
The utility model has the beneficial effects that: 1) the utility model can realize bidirectional wireless charging.
2) When the utility model is implemented, for example, applied to a submersible vehicle, the storage battery of the submersible vehicle can be connected behind the filtering module, so that in a receiving state, the alternating current electric energy provided by external wireless charging equipment is converted into the direct current electric energy to charge the storage battery of the submersible vehicle, and in a transmitting state, the direct current electric energy provided by the storage battery of the submersible vehicle is converted into the alternating current electric energy to wirelessly charge other equipment.
Drawings
Fig. 1 is a schematic diagram of a resonance module, a rectification inverter module, a filtering module and a rectification control module according to the present invention.
Fig. 2 is a schematic diagram of a coil current sampling unit according to the present invention.
FIG. 3 is a diagram of a first driving chip according to the present invention.
FIG. 4 is a diagram of a second driving chip according to the present invention.
Detailed Description
The utility model will be described in further detail with reference to the following figures and specific embodiments.
A transceiver circuit for bidirectional wireless charging comprises a resonance module, a rectification inversion module, a filtering module, a rectification control module, an inversion control module and a driving module, wherein the resonance module, the rectification inversion module and the filtering module are sequentially connected; the receiving and transmitting circuit has two working states of receiving and transmitting, when the receiving circuit works in the receiving state, the resonance module is used for receiving alternating electric energy, the rectification inversion module is used for converting the alternating electric energy into direct current electric energy, and the filtering module is used for filtering the direct current electric energy; when the wireless power transmission device works in a transmitting state, the filtering module is used for filtering received direct current electric energy, the rectifying and inverting module is used for converting the direct current electric energy into alternating electric energy, and the resonance module is used for transmitting the alternating electric energy; the rectification inversion module is a full-bridge circuit formed by four field effect transistors, wherein two field effect transistors form an upper bridge arm of the full-bridge circuit, the other two field effect transistors form a lower bridge arm of the full-bridge circuit, when the transceiver circuit works in a receiving state, the rectification control module detects voltages of source electrodes and drain electrodes of the two field effect transistors of the lower bridge arm and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the four field effect transistors to be switched on and off according to the received driving signal; the resonance module comprises a coil L and a second capacitor which are connected in series, when the transceiver circuit works in a transmitting state, the inverter control circuit detects the current of the coil L and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the on and off of the four field effect transistors according to the received driving signal.
As shown in fig. 1, in this embodiment, the four field effect transistors are a first field effect transistor V1, a second field effect transistor V2, a third field effect transistor V3, and a fourth field effect transistor V4, the four field effect transistors are all N-type insulated gate bipolar transistors with damping diodes, the first field effect transistor V1 and the second field effect transistor V2 form an upper arm, and the third field effect transistor V3 and the fourth field effect transistor V4 form a lower arm; a third resistor R3 and a first diode D1 which are connected in parallel are connected between the grid and the source of the first field effect tube V1, the grid of the first field effect tube V1 is connected in series with a first resistor R1, a fourth resistor R4 and a second diode D2 which are connected in parallel are connected between the grid and the source of the second field effect tube V2, the grid of the second field effect tube V2 is connected in series with a second resistor R2, a seventh resistor R7 and a third diode D3 which are connected in parallel are connected between the grid and the source of the third field effect tube V3, a fifth resistor R5 is connected in series with the grid of the third field effect tube V3, an eighth resistor R8 and a fourth diode D4 which are connected in parallel are connected between the grid and the source of the fourth field effect tube V4, and a sixth resistor R6 is connected in series with the grid of the fourth field effect tube V4; the drain electrode of the fourth field effect tube V4 is connected with the source electrode of the second field effect tube V2 to be used as the first input end of the bidirectional synchronous rectification circuit, the drain electrode of the second field effect tube V2 is connected with the drain electrode of the first field effect tube V1 to be used as the positive output end of the bidirectional synchronous rectification circuit, the source electrode of the first field effect tube V1 is connected with the drain electrode of the third field effect tube V3 to be used as the second input end of the bidirectional synchronous rectification circuit, and the source electrode of the third field effect tube V3 is connected with the source electrode of the fourth field effect tube V4 to be used as the negative output end of the bidirectional synchronous rectification circuit; the first end of the coil L is connected with a second capacitor C2 in series and then is connected with the first input end of the synchronous rectification circuit, and the second end of the coil L is connected with the second input end of the synchronous rectification circuit; the filtering module is composed of a first capacitor C1, the first capacitor C1 is an electrolytic capacitor, and the first capacitor C1 is connected in parallel between the positive output end and the negative output end of the rectifying and inverting module.
B in fig. 1 represents a storage battery of the device in practical implementation, FUSE1 is a FUSE, and the FUSE can be connected in series in a storage battery loop for safety in practical implementation, which is not the utility model point of the embodiment and is a conventional means.
As shown in fig. 1, in this embodiment, the types of the first synchronous rectification control chip and the second synchronous rectification control chip are IR11672, the rectification control module includes the first synchronous rectification control chip and the second synchronous rectification control chip, the drain voltage detection terminal VD of the first synchronous rectification control chip is connected to the drain of the fourth fet V4, the source voltage detection terminal VS of the first synchronous rectification control chip is connected to the source of the fourth fet V4, the drain voltage detection terminal VD of the second synchronous rectification control chip is connected to the drain of the third fet V3, and the source voltage detection terminal VS of the second synchronous rectification control chip is connected to the source of the third fet V3. The rectification control module further comprises a fourth capacitor C4, an eighth capacitor C8, an eleventh resistor R11, a thirteenth resistor R13, a third capacitor C3, a seventh capacitor C7, a ninth resistor R9 and a tenth resistor R10; the enable end EN of the first synchronous rectification control chip is connected in series with the fourth capacitor C4 and then grounded, the minimum on-time adjusting end MOT of the first synchronous rectification control chip is connected in series with the eleventh resistor R11 and then grounded, the first end of the eighth capacitor C8 is connected with the power supply end VCC of the first synchronous rectification control chip, the second end of the eighth capacitor C8 is grounded, the common end GND of the first synchronous rectification control chip is grounded, and the GATE drive output end GATE of the first synchronous rectification control chip is connected in series with the thirteenth resistor R13 and then serves as the output end of the first synchronous rectification control chip; the enabling end EN of the second synchronous rectification control chip is connected with the third capacitor C3 in series and then grounded, the minimum on-time adjusting end MOT of the second synchronous rectification control chip is connected with the ninth resistor R9 in series and then grounded, the first end of the seventh capacitor C7 is connected with the power supply end VCC of the second synchronous rectification control chip, the second end of the seventh capacitor C7 is grounded, the common end GND of the second synchronous rectification control chip is grounded, and the GATE drive output end GATE of the second synchronous rectification control chip is connected with the tenth resistor R10 in series and then serves as the output end of the second synchronous rectification control chip.
In this embodiment, the inversion control module includes a coil current sampling unit and an inversion control chip, the coil current sampling unit is connected to the inversion control chip, the inversion control chip is connected to the first driving chip and the second driving chip, the inversion control chip in this embodiment is a DSP chip, and the TMS320F28035 may be used in specific implementation; as shown in fig. 2, the coil current sampling unit includes an operational amplifier, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eighth resistor, a sixty-eighth resistor, a twenty-fifth capacitor, a twenty-seventh capacitor, and a twenty-eighth capacitor; the first end of the coil L is connected with the inverting input end of the operational amplifier after being connected with a twenty-fifth capacitor and a twenty-sixth resistor in series, the first end of the sixteenth resistor is connected with the first end of the coil L, the second end of the sixteenth resistor is connected with the second end of the coil L and grounded, the twenty-eighth resistor and the twenty-ninth resistor are connected in series and grounded, the node of the twenty-eighth resistor and the twenty-ninth resistor is connected with the non-inverting input end of the operational amplifier, the twenty-seventh resistor is connected between the inverting input end and the output end of the operational amplifier, the first end of the twenty-seventh capacitor is connected with the output end of the operational amplifier, the second end of the twenty-seventh capacitor is grounded, the output end of the operational amplifier is connected with the thirty resistor in series and serves as the output end of the coil Current sampling unit, a coil Current signal is output, and the first end of the twenty-eighth capacitor is connected with the output end of the coil Current sampling unit, and the second end of the twenty-eighth capacitor is grounded. In this embodiment, OPA356 is used as the operational amplifier.
As shown in fig. 1, the driving module includes a first driving chip and a second driving chip, both the first driving chip and the second driving chip are MOS field effect transistor driving chips, a high-side output pin of the first driving chip is connected to a gate input terminal of a first field effect transistor, a high-side floating power offset voltage pin of the first driving chip is connected to a source of the first field effect transistor, a low-side output pin of the first driving chip is connected to a gate input terminal of a second field effect transistor, and a common terminal pin of the first driving chip is connected to a source of the second field effect transistor; the high-end output pin of the second driving chip is connected with the grid input end of the third field effect transistor, the high-end floating power supply offset voltage pin of the second driving chip is connected with the source electrode of the third field effect transistor, the low-end output pin of the second driving chip is connected with the grid input end of the fourth field effect transistor, and the public end pin of the second driving chip is connected with the source electrode of the fourth field effect transistor.
As shown in fig. 3 and 4, the logic low-side input pin of the first driver chip and the logic high-side input pin of the second driver chip are both connected to the output end of the first synchronous rectification control chip, and the logic high-side input pin of the first driver chip and the logic low-side input pin of the second driver chip are both connected to the output end of the second synchronous rectification control chip. In this embodiment, the driving signal output by the output end of the first synchronous rectification control chip is GAT-PWM-1, and the driving signal output by the output end of the second synchronous rectification control chip is GAT-PWM-2; the inversion control chip is a DSP chip, and the DSP chip performs frequency conversion regulation control according to the received coil Current signal Current, so that driving signals PWM1, PWM2, PWM3 and PWM4 are generated and transmitted to the first driving chip and the second driving chip; the first driving chip and the second driving chip effectively control the working time sequence of the four field effect transistors according to the driving signals, corresponding rectification and inversion loops are formed in time, the rectification and inversion functions are realized, and therefore bidirectional wireless charging is realized. The models of the first driving chip and the second driving chip are both IR2110, and the driving module further comprises a tenth capacitor C10, a twelfth capacitor C12, a fourteenth capacitor C14, a fifth diode D5, a sixth diode D6, an eleventh capacitor C11, a thirteenth capacitor C13 and a fifteenth capacitor C15; a first end of the tenth capacitor C10 is connected to a logic power supply voltage pin VDD of the first driving chip, a second end of the tenth capacitor C10 is grounded, a first end of the fourteenth capacitor C14 is connected to a low-end fixed power supply voltage pin VCC of the first driving chip, a second end of the fourteenth capacitor C14 is connected to a common end pin COM of the first driving chip and grounded, a first end of the twelfth capacitor C12 is connected to a high-end floating power supply voltage pin VB of the first driving chip, a second end of the twelfth capacitor C12 is connected to a high-end floating power supply offset voltage VS pin of the first driving chip, an anode of the fifth diode D5 is connected to the low-end fixed power supply voltage VCC of the first driving chip, a cathode of the fifth diode D5 is connected to the high-end floating power supply voltage pin VB of the first driving chip, and a logic circuit ground potential pin VSs of the first driving chip is grounded; a first end of the eleventh capacitor C11 is connected to a logic power supply voltage pin VDD of the second driver chip, a second end of the eleventh capacitor C11 is grounded, a low end of the fifteenth capacitor C15 is connected to a low-end fixed power supply voltage VCC pin of the second driver chip, a second end of the fifteenth capacitor C15 is connected to a common end pin COM of the second driver chip and grounded, a first end of the thirteenth capacitor C13 is connected to a high-end floating power supply voltage pin VB of the second driver chip, a second end of the thirteenth capacitor C13 is connected to a high-end floating power supply offset voltage pin VS of the second driver chip, an anode of the sixth diode D6 is connected to the low-end fixed power supply voltage VCC of the second driver chip, a cathode of the sixth diode D6 is connected to the high-end floating power supply voltage pin VB of the second driver chip, and a ground end VSs pin of a logic circuit of the second driver chip is grounded.
Claims (10)
1. A transceiver circuit for bidirectional wireless charging, characterized by: the rectifier and inverter circuit comprises a resonance module, a rectifier and inverter module, a filtering module, a rectifier control module, an inverter control module and a driving module, wherein the resonance module, the rectifier and inverter module and the filtering module are sequentially connected;
the receiving and transmitting circuit has two working states of receiving and transmitting, when the receiving circuit works in the receiving state, the resonance module is used for receiving alternating electric energy, the rectification inversion module is used for converting the alternating electric energy into direct current electric energy, and the filtering module is used for filtering the direct current electric energy; when the wireless power transmission device works in a transmitting state, the filtering module is used for filtering received direct current electric energy, the rectifying and inverting module is used for converting the direct current electric energy into alternating electric energy, and the resonance module is used for transmitting the alternating electric energy;
the rectification inversion module is a full-bridge circuit formed by four field effect transistors, wherein two field effect transistors form an upper bridge arm of the full-bridge circuit, the other two field effect transistors form a lower bridge arm of the full-bridge circuit, when the transceiver circuit works in a receiving state, the rectification control module detects voltages of source electrodes and drain electrodes of the two field effect transistors of the lower bridge arm and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the four field effect transistors to be switched on and off according to the received driving signal;
the resonance module comprises a coil and a second capacitor which are connected in series, when the transceiver circuit works in a transmitting state, the inverter control circuit detects the current of the coil and outputs a driving signal to the driving module according to a detection result, and the driving module respectively controls the on and off of the four field effect transistors according to the received driving signal.
2. The transceiver circuit of claim 1, wherein: the four field effect transistors are respectively a first field effect transistor, a second field effect transistor, a third field effect transistor and a fourth field effect transistor, the four field effect transistors are N-type insulated gate bipolar transistors with damping diodes, the first field effect transistor and the second field effect transistor form an upper bridge arm, and the third field effect transistor and the fourth field effect transistor form a lower bridge arm; resistors and diodes which are connected in parallel are connected between the grid electrodes and the source electrodes of the four field effect transistors, and the diodes are bidirectional transient suppression diodes; the grid electrodes of the four field effect tubes are connected in series with resistors and then serve as the grid electrode input end of each field effect tube;
the drain electrode of the fourth field effect tube is connected with the source electrode of the second field effect tube to serve as the first input end of the bidirectional synchronous rectification circuit, the drain electrode of the second field effect tube is connected with the drain electrode of the first field effect tube to serve as the positive output end of the bidirectional synchronous rectification circuit, the source electrode of the first field effect tube is connected with the drain electrode of the third field effect tube to serve as the second input end of the bidirectional synchronous rectification circuit, and the source electrode of the third field effect tube is connected with the source electrode of the fourth field effect tube to serve as the negative output end of the bidirectional synchronous rectification circuit;
and the first end of the coil is connected with the first input end of the synchronous rectification circuit after being connected with the second capacitor in series, and the second end of the coil is connected with the second input end of the synchronous rectification circuit.
3. The transceiver circuit of claim 2, wherein: the driving module comprises a first driving chip and a second driving chip, the first driving chip and the second driving chip are both MOS field effect transistor driving chips, a high-end output pin of the first driving chip is connected with a grid input end of a first field effect transistor, a high-end floating power offset voltage pin of the first driving chip is connected with a source electrode of the first field effect transistor, a low-end output pin of the first driving chip is connected with a grid input end of a second field effect transistor, and a common end pin of the first driving chip is connected with a source electrode of the second field effect transistor; the high-end output pin of the second driving chip is connected with the grid input end of the third field effect transistor, the high-end floating power supply offset voltage pin of the second driving chip is connected with the source electrode of the third field effect transistor, the low-end output pin of the second driving chip is connected with the grid input end of the fourth field effect transistor, and the public end pin of the second driving chip is connected with the source electrode of the fourth field effect transistor.
4. A transceiver circuit for bidirectional wireless charging according to claim 3, wherein: the rectification control module comprises a first synchronous rectification control chip and a second synchronous rectification control chip, a drain electrode voltage detection end of the first synchronous rectification control chip is connected with a drain electrode of the fourth field effect transistor, a source electrode voltage detection end of the first synchronous rectification control chip is connected with a source electrode of the fourth field effect transistor, a drain electrode voltage detection end of the second synchronous rectification control chip is connected with a drain electrode of the third field effect transistor, and a source electrode voltage detection end of the second synchronous rectification control chip is connected with a source electrode of the third field effect transistor.
5. The transceiver circuit of claim 4, wherein: the types of the first synchronous rectification control chip and the second synchronous rectification control chip are both IR11672, and the rectification control module further comprises a fourth capacitor, an eighth capacitor, an eleventh resistor, a thirteenth resistor, a third capacitor, a seventh capacitor, a ninth resistor and a tenth resistor;
the enabling end of the first synchronous rectification control chip is connected with the fourth capacitor in series and then grounded, the minimum on-time adjusting end of the first synchronous rectification control chip is connected with the eleventh resistor in series and then grounded, the first end of the eighth capacitor is connected with the power supply end of the first synchronous rectification control chip, the second end of the eighth capacitor is grounded, the common end of the first synchronous rectification control chip is grounded, and the gate driving output end of the first synchronous rectification control chip is connected with the thirteenth resistor in series and then serves as the output end of the first synchronous rectification control chip;
the enabling end of the second synchronous rectification control chip is connected with the third capacitor in series and then grounded, the minimum on-time adjusting end of the second synchronous rectification control chip is connected with the ninth resistor in series and then grounded, the first end of the seventh capacitor is connected with the power supply end of the second synchronous rectification control chip, the second end of the seventh capacitor is grounded, the common end of the second synchronous rectification control chip is grounded, and the gate driving output end of the second synchronous rectification control chip is connected with the tenth resistor in series and then serves as the output end of the second synchronous rectification control chip.
6. The transceiver circuit of claim 5, wherein: and the logic high-end input pin of the first driving chip and the logic high-end input pin of the second driving chip are both connected with the output end of the first synchronous rectification control chip, and the logic high-end input pin of the first driving chip and the logic low-end input pin of the second driving chip are both connected with the output end of the second synchronous rectification control chip.
7. A transceiver circuit for bidirectional wireless charging according to claim 3, wherein: the inversion control module comprises a coil current sampling unit and an inversion control chip, the coil current sampling unit is connected with the inversion control chip, and the inversion control chip is respectively connected with the first driving chip and the second driving chip;
the coil current sampling unit comprises an operational amplifier, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eighth resistor, a sixteenth capacitor, a twenty-fifth capacitor, a twenty-seventh capacitor and a twenty-eighth capacitor; the first end of the coil is connected with the anti-phase input end of the operational amplifier after being connected with the twenty-fifth capacitor and the twenty-sixth resistor in series, the first end of the sixty-eighth resistor is connected with the first end of the coil, the second end of the sixty-eighth resistor is connected with the second end of the coil and grounded, the twenty-eighth resistor and the twenty-ninth resistor are connected with the ground after being connected with each other in series, a node of the twenty-eighth resistor and the twenty-ninth resistor is connected with the non-phase input end of the operational amplifier, the twenty-seventh resistor is connected between the anti-phase input end and the output end of the operational amplifier, the first end of the twenty-seventh capacitor is connected with the output end of the operational amplifier, the second end of the twenty-seventh capacitor is grounded, the output end of the operational amplifier is connected with the thirty resistor in series and then serves as the output end of the coil current sampling unit, the first end of the twenty-eighth capacitor is connected with the output end of the coil current sampling unit, and the second end of the twenty-eighth capacitor is grounded.
8. The transceiver circuit of claim 7, wherein: the inversion control chip is a DSP chip.
9. A transceiver circuit for bidirectional wireless charging according to any one of claims 3 to 8, wherein: the types of the first driving chip and the second driving chip are both IR2110, and the driving module further comprises a tenth capacitor, a twelfth capacitor, a fourteenth capacitor, a fifth diode, a sixth diode, an eleventh capacitor, a thirteenth capacitor and a fifteenth capacitor;
the first end of the tenth capacitor is connected with a logic power supply voltage pin of the first driving chip, the second end of the tenth capacitor is grounded, the first end of the fourteenth capacitor is connected with a low-end fixed power supply voltage pin of the first driving chip, the second end of the fourteenth capacitor is connected with a common end pin of the first driving chip and grounded, the first end of the twelfth capacitor is connected with a high-end floating power supply voltage pin of the first driving chip, the second end of the twelfth capacitor is connected with a high-end floating power supply offset voltage pin of the first driving chip, the anode of the fifth diode is connected with the low-end fixed power supply voltage pin of the first driving chip, the cathode of the fifth diode is connected with the high-end floating power supply voltage pin of the first driving chip, and a logic circuit ground potential end pin of the first driving chip is grounded;
the first end of the eleventh capacitor is connected with a logic power supply voltage pin of the second driving chip, the second end of the eleventh capacitor is grounded, the low end of the fifteenth capacitor is connected with a low-end fixed power supply voltage pin of the second driving chip, the second end of the fifteenth capacitor is connected with a common end pin of the second driving chip and grounded, the first end of the thirteenth capacitor is connected with a high-end floating power supply voltage pin of the second driving chip, the second end of the thirteenth capacitor is connected with a high-end floating power supply offset voltage pin of the second driving chip, the anode of the sixth diode is connected with the low-end fixed power supply voltage pin of the second driving chip, the cathode of the sixth diode is connected with the high-end floating power supply voltage pin of the second driving chip, and a logic circuit ground potential end pin of the second driving chip is grounded.
10. The transceiver circuit of claim 2, wherein: the filtering module is composed of a first capacitor, the first capacitor is an electrolytic capacitor, and the first capacitor is connected in parallel between the positive output end and the negative output end of the rectification inversion module.
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| CN202122928756.0U CN216564661U (en) | 2021-11-26 | 2021-11-26 | A transceiver circuit for two-way wireless charging |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115296689A (en) * | 2022-08-08 | 2022-11-04 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, serial circuit chip, electronic equipment and vehicle |
| CN117914344A (en) * | 2024-01-22 | 2024-04-19 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
| CN118264135A (en) * | 2024-04-24 | 2024-06-28 | 四川杰莱美科技有限公司 | Rectifying circuit based on circuit signal control and electronic device |
| WO2024193075A1 (en) * | 2023-03-21 | 2024-09-26 | 荣耀终端有限公司 | Wireless charging circuit, wireless charging chip, system and electronic device |
-
2021
- 2021-11-26 CN CN202122928756.0U patent/CN216564661U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115296689A (en) * | 2022-08-08 | 2022-11-04 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, serial circuit chip, electronic equipment and vehicle |
| CN115296689B (en) * | 2022-08-08 | 2023-11-03 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, serial circuit chip, electronic equipment and vehicle |
| WO2024193075A1 (en) * | 2023-03-21 | 2024-09-26 | 荣耀终端有限公司 | Wireless charging circuit, wireless charging chip, system and electronic device |
| CN117914344A (en) * | 2024-01-22 | 2024-04-19 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
| CN118264135A (en) * | 2024-04-24 | 2024-06-28 | 四川杰莱美科技有限公司 | Rectifying circuit based on circuit signal control and electronic device |
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