CN215376139U

CN215376139U - Efficient data acquisition system based on ARM and FPGA

Info

Publication number: CN215376139U
Application number: CN202121857863.2U
Authority: CN
Inventors: 詹小静; 黄志鹏; 周鹤
Original assignee: Tan Kah Kee Innovation Laboratory
Current assignee: Tan Kah Kee Innovation Laboratory
Priority date: 2021-08-10
Filing date: 2021-08-10
Publication date: 2021-12-31
Anticipated expiration: 2031-08-10

Abstract

The utility model relates to an efficient data acquisition system based on an ARM and an FPGA, which comprises an ARM chip and an FPGA chip, wherein the ARM chip and the FPGA chip are communicated through a data bus; the FPGA chip is integrated with an FSMC module and a register management module, the register management module comprises an address buffer, the address buffer is used for storing the address signal, and the FSMC module outputs a collecting signal of a corresponding address according to the address signal; the ARM chip is used for sending a control signal containing the address signal to the FPGA chip and receiving and outputting the acquisition signal output by the FPGA chip. The utility model designs the control information interaction into a register read-write access mode, namely, the ARM sends a configuration or control instruction to the FPGA and writes the corresponding register through the SPI.

Description

Efficient data acquisition system based on ARM and FPGA

Technical Field

The utility model relates to the field of data acquisition systems, in particular to an efficient data acquisition system based on ARM and FPGA.

Background

As an important means for data acquisition, the data acquisition technology is widely applied in various fields, and in particular, in various control systems, the data acquisition, transmission and processing are almost involved. The data acquisition system taking the ARM as the core can process complex protocols and data management, but due to the characteristic of serial execution, the real-time performance and the stability of data sampling are limited. The FPGA-based data acquisition system can realize stable and quick sampling to the maximum extent by benefiting from the parallel processing characteristic of the FPGA, has prominent advantages in multi-signal and multi-channel data acquisition, and cannot realize complex and flexible data processing and interaction functions. Therefore, data acquisition schemes based on the ARM and the FPGA gradually become the mainstream trend, in such systems, the FPGA is generally only responsible for data acquisition, the MCU is responsible for data processing and communication interaction, and the two cooperate through the FSMC interface. Besides the huge amount of original sampling data, the interactive information between the ARM and the FPGA also has some control configuration information, so that the interactive protocol is generally complex, and the parallel and high-speed processing capability of the FPGA is restricted to a certain extent.

Aiming at the problems in the prior art, the utility model aims to design an efficient data acquisition system based on ARM and FPGA.

SUMMERY OF THE UTILITY MODEL

Aiming at the problems in the prior art, the utility model provides an efficient data acquisition system based on ARM and FPGA, which can effectively solve the problems in the prior art.

The technical scheme of the utility model is as follows:

the efficient data acquisition system based on the ARM and the FPGA comprises an ARM chip and an FPGA chip, wherein the ARM chip and the FPGA chip are communicated through a data bus;

the FPGA chip is integrated with an FSMC module and a register management module, the register management module comprises an address buffer, the address buffer is used for storing the address signal, and the FSMC module outputs a collecting signal of a corresponding address according to the address signal;

the ARM chip is used for sending a control signal containing the address signal to the FPGA chip and receiving and outputting the acquisition signal output by the FPGA chip.

Furthermore, the FPGA chip is integrated with a first SPI driving module, the ARM chip is integrated with a second SPI driving module, the first SPI driving module is connected with the second SPI driving module, and the FPGA chip and the ARM chip communicate through the first SPI driving module and the second SPI driving module.

Further, the second SPI driving module is configured to send the control signal to the first SPI driving module.

Furthermore, the FSMC module comprises a multi-path selection unit, and the multi-path selection unit is connected with a plurality of acquisition cards.

Furthermore, the FPGA chip is integrated with a first FSMC driving module, the first FSMC driving module reads an address signal of the address buffer and sends the address signal to the multi-path selection unit, and the multi-path selection unit is switched to a corresponding acquisition card according to the address signal.

Furthermore, the ARM chip is integrated with a second FSMC driving module, the first FSMC driving module is connected with the second FSMC driving module, the FPGA chip outputs the acquisition signals of the corresponding acquisition card through the first FSMC driving module, and the ARM chip receives the acquisition signals through the second FSMC driving module and outputs the acquisition signals through the corresponding external interface.

Furthermore, the FSMC module comprises a plurality of acquisition card control units, a plurality of data cache units and a multi-path selection unit, wherein the acquisition card control units are respectively connected to the acquisition cards, each acquisition card control unit is connected with one data cache unit, and all the data cache units are connected to the multi-path selection unit.

Further, the data buffer unit is a first-in first-out data buffer unit.

The utility model has the advantages that:

the FPGA chip is integrated with an FSMC module and a register management module, the register management module comprises an address buffer, the address buffer is used for storing the address signal, and the FSMC module outputs a collecting signal of a corresponding address according to the address signal; the FSMC module is only responsible for the transmission of a large amount of sampling data and only carries out the one-way transmission from the FPGA chip to the ARM chip, thereby simplifying the interactive protocol between the ARM and the FPGA. The FPGA chip only needs 1 read control signal line and 16 data lines from the ARM chip, IO resource consumption is not increased, control information is interactively designed into a register read-write access mode, namely, the ARM chip sends configuration or control instructions to the FPGA chip and writes corresponding registers through the SPI, and transmission efficiency is greatly improved.

The two chips of the utility model are connected with the FSMC driving module through the SPI, the FSMC driving module is only responsible for unidirectionally transmitting a large amount of sampling data with higher real-time performance, and the SPI is responsible for the interaction of all light-weight data such as control, configuration and the like.

The utility model introduces a dual communication mode of FSMC and SPI to separately transmit the sampling data and the control information. The FSMC in the system is only used for transmitting the collected data, and the transmission of the collected data is unidirectional, so that the FSMC only works in a reading mode.

Drawings

FIG. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a read timing diagram of the FSMC module.

FIG. 3 is a write timing diagram for the FSMC module.

FIG. 4 shows the SPI register read timing of the ARM chip.

FIG. 5 shows the SPI register write timing of the ARM chip.

Detailed Description

To facilitate understanding of those skilled in the art, the structure of the present invention will now be described in further detail by way of examples in conjunction with the accompanying drawings:

example one

Referring to fig. 1, the efficient data acquisition system based on ARM and FPGA comprises an ARM chip and an FPGA chip,

the ARM chip and the FPGA chip are communicated through a data bus; the embodiment only needs data bus communication and does not need address bus communication, and a large number of connecting wires are saved between chips.

The specific working mode is that the FSMC module is only responsible for the transmission of a large amount of sampling data, the FPGA chip extracts address signals from the address buffer at regular time, the FSMC module outputs, switches and connects the FSMC module to a collecting card corresponding to the address signals, and outputs the collecting signals. The ARM chip is used for sending control signals to the FPGA chip, for example, each acquisition control unit is provided with a group of registers and used for realizing the control of the ARM control module on the parameter configuration and the working state of the acquisition module, the control signals comprise address signals and the like, and after the FPGA chip receives the control signals, the address signals are stored in the address buffer and are read by the FPGA chip and used for selectively switching the corresponding acquisition card. In the whole process, the calculation of the FPGA chip is completely concentrated on reading the acquisition signals of the acquisition card, an address bus is not needed to receive the address signals, the bandwidth is utilized to the maximum extent, and the processing mode of the acquisition system is simplified. Because the FSMC module in the acquisition system is only used for transmitting the acquired data, and the transmission of the acquired data is unidirectional, the FSMC module only works in a read mode without writing a control signal NEW, and the design of a register address is introduced, and the interior of the FPGA automatically sends the corresponding sampled data to an FSMC data wire according to the value of a preset FSMC address register, namely for ARM, the FPGA is equivalent to a 16-bit ROM with only one address, so an address line A and a byte selection channel NBL are not needed; the FPGA is only one, and the chip selection signal NEx has no meaning; in summary, the hardware connection of the FSMC interface only requires 1 read control signal NOE and a 16-bit data bus.

Furthermore, the FPGA chip is integrated with a first SPI driving module, the ARM chip is integrated with a second SPI driving module, the first SPI driving module is connected with the second SPI driving module, and the FPGA chip and the ARM chip communicate through the first SPI driving module and the second SPI driving module. And the second SPI driving module is used for sending the control signal to the first SPI driving module. In this embodiment, the two chips are physically connected through the SPI and the FSMC driver module, the FSMC module is only responsible for unidirectionally transmitting a large amount of sampling data with relatively high real-time performance, and the SPI is responsible for interaction of all light-weight data such as control and configuration. The two chips are interacted through the SPI driving module; the ARM chip comprises a data management unit, which is used for receiving data from the FSMC, classifying, converting, caching the data or sending the data out through an external interface for storage, visualization and the like according to the instruction of the protocol processing unit; the third communication unit is an external interface of the whole acquisition system, can be an SD card interface for storing sampling data according to application scenes, can also be a USB/network interface and the like, and is used for interfacing with a higher-level control core to realize data storage or visualization, a control protocol and the like; the protocol processing unit is a control core of the data acquisition system and is responsible for initialization, configuration, scheduling and the like of each part of the system, and when a higher-layer control core exists, the protocol processing unit can be used as a sub-core to complete the butt joint of the acquisition system and the control core.

Furthermore, the FSMC module comprises a multi-path selection unit, and the multi-path selection unit is connected with a plurality of acquisition cards. The multiplexer unit of this embodiment is a MUX, also called a data selector. The corresponding acquisition circuit can be switched on according to the address signal, so that the acquisition card is switched to output the acquisition signal of the acquisition card.

Furthermore, the FPGA chip is integrated with a first FSMC driving module, the first FSMC driving module reads an address signal of the address buffer and sends the address signal to the multi-path selection unit, and the multi-path selection unit is switched to a corresponding acquisition card according to the address signal. The FPGA chip outputs the acquisition signals of the corresponding acquisition card through the first FSMC driving module, and the ARM chip receives the acquisition signals through the second FSMC driving module and outputs the acquisition signals through the corresponding external interface.

Furthermore, the FSMC module comprises a plurality of acquisition card control units, a plurality of data cache units and a multi-path selection unit, wherein the acquisition card control units are respectively connected to the acquisition cards, each acquisition card control unit is connected with one data cache unit, and all the data cache units are connected to the multi-path selection unit. The FSMC module interfaces corresponding readout interfaces from several cache spaces to the FSMC module.

Further, the data buffer unit is a first-in first-out data buffer unit.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.

Claims

1. High-efficient data acquisition system based on ARM and FPGA, including ARM chip and FPGA chip, its characterized in that:

the ARM chip and the FPGA chip are communicated through a data bus;

the FPGA chip is integrated with an FSMC module and a register management module, the register management module comprises an address buffer, the address buffer is used for storing address signals, and the FSMC module outputs acquisition signals of corresponding addresses according to the address signals;

2. The ARM and FPGA-based high-efficiency data acquisition system according to claim 1, wherein: the FPGA chip is integrated with a first SPI driving module, the ARM chip is integrated with a second SPI driving module, the first SPI driving module is connected with the second SPI driving module, and the FPGA chip and the ARM chip are communicated through the first SPI driving module and the second SPI driving module.

3. The ARM and FPGA-based high-efficiency data acquisition system of claim 2, wherein: and the second SPI driving module is used for sending the control signal to the first SPI driving module.

4. The ARM and FPGA-based high-efficiency data acquisition system of claim 2, wherein: the FSMC module comprises a multi-path selection unit, and the multi-path selection unit is connected with a plurality of acquisition cards.

5. The ARM and FPGA based high efficiency data acquisition system of claim 4, wherein: the FPGA chip is integrated with a first FSMC driving module, the first FSMC driving module reads an address signal of the address buffer and sends the address signal to the multi-path selection unit, and the multi-path selection unit is switched to a corresponding acquisition card according to the address signal.

6. The ARM and FPGA based high efficiency data acquisition system of claim 5, wherein: the FPGA chip outputs the acquisition signals of the corresponding acquisition card through the first FSMC driving module, and the ARM chip receives the acquisition signals through the second FSMC driving module and outputs the acquisition signals through the corresponding external interface.

7. The ARM and FPGA based high efficiency data acquisition system of claim 4, wherein: the FSMC module comprises a plurality of acquisition card control units, a plurality of data cache units and a multi-path selection unit, wherein the acquisition card control units are respectively connected to acquisition cards, each acquisition card control unit is connected with one data cache unit, and all the data cache units are connected to the multi-path selection unit.

8. The ARM and FPGA-based high efficiency data acquisition system of claim 7, wherein: the data buffer unit is a first-in first-out data buffer unit.