CN215342505U - Wafer-level ASIC 3D integrated substrate and packaging device - Google Patents

Abstract

The utility model provides a wafer-level ASIC 3D integrated substrate and a packaging device. The substrate comprises a first wiring layer, a conductive column, a plastic packaging layer, a second wiring layer, a bridging chip and a solder ball; the first wiring layer comprises a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed on the surface of the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wire layer, and the second metal wire layer is exposed on the surface of the second dielectric layer; the conductive column is positioned between the first wiring layer and the second wiring layer, two ends of the conductive column are respectively electrically connected with the first metal wire layer and the second metal wire layer, and the bridging chip is electrically connected with the conductive column; the plastic packaging layer wraps the conductive column and the bridging chip; the solder ball is positioned on one side of the second wiring layer, which is far away from the conductive column, and is electrically connected with the second metal wire layer. By adopting the utility model for packaging, system-level packaging can be really realized, parasitic capacitance of the substrate can be eliminated, and noise of the device can be reduced; meanwhile, the power supply efficiency can be improved, and the response efficiency and reliability of the device can be improved.

Description

Wafer-level ASIC 3D integrated substrate and packaging device

Technical Field

The utility model relates to the technical field of semiconductor manufacturing, in particular to the field of back-end packaging, and specifically relates to a wafer-level ASIC (application specific integrated circuit) 3D integrated substrate and a packaging device.

Background

A printed Circuit board (pcb), which is also called a printed Circuit board (pcb), is a support for electronic components and a carrier for electrical connection, and is one of the commonly used package substrates. At present, the number of PCB boards applied in batch is 1-12, the more I/O interfaces of the chip are, the more the number of required PCB board layers is, and the price is high. The conventional substrate manufacturing process has a certain limit, for example, the minimum line width/pitch of the current PCB substrate is generally over 50 μm, the minimum line width/pitch of the ball grid array (BGA IC) carrier is 30/30 μm, and even the most advanced manufacturing process of the fine pitch ball grid array (FBGA IC) carrier can only make the minimum line width/pitch 20um/20 um. With the continuous improvement of the function integration of the previous chip, the existing packaging substrate technology cannot meet the previous requirement, so that a 2.5D & Fan-out wafer level (Fan out wafer) advanced packaging technology is needed, but the technology has the disadvantages of high manufacturing cost, long manufacturing time (compared with the manufacturing cost of the traditional substrate), and the like, and the advanced packaging technology is only suitable for packaging the wafer after the previous stage process is completed and cannot be customized in advance, so that the chip can be damaged in the packaging process.

SUMMERY OF THE UTILITY MODEL

In view of the above disadvantages of the prior art, an object of the present invention is to provide a wafer level ASIC 3D integrated substrate and a package device, which are used to solve the problems that the process margin exists in the prior art that the PCB substrate package technology is adopted, the line width cannot be further reduced, and the requirement of higher and higher integration level of electronic devices cannot be met, and the fan-out wafer level package technology has high cost, long manufacturing time, and chip damage may be caused during the packaging process.

To achieve the above and other related objects, the present invention provides a wafer level ASIC 3D integrated substrate, which includes:

providing a carrier, and forming a separation layer on the carrier;

forming a first wiring layer on the separation layer, wherein the first wiring layer comprises a first dielectric layer and a first metal wire layer, and the first metal wire layer is exposed on the surface of the first dielectric layer;

forming a conductive pillar on the first routing layer, the conductive pillar being electrically connected to the first metal line layer;

electrically connecting the bridge chip with the conductive posts;

forming a plastic packaging layer, wherein the plastic packaging layer wraps the conductive posts and the bridging chip, and the conductive posts are exposed on the surface of the plastic packaging layer;

forming a second wiring layer on the plastic packaging layer, wherein the second wiring layer comprises a second dielectric layer and a second metal wire layer, the second metal wire layer is exposed on the surface of the second dielectric layer, and the second metal wire layer is electrically connected with the conductive column;

forming a solder ball on the second wiring layer, wherein the solder ball is electrically connected with the second metal wire layer;

and stripping the carrier from the separation layer to expose the surface of the first wiring layer, which is far away from the conductive pillar, and expose the first metal wire layer on the surface of the first wiring layer.

Optionally, the thickness of the first wiring layer and the thickness of the second wiring layer are 15 μm to 40 μm, and the thickness of the plastic package layer is 50 μm to 100 μm.

Optionally, the preparation method further includes a step of forming an OSP antioxidation layer on a surface of the first wiring layer away from the conductive pillar before peeling the carrier, where the OSP antioxidation layer covers a surface of the first metal wire layer.

Optionally, the number of the wafer-level ASIC 3D integrated substrates is multiple, and the preparation method further includes a step of separating the wafer-level ASIC 3D integrated substrates from each other by cutting and molding after forming the OSP antioxidation layer.

The utility model also provides a wafer-level ASIC 3D integrated substrate, wherein the wafer-level ASIC 3D integrated substrate comprises a first wiring layer, a conductive column, a bridging chip, a plastic packaging layer, a second wiring layer and a solder ball; the first wiring layer comprises a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed on the surface of the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wire layer, and the second metal wire layer is exposed on the surface of the second dielectric layer; the conductive column is positioned between the first wiring layer and the second wiring layer, two ends of the conductive column are respectively and electrically connected with the first metal wire layer and the second metal wire layer, and the bridging chip is electrically connected with the conductive column; the plastic packaging layer wraps the conductive column and the bridging chip; the solder balls are positioned on one side, away from the conductive columns, of the second wiring layer and are electrically connected with the second metal wire layer.

Optionally, the wafer level ASIC 3D integrated substrate further includes an OSP antioxidation layer, where the OSP antioxidation layer is located on the surface of the first wiring layer away from the conductive pillar, and covers the surface of the first metal wire layer.

The packaging device provided by the utility model comprises a functional chip and the wafer-level ASIC 3D integrated substrate in any scheme, wherein the functional chip is arranged on the surface of the wafer-level ASIC 3D integrated substrate and is electrically connected with the wafer-level ASIC 3D integrated substrate.

Optionally, the functional chip includes an active device, the package device further includes an inductor and a capacitor, and the active device is located on a surface of the first wiring layer away from the molding compound layer and electrically connected to the first wiring layer; the active devices comprise one or more of SOC devices, HBM devices, SSI devices and PMU devices, and each active device is single or multiple; the inductor and the capacitor are located on the surface of the wafer-level ASIC 3D integrated substrate and are electrically connected with the second wiring layer.

Optionally, the package device further includes a passive device, where the passive device is located on a surface of the second wiring layer away from the molding compound layer, and is electrically connected to the second wiring layer.

In an alternative, the package device further includes a protection layer and an antenna, the protection layer covers the active device, and the antenna is located on a surface of the protection layer and electrically connected to the conductive pillar.

In another alternative, the package device further comprises a protection layer and an electromagnetic shielding layer, the protection layer covers the active device, and the electromagnetic shielding layer extends from the surface of the protection layer to the side faces of the first wiring layer and the plastic package layer.

As described above, the wafer level ASIC 3D integrated substrate and the package device of the present invention have the following advantages: the minimum line width and line distance of the wafer-level ASIC 3D integrated substrate can be reduced to 1.5/1.5um which is far smaller than 20/20um of the traditional substrate, so that high-density and high-integration device packaging can be realized; the thickness of the substrate can be less than 0.2mm (the thickness of a 10-layer plate of a traditional fine-pitch ball grid array is 1mm), which is beneficial to further reducing the packaging size of the device; the processing time of the substrate is short, large-scale customization can be realized, and the packaging cost is reduced; the chip package is not needed, the chip damage risk can be reduced, the package yield is improved, the bridging chip is connected into the substrate, and the integration level of the packaged device can be further improved. By adopting the wafer-level ASIC 3D integrated substrate to package, various electronic chips and components such as a millimeter wave antenna, a capacitor, an inductor, a transistor switch, a GPU, a PMU, a DDR, a flash memory, a filter and the like can be simultaneously integrated, and system-level packaging is really realized. The packaging device packaged by the wafer-level ASIC 3D integrated substrate not only can reduce the cost, but also can eliminate the substrate parasitic capacitance and reduce the device noise; meanwhile, the power supply efficiency can be improved, and the response efficiency and reliability of the device can be improved; the requirement on the design margin of the device is low, so that the application range of the packaging device is wider.

Drawings

Fig. 1 to 11 are schematic cross-sectional views of a wafer-level ASIC 3D integrated substrate according to the present invention in various steps during the manufacturing process.

Fig. 12-16 show schematic cross-sectional views of packaged devices provided in accordance with the present invention in various examples.

Fig. 17 is a schematic diagram illustrating an exemplary top view structure of a packaged device according to the present invention.

Description of the element reference numerals

11 vector

12 separating layer

13 first wiring layer

131 first dielectric layer

132 first metal wire layer

14 conductive post

15 Plastic packaging layer

16 second wiring layer

161 second dielectric layer

162 second metal wire layer

17 solder ball

18 OSP antioxidation layer

191 active device

192 passive component

20 bump

21 stage

22 bridge chip

23 antenna layer

24 electromagnetic shielding layer

25 inductance

26 capacitor

27 protective layer

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.

The traditional packaging technology adopts a PCB substrate or a fine-pitch ball grid array (FBGA) substrate for packaging, the minimum line width/line distance can only be 20um/20um, which can not meet the requirement of higher and higher integration level of the front-end chip at present, and adopts advanced packaging technologies such as 2.5D fan-out type wafer level and the like, which are only suitable for packaging the wafer after the front-end process is completed but can not be customized in advance, so that chip damage can be caused in the packaging process, and the problems of high cost, long manufacturing time and the like exist. The utility model people of the present case have proposed an improvement scheme through a large amount of research in long-term work.

Specifically, the utility model provides a wafer-level ASIC 3D integrated substrate, and the preparation method comprises the following steps:

providing a carrier 11 (refer to fig. 1), and forming a separation layer 12 on the carrier 11, wherein the obtained structure is shown in fig. 2;

forming a first wiring layer 13 (which may also be referred to as a front-side wiring layer because the wiring layer is to be used for mounting to the front side of a chip in a subsequent device package) on the separation layer 12, where the first wiring layer 13 includes a first dielectric layer 131 and a first metal wire layer 132, and the first metal wire layer 132 is exposed on the surface of the first dielectric layer 131, and the resulting structure is as shown in fig. 3;

forming conductive pillars 14 on the first routing layer 13, the conductive pillars 14 including but not limited to copper pillars, the conductive pillars 14 being electrically connected to the first metal line layer 132; in an example, the conductive pillars 14 may be formed by forming a metal seed layer by using a vapor deposition process including but not limited to a vapor deposition process, then forming an electroplated copper layer on a surface of the metal seed copper layer by using a plating process including but not limited to an electroplating process, and then performing photolithography etching on the formed electroplated copper layer and the metal seed layer to form a plurality of spaced conductive pillars 14;

electrically connecting a Bridge chip (Bridge IC)22 to the conductive posts 14, for example, attaching the Bridge chip 22 to the surfaces of the conductive posts 14, so that the Bridge chip 22 is flush or nearly flush with the upper surfaces of the other conductive posts 14 (the conductive posts not connected to the Bridge chip), and the structure obtained after this step is as shown in fig. 4; of course, in other examples, the bridge chip 22 may be attached to the surface of the first wiring layer, and then the conductive pillars 14 are formed, which is not limited to this, but the conductive pillars are formed first and then connected to the bridge chip, so that the bridge chip may be prevented from being damaged in the process of forming the conductive pillars; the bridging chip is accessed, so that more chips of different types can be accessed to the substrate during subsequent packaging, and the packaging integration level is further improved;

after the bridge chip 22 is connected, a molding layer 15 is formed, the conductive posts 14 and the bridge chip 22 are covered by the molding layer 15, and the conductive posts 14 and the bridge chip 22 are exposed on the surface of the molding layer 15; specifically, the molding compound layer 15 covering the conductive pillars 14 and the bridge chip 22 may be formed by one or more combinations of methods including, but not limited to, compression molding, transfer molding, liquid sealing, vacuum lamination, spin coating, etc., and the resulting structure is as shown in fig. 5, and then a planarization process is performed by using, but not limited to, a grinding method, so that the upper surfaces of the conductive pillars 14 are flush with the upper surface of the molding compound layer 15, so as to obtain the structure shown in fig. 6, where the material of the molding compound layer 15 includes one or more combinations of, but not limited to, polyimide, silicone, and epoxy resin; of course, in other examples, the molding layer 15 may be formed, then the opening is formed in the molding layer 15, and then the opening is filled with the metal material to form the conductive pillar 14, but forming the conductive pillar 14 first and then performing the molding can ensure the electrical connection between the conductive pillar 14 and the first wiring layer 13, thereby reducing the alignment difficulty;

forming a second wiring layer 16 (also referred to as a back wiring layer or a reverse wiring layer) on the plastic package layer 15, where the second wiring layer 16 includes a second dielectric layer 161 and a second metal wire layer 162, the second metal wire layer 162 is exposed on the surface of the second dielectric layer 161, and the second metal wire layer 162 is electrically connected to the conductive pillar 14 and can be electrically connected to the bridge chip 22 at the same time, and the obtained structure is as shown in fig. 7; of course, in other examples, if necessary, the conductive pillars and the wiring layer may also be formed on the second wiring layer to form a stack of 3 or more wiring layers;

forming solder balls 17 on the second wiring layer 16, wherein the solder balls 17 are electrically connected to the second metal wire layer 162, and the resulting structure is as shown in fig. 8; for example, an opening exposing the second metal wire layer 162 is formed on the second wiring layer 16, and then the solder ball 17 is formed in the corresponding opening by ball mounting, which helps to ensure good electrical contact between the solder ball 17 and the second metal wire layer 162; the material of the solder ball 17 includes but is not limited to tin, gold, copper or an alloy of tin and copper;

after the solder balls 17 are formed, the carrier 11 is peeled off from the separation layer 12 to expose the surface of the first wiring layer 13 away from the conductive pillars 14, and the first metal wire layer 132 is exposed on the surface of the first wiring layer 13, for example, the structure obtained in the foregoing steps is placed upside down (i.e., the solder balls 17 face down) on a stage 21, and depending on the material of the separation layer 12, for example, if the separation layer 12 is a UV resin layer, the separation layer 12 may be irradiated with UV light to peel off the carrier 11, which is shown in fig. 9; to avoid oxidation of the exposed metal wire layer in the air, in an example, before the carrier 11 is stripped, an OSP antioxidation layer 18 may be formed on a surface of the first wiring layer 13 away from the conductive pillar 14, the OSP antioxidation layer 18 covers a surface of the first metal wire layer 132, the resulting structure is shown in fig. 10, and after the carrier 11 is stripped, the resulting structure is shown in fig. 11. The OSP (organic solder resist) oxide layer is an organic solder mask, also called copper-protecting agent, and is prepared by chemically growing an organic film on the surface of the clean first metal wire layer 132 (such as copper layer). The OSP antioxidation layer 18 has the characteristics of oxidation resistance, thermal shock resistance, moisture resistance and the like, can prevent the surface of the first metal wire layer 132 exposed to air from rusting (oxidation, vulcanization and the like), but can be easily and quickly cleaned by the soldering flux in the subsequent high welding temperature, so that the exposed surface of the first metal wire layer 132 can be immediately combined with the molten solder ball 17 to form a firm welding spot in a very short time.

The wafer-level ASIC 3D integrated substrate is manufactured by adopting a semiconductor front-end manufacturing process, so that the minimum line width/line distance can be 1.5/1.5um, the whole thickness of the substrate can be less than 0.2mm, and when the wafer-level ASIC 3D integrated substrate is used for packaging devices, high-density and high-integration packaging can be realized, and the further reduction of the packaging size of the devices is facilitated. The preparation process of the substrate is simple, large-scale customization can be realized, the process time is shortened, the packaging cost is reduced, no chip is required in the preparation process of the substrate, the chip damage risk can be reduced, and the packaging yield is improved.

As an example, the first wiring layer 13 is formed by first forming a first dielectric layer 131 on the separation layer 12 by using a vapor deposition process, and then forming an opening corresponding to the first metal wire layer 132 in the first dielectric layer 131 by using a photolithography and etching process, and then forming a first metal material layer by combining one or more methods including, but not limited to, a sputtering method, an electroplating method, and a chemical plating method into the opening and on the surface of the first dielectric layer 131 to form the first metal wire layer 132. The first dielectric layer 131 is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and may be made of other high-K dielectric materials; the material of the first metal wire layer 132 includes, but is not limited to, a combination of one or more of gold, silver, copper, aluminum, etc. (preferably a copper layer). The first dielectric layer 131 and the first metal wire layer 132 may be of a single-layer or multi-layer structure, but it is necessary to ensure that the first metal wire layers 132 of different layers are electrically connected to each other. The material and manufacturing process of the second wiring layer 16 may be the same as those of the first wiring layer 13, and detailed description thereof is omitted.

As an example, the thickness of the first wiring layer 13 and the thickness of the second wiring layer 16 are 15 μm to 40 μm, and the thickness of the first wiring layer 13 and the thickness of the second wiring layer 16 may be the same or different, and are specifically set as required. The specific structures of the first wiring layer 13 and the second wiring layer 16 can be flexibly adjusted according to the number/type of chips to be packaged, so that the integrated substrate of the utility model can be applied to various packaging structures.

In one example, the thickness of the molding layer 15 is 50 μm to 100 μm. By forming the conductive posts 14 and the plastic package layer 15 covering the conductive posts 14, the height of the entire substrate can be increased, which is beneficial to further reducing the stress of the substrate and is beneficial to subsequent device packaging.

The carrier 11 mainly plays a supporting role, and avoids the defects of bending deformation and the like in the device preparation process. By way of example, the carrier 11 includes, but is not limited to, a glass, a silicon substrate, a sapphire substrate, a ceramic substrate, a metal substrate, and the like, which have a certain hardness and are not easily bent. In this embodiment, a transparent substrate such as a glass substrate is preferable, which facilitates the subsequent peeling of the separation layer 12, and the support 11 can be peeled from the separation layer 12 by irradiating UV light from the back surface of the support 11. Before the separation layer 12 is prepared, the carrier 11 may be washed and dried.

The separation layer 12 may be a single-layer or multi-layer structure, and may include, for example, a release layer and a protective layer on the surface of the release layer. Specifically, the release layer includes, but is not limited to, a combination of one or more of a carbon material layer, a resin material layer, and an organic material layer, and the protective layer includes, but is not limited to, a polyimide layer. For example, the carrier 11 is a transparent substrate such as glass, and the separation layer 12 is a UV resin layer, and the separation layer 12 may be peeled off by irradiating the separation layer 12 from the back surface of the carrier 11 at the time of subsequent peeling. The separation layer 12 may also be an LTHC light-to-heat conversion layer, and the subsequent step may be heating the LTHC light-to-heat conversion layer based on a method such as laser, so as to separate the carrier 11 from the LTHC light-to-heat conversion layer, thereby reducing the difficulty of the stripping process and preventing the device from being damaged. The method for forming the separation layer 12 may be determined according to the material thereof, and may be one or more selected from spin coating, spray coating, direct attachment, and the like.

The preparation method can prepare a single or a plurality of wafer-level ASIC 3D integrated substrates at the same time, and when a plurality of wafer-level ASIC 3D integrated substrates are prepared, the preparation method further comprises the step of separating the wafer-level ASIC 3D integrated substrates from each other by cutting and forming after the OSP oxidation resisting layer 18 is formed. Of course, dicing may be performed after the chip is mounted on the substrate.

The utility model also provides a wafer level ASIC 3D integrated substrate, which can be prepared based on any preparation method, so the contents can be fully cited. Specifically, as shown in fig. 11, the wafer level ASIC 3D integrated substrate includes a first wiring layer 13, a conductive pillar 14, a bridge chip 22, a molding layer 15, a second wiring layer 16, and a solder ball 17; the first wiring layer 13 includes a first dielectric layer 131 and a first metal wire layer 132, the first metal wire layer 132 is exposed on the surface of the first dielectric layer 131, the second wiring layer 16 includes a second dielectric layer 161 and a second metal wire layer 162, and the second metal wire layer 162 is exposed on the surface of the second dielectric layer 161; the conductive pillars 14 are located between the first wiring layer 13 and the second wiring layer 16, and two ends of each conductive pillar are electrically connected to the first metal line layer 132 and the second metal line layer 162, respectively, one end of the bridge chip 22 is electrically connected to the conductive pillar 14, the other end of the bridge chip is flush with the upper surface of the other conductive pillar 14, and the other end of the bridge chip can be electrically connected to the second wiring layer 16; the conductive posts 14 and the bridge chip 22 are covered by the plastic package layer 15; the solder balls 17 are located on a side of the second wiring layer 16 away from the conductive pillars 14, and are electrically connected to the second metal wire layer 162.

As an example, the wafer level ASIC 3D integrated substrate further includes an OSP oxidation resistant layer 18, where the OSP oxidation resistant layer 18 is located on a surface of the first wiring layer 13 away from the conductive pillar 14 and covers a surface of the first metal wire layer 132.

For more descriptions of the wafer level ASIC 3D integrated substrate, please refer to the foregoing, which is not repeated for brevity. The wafer level ASIC 3D integrated substrate can be used in 2.5D packaging and 3D packaging, the whole body of the wafer level ASIC 3D integrated substrate is used as a silicon Interposer (silicon Interposer), various electronic chips and components such as a millimeter wave antenna, a capacitor, an inductor, a transistor switch, a GPU, a PMU, a DDR, a flash memory (flash), a filter and the like can be simultaneously integrated, and the wafer level ASIC 3D integrated substrate can be compatible with a traditional substrate, such as a fine pitch ball grid array (FBGA) substrate. That is, the wafer level ASIC 3D integrated substrate according to the present invention can implement various packaging technologies such as System In a Package (SIP), flip chip scale Package (FCCSP), Antenna-In-Package (AIP), fan-out Package (FO), and the like.

The utility model also provides a packaging device which comprises a functional chip and the wafer-level ASIC 3D integrated substrate in any scheme, wherein the functional chip is arranged on the surface of the wafer-level ASIC 3D integrated substrate and is electrically connected with the wafer-level ASIC 3D integrated substrate. For more descriptions of the wafer level ASIC 3D integrated substrate, please refer to the foregoing, which is not repeated for brevity. According to the manufacturing method of the packaging device, after the wafer-level ASIC 3D integrated substrate is completed, the functional chips can be welded to the front side or the back side of the substrate through bumps 20(bump) or pads (pad) on each functional chip according to the type of the functional chip. In addition, passive devices such as inductors and capacitors can be attached to the surface of the substrate, and various packaged devices packaged on the basis of the 3D integrated substrate will be described in detail.

In an example, the functional chip includes an active device 191, the package device further includes an inductor 25 and a capacitor 26, the active device 191 is located on a surface of the first wiring layer 13 facing away from the molding compound layer 15 and is electrically connected to the first wiring layer 13, and the inductor 25 and the capacitor 26 are located on a surface of the wafer level ASIC 3D integrated substrate and are electrically connected to the second wiring layer 16 (although in other examples, the inductor 25 and the capacitor may also be electrically connected to the first wiring layer). Specifically, as shown in fig. 12 (for simplicity of illustration, specific structures of the first wiring layer 13 and the second wiring layer 16 are not illustrated in fig. 12-16), the active device 191 includes one or more of an SOC device (system on chip), an HBM (high Bandwidth memory) device, an SSI device (small scale integrated circuit) and a PMU device (Power Management Unit) device, each active device is single or multiple, for example, in this example, the HBM device and the SOC device are both 2 and the HBM device and the PMU device are both single, each active device is arranged on the front side (i.e., the side facing away from the front side) of the substrate at intervals, and an inductor and a capacitor are arranged corresponding to each active device, for example, each active device corresponds to an inductor and capacitor pair up and down.

In another example, as shown in fig. 13, the package device includes not only the active device 191, the inductor 25 and the capacitor 26, the active device 191 includes one or more of an SOC device (system on chip), an hbm (high Bandwidth memory) device, an SSI device (small scale integrated circuit) and a PMU device (Power Management Unit) device, each active device is single or multiple, and the arrangement of the active device 191, the inductor 25 and the capacitor 26 is the same as that in fig. 12, the package device further has a protective layer 27 and an antenna 23, the protective layer 27 covers the active device 191, the antenna 23 is located on the surface of the protective layer 27 and is electrically connected to the conductive pillar 14, for example, after the functional chip is mounted, an electrical lead-out structure electrically connected to a first wiring layer is formed, and the electrical lead-out structure is exposed on the surface of the protective layer 27, electrically connected to the antenna formed later. In an example, the protection layer 27 may be a plastic package material layer, and after the active device is attached (for example, attached to the surface of the first wiring layer by conductive silver paste) or soldered to the surface of the first wiring layer, the protection layer covering the active device is formed by spin coating or other processes. Of course, in other examples, the protective layer 27 may also be a prefabricated plastic housing, which is sleeved on the periphery of the active device 191, and the antenna 23 may be pre-prepared and then disposed on the surface of the protective layer 27, or the antenna may be formed by a sputtering process after the protective layer 27 is formed.

In another example, as shown in fig. 14, the package device includes not only the active device 191, the inductor 25 and the capacitor 26, where the active device 191 includes one or more of an SOC device (system on chip), an hbm (high Bandwidth memory) device, an SSI device (small scale integrated circuit) and a PMU device (Power Management Unit) device, each of the active devices is single or multiple, and the active device 191, the inductor 25 and the capacitor 26 are arranged in the same manner as in fig. 12, the package device further includes a protection layer 27 and an electromagnetic shielding layer 24, where the protection layer 27 covers the active device 191, and the electromagnetic shielding layer 24 extends from a surface of the protection layer 27 to a side of the first wiring layer 13 and the molding layer 15. The protective layer 27 may also be a plastic package material layer or a prefabricated plastic housing, and the electromagnetic shielding layer 24 may also be a prefabricated metal layer or be prepared on the protective layer 27 by a sputtering process.

In another example, as shown in fig. 15, the packaged Device includes an active Device 191, a Passive Device 192, an inductor 25 and a capacitor 26, the active Device 191 is located on a surface of the first wiring layer 13 facing away from the molding layer 15 and is electrically connected to the first wiring layer 13, and the Passive Device (IPD) is located on a surface of the second wiring layer 16 facing away from the molding layer 15 and is electrically connected to the second wiring layer 16; the inductor 25 and the capacitor 26 are located on the surface of the wafer-level ASIC 3D integrated substrate, and are electrically connected to the second wiring layer 16 (although they may also be electrically connected to the first wiring layer in other examples), and the active device 191 includes one or more of an SOC device (system on chip), an hbm (high Bandwidth memory) device, an SSI device (small scale integrated circuit), and a PMU device (Power Management Unit), where each active device is single or multiple; in a further example, the package device further has a protective layer 27 and an antenna 23, the protective layer 27 covers the active device 191, and the antenna 23 is located on the surface of the protective layer 27 and electrically connected to the conductive pillar 14. The protective layer 27 may also be a plastic package material layer or a prefabricated housing, and the antenna 23 may also be prefabricated or formed by a sputtering process, for which reference is made to the foregoing specifically, which is not repeated herein for the sake of brevity. Namely, the packaged device of the present embodiment is obtained by adding the passive device 192 to fig. 13.

In yet another example, as shown in fig. 16, the packaged device includes an active device 191, a passive device 192, an inductor 25, a capacitor 26, a protection layer 27 and an electromagnetic shielding layer 24, where the active device 191 includes one or more of an SOC device (system on chip), an hbm (high Bandwidth memory) device, an SSI device (small scale integrated circuit) and a PMU device (Power Management Unit) device, each active device is single or multiple, the protection layer 27 covers the active device 191, and the passive device 192 is located on a surface of the second wiring layer 16 away from the molding layer 15 and is electrically connected to the second wiring layer 16; the electromagnetic shielding layer 24 extends from the surface of the protection layer 27 to the side of the first wiring layer 13 and the molding layer 15. The protective layer 27 may also be a plastic package material layer or a prefabricated plastic housing, and the electromagnetic shielding layer 24 may also be a prefabricated metal layer or be prepared on the protective layer 27 by a sputtering process. That is, the package structure of this embodiment adds the passive device 192 on the back surface of the substrate (i.e., the surface where the solder balls are located) on the basis of the example shown in fig. 14.

As shown in fig. 17, the package device may be an all-in-one package Module (AIP Module), which may simultaneously integrate devices such as a Processor (Processor), a Sensor (Sensor), a Data Encryption chip (Data Encryption), an execution device (initiator), a Memory (Memory), a connector (connection), a secure-in-Security chip (secure), and the like, and each of the devices may be arranged on a surface of the package substrate, and an antenna and/or an electromagnetic shielding layer (EMI Shield) may be formed on a surface of the package device.

By adopting the wafer-level ASIC 3D integrated substrate, the integration level of the packaging device can be further improved, the size can be further reduced, the cost can be further reduced, and the parasitic capacitance of the substrate can be eliminated to reduce the noise of the device; meanwhile, the power supply efficiency can be improved, and the response efficiency and reliability of the device can be improved. The packaging device has low requirement on Design Margin (Design Margin), and can further improve the applicability of the packaging device.

In summary, the utility model provides a wafer level ASIC 3D integrated substrate and a package device. By adopting the wafer-level ASIC 3D integrated substrate, the minimum line width and line distance of the package can be reduced to 1.5/1.5um which is far smaller than 20/20um of the traditional substrate, so that the device package with high density and high integration level can be realized; the thickness of the substrate can be less than 0.2mm (the thickness of a traditional FBGA 10 laminate is 1mm), which is beneficial to further reducing the packaging size of the device; the processing time of the substrate is short, large-scale customization can be realized, and the packaging cost is reduced; the chip package is not needed, the chip damage risk can be reduced, the package yield is improved, the substrate is integrated with the bridging chip, and the package integration level can be further improved. By adopting the wafer-level ASIC 3D integrated substrate to package, various electronic chips and components such as a millimeter wave antenna, a capacitor, an inductor, a transistor switch, a GPU, a PMU, a DDR, a flash memory, a filter and the like can be simultaneously integrated, and system-level packaging is really realized. The packaging device packaged by the wafer-level ASIC 3D integrated substrate not only can reduce the cost, but also can eliminate the substrate parasitic capacitance and reduce the device noise; meanwhile, the power supply efficiency can be improved, and the response efficiency and reliability of the device can be improved; the requirement on the design margin of the device is low, so that the packaging substrate has wide applicability. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A wafer-level ASIC 3D integrated substrate is characterized in that the wafer-level ASIC 3D integrated substrate comprises a first wiring layer, a conductive column, a bridging chip, a plastic packaging layer, a second wiring layer and a solder ball; the first wiring layer comprises a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed on the surface of the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wire layer, and the second metal wire layer is exposed on the surface of the second dielectric layer; the conductive column is positioned between the first wiring layer and the second wiring layer, two ends of the conductive column are respectively and electrically connected with the first metal wire layer and the second metal wire layer, and the bridging chip is electrically connected with the conductive column; the plastic packaging layer wraps the conductive column and the bridging chip; the solder balls are positioned on one side, away from the conductive columns, of the second wiring layer and are electrically connected with the second metal wire layer.

2. The wafer-level ASIC 3D integrated substrate of claim 1, wherein the thickness of the first and second wiring layers is 15 to 40 μ ι η.

3. The wafer-level ASIC 3D integrated substrate of claim 1, wherein the thickness of the molding layer is 50 μ ι η to 100 μ ι η.

4. The wafer-level ASIC 3D integrated substrate of claim 1, in which the conductive pillars comprise copper pillars.

5. The wafer-level ASIC 3D integrated substrate of claim 1, wherein the wafer-level ASIC 3D integrated substrate further comprises an OSP oxidation resistant layer located on a surface of the first routing layer facing away from the conductive pillars and overlying a surface of the first metal line layer.

6. A packaged device, comprising a functional chip and the wafer-level ASIC 3D integrated substrate of claim 1, wherein the functional chip is disposed on a surface of the wafer-level ASIC 3D integrated substrate and electrically connected to the wafer-level ASIC 3D integrated substrate.

7. The packaged device according to claim 6, wherein the functional chip comprises an active device, the packaged device further comprises an inductor and a capacitor, and the active device is located on a surface of the first wiring layer facing away from the molding compound layer and is electrically connected with the first wiring layer; the active devices comprise one or more of SOC devices, HBM devices, SSI devices and PMU devices, and each active device is single or multiple; the inductor and the capacitor are located on the surface of the wafer-level ASIC 3D integrated substrate and are electrically connected with the second wiring layer.

8. The packaged device of claim 7, further comprising a passive device on a surface of the second wiring layer facing away from the molding layer and electrically connected to the second wiring layer.

9. The package device according to claim 7 or 8, further comprising a protection layer and an antenna, wherein the protection layer covers the active device, and the antenna is located on a surface of the protection layer and electrically connected to the conductive pillar.

10. The packaged device according to claim 7 or 8, wherein the packaged device further comprises a protection layer and an electromagnetic shielding layer, the protection layer covers the active device, and the electromagnetic shielding layer extends from a surface of the protection layer to a side surface of the first wiring layer and the molding layer.

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