CN214702569U - Pressure sensor - Google Patents

Abstract

The utility model relates to a pressure sensor, which comprises a substrate structure and a top layer structure, wherein in the top layer structure, a first silicon layer is used as a pressure sensitive film; the second silicon layer serves as a piezoresistive layer; the front surface of the first silicon layer is provided with a thick semiconductor material layer used as an island structure; a top lower insulating layer which coats the first silicon layer and the thick semiconductor material layer is also formed on the front surface of the first silicon layer; the upper surface of the substrate structure is recessed downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove; a first electric connection channel used for self detection is formed between the first silicon layer and the substrate structure; forming a second electrical connection channel between the second silicon layer and the substrate structure for use as a piezoresistive structure; the first electrical connection channel is insulated from the second electrical connection channel, and the second electrical connection channel is insulated from the first silicon layer. The pressure sensor forms a capacitance structure between the island structure and the substrate structure, and the purpose of online self-calibration of the pressure sensor is achieved.

Description

Pressure sensor

Technical Field

The utility model relates to a pressure sensor technical field especially relates to a pressure sensor.

Background

With the rise of industries such as the internet of things, MEMS (Micro electro Mechanical Systems) sensors have a huge application prospect due to the advantages of small size, low power consumption, light weight, fast response and the like. In particular, MEMS pressure sensors have great application in the fields of automotive electronics, consumer products, industrial control and the like.

At present, the MEMS pressure sensor mostly adopts the electrical isolation between PN strong instant force sensitive piezoresistive elements. Under the condition of normal temperature, the PN junction can effectively prevent the generation of leakage current, but under the condition of high temperature (generally more than 150 ℃), the leakage current of the PN junction is obviously increased, the stability of the output of the sensor is influenced, and even the sensor is failed, so that the MEMS pressure sensor adopting the PN junction can only work in the environment of less than 150 ℃.

In addition, the existing MEMS pressure sensor also adopts a pressure sensing mode on the back side of the pressure sensitive film, which increases the nonlinearity of the pressure sensitive film, but when the measured pressure is too high, the sealing material of the front-side mounted chip leaks air, or is pushed away by high pressure, which makes the pressure range that the MEMS pressure sensor can measure limited, and the existing technology cannot avoid the nonlinear increase effect of pressure measurement.

In addition, the conventional piezoresistive pressure sensor generally performs detection through an additional detection device, and cannot perform online self-detection.

SUMMERY OF THE UTILITY MODEL

Based on this, the utility model provides a pressure sensor, constitute the electric capacity structure between island structure and the substrate structure, reach pressure sensor's online self calibration's purpose.

A pressure sensor comprises a substrate structure and a top layer structure, wherein the top layer structure comprises a first silicon layer, a second silicon layer arranged on the back of the first silicon layer and a first insulating layer arranged between the first silicon layer and the second silicon layer; the first silicon layer serves as a pressure sensitive membrane; the second silicon layer serves as a piezoresistive layer; a thick semiconductor material layer electrically communicated with the first silicon layer is formed on the front surface of the first silicon layer, and the thick semiconductor material layer is used as an island structure; a top lower insulating layer which coats the first silicon layer and the thick semiconductor material layer is also formed on the front surface of the first silicon layer;

the upper surface of the substrate structure is recessed downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove;

a first electrical connection hole and a second electrical connection hole are formed on the pressure sensor; the first electrical connecting hole is filled with a conductive semiconductor material so that a first electrical connecting channel used for self detection is formed between the first silicon layer and the substrate structure; the second electrical connecting hole is filled with a conductive semiconductor material so that a second electrical connecting channel serving as a piezoresistive structure is formed between the second silicon layer and the substrate structure;

the first electrical connection channel is insulated from the second electrical connection channel, which is insulated from the first silicon layer.

In the pressure sensor, the front surface of the first silicon layer is provided with a thick semiconductor material layer which is conducted with the first silicon layer and is used as an island structure, the thick semiconductor material layer is bonded in a bonding groove of a substrate structure and forms a gap with the bonding groove, and a first electric connection channel is formed between the first silicon layer and the substrate structure, so that a capacitor structure is formed between the island structure and the substrate structure. In addition, the thick semiconductor material layer used as the island structure is formed on the front surface of the first silicon layer, and the front surface pressure sensing technology of the pressure sensitive film (namely the first silicon layer) is utilized, so that the phenomenon that the sealing material leaks or is pushed away by high pressure can be avoided, meanwhile, the nonlinearity of the pressure sensitive film can be reduced, and the range of measurable pressure can be increased.

In one embodiment, the substrate structure comprises a middle silicon material layer and an upper substrate insulating layer formed on the upper surface of the middle silicon material layer, and the lower surface of the middle silicon material layer is doped to form a doped layer.

In one embodiment, a first substrate region, a second substrate region and a third substrate region are formed on the substrate structure, wherein the first substrate region, the second substrate region and the third substrate region are insulated from each other, the first silicon layer is conducted with the first substrate region through the first electrical connection hole, the second silicon layer is conducted with the second substrate region through the second electrical connection hole, and the bonding groove is formed in the third substrate region;

the pressure sensor also comprises a first insulating protection layer deposited on the upper surface of the top layer structure and a second insulating protection layer deposited on the lower surface of the substrate structure;

and a first conductive contact hole corresponding to the first substrate region, a second conductive contact hole corresponding to the second substrate region and a third conductive contact hole corresponding to the third substrate region are formed on the second insulating and protecting layer.

In one embodiment, the first substrate region is provided with at least one, the second substrate region is provided with at least one, and the third substrate region is provided with at least one;

the first conductive contact hole is provided with at least one, the second conductive contact hole is provided with at least one, and the third conductive contact hole is provided with at least one.

Drawings

Fig. 1 is a schematic longitudinal sectional view of a pressure sensor according to an embodiment of the present invention;

fig. 2 to 15 are process flow diagrams of the pressure sensor shown in fig. 1.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As shown in fig. 1, a pressure sensor manufactured based on a Double-layer silicon-on-insulator (DSOI) wafer according to an embodiment of the present invention includes: the structure comprises a substrate structure 1 and a top layer structure 2, wherein the top layer structure 2 comprises a first silicon layer 21, a second silicon layer 22 arranged on the back surface of the first silicon layer 21, and a first insulating layer 23 arranged between the first silicon layer 21 and the second silicon layer 22. The first silicon layer 231 functions as a pressure sensitive membrane. The second silicon layer 22 serves as a piezoresistive layer. The front surface of the first silicon layer 21 is formed with a thick semiconductor material layer 24 electrically conducting with the first silicon layer 21, the thick semiconductor material layer serving as an island structure; a top-layer lower insulating layer 25 is formed on the front surface of the first silicon layer 21 to cover the first silicon layer 21 and the thick semiconductor material layer 24.

The upper surface of the substrate structure 1 is recessed downwards to form a bonding groove 10, and the thick semiconductor material layer 24 is bonded in the bonding groove 10 and forms a gap with the bonding groove 10.

A first electrical connection hole 3 and a second electrical connection hole 4 are formed on the pressure sensor; the first electrical connection hole 3 is filled with a conductive semiconductor material so that a first electrical connection channel (shown by a dashed line in fig. 1) serving as a self-test is formed between the first silicon layer 21 and the substrate structure 1. The second electrical connection hole 4 is filled with a conductive semiconductor material so that a second electrical connection channel (shown by a dotted line in fig. 14) serving as a piezoresistive structure is formed between the second silicon layer 22 and the substrate structure 1.

The first electrical connection channel is insulated from the second electrical connection channel, which is insulated from the first silicon layer 21.

In the pressure sensor 1, a thick semiconductor material layer 24 which is used as an island structure and is conducted with the front surface of a first silicon layer 21 is formed, the thick semiconductor material layer 24 is bonded in a bonding groove 10 of a substrate structure 1 and forms a gap with the bonding groove 10, a first electric connection channel is formed between the first silicon layer 21 and the substrate structure 1, so that a capacitor structure is formed between the island structure and the substrate structure 1, when a voltage value is applied between the capacitors, an electrostatic force can pull the island structure to the substrate structure 1, so that a pressure sensitive film (namely, the first silicon layer 21) is driven to deform, and online self-calibration of the pressure sensor is performed by utilizing the effect. In addition, the thick semiconductor material layer 24 used as an island structure is formed on the front surface of the first silicon layer 21, and the front surface pressure sensing technology of the pressure sensitive film (i.e. the first silicon layer 21) can be used to avoid the occurrence of the phenomenon that the sealing material leaks or is pushed away by high pressure, and simultaneously, the nonlinearity of the pressure sensitive film can be reduced, and the range of measurable pressure can be increased. The utility model discloses pressure sensor adopts the DSOI wafer to the first silicon layer 21 of DSOI wafer is as the pressure sensitive membrane, and its thickness uniformity is good. The lateral dimensions of the pressure sensitive membrane are determined by the graphic dimensions of the bonding grooves 10 of the substrate structure 1, which are easy to control compared to the back-side cavity-opening approach of the prior art.

In one embodiment, as shown in fig. 1, the doping type of the first silicon layer 21 and the doping type of the second silicon layer 22 are consistent, so that the pressure sensor can improve the stability of the sensor output under high temperature (generally more than 150 degrees), reduce the probability of the failure of the pressure sensor, and operate in an environment with a temperature higher than 150 ℃. In one embodiment, the first silicon layer 21 and the second silicon layer 22 are both P-type doped.

In a preferred embodiment, the second silicon layer 22 may be doped by implanting boron ions, and the second silicon layer 22 has a doping concentration greater than 1E20cm^-3。

In one embodiment, as shown in fig. 1, the first insulating layer 23 is a silicon oxide layer.

In one embodiment, as shown in fig. 1, the thick semiconductor material layer 24 is doped in situ, and the doping type of the thick semiconductor material layer 24 is consistent with the doping type of the first silicon layer 21 so as to make the thick semiconductor material layer 24 and the first silicon layer 21 electrically conductive.

In one embodiment, as shown in fig. 1, the conductive semiconductor material is a polysilicon material doped in situ to realize electrical conduction between the first silicon layer 21 and the substrate structure 1, and to realize electrical conduction between the second silicon layer 22 and the substrate structure 1.

In one embodiment, as shown in fig. 1, the substrate structure 1 includes a middle silicon material layer 11 and an upper insulating layer 12 formed on an upper surface of the middle silicon material layer 11, and a lower surface of the middle silicon material layer 11 is doped to form a doped layer 13. Preferably, the doped layer 13 is doped by implanting boron ions, and the doping concentration of the doped layer 13 is greater than 1E20cm^-3。

In one embodiment, as shown in fig. 1, a first substrate region 111, a second substrate region 112 and a third substrate region 113 are formed on the middle silicon material layer 11, the first silicon layer 21 is electrically connected to the first substrate region 111 through the first electrical connection hole 3, the second silicon layer 22 is electrically connected to the second substrate region 112 through the second electrical connection hole 4, and the bonding groove 10 is formed in the third substrate region 113. The "first", "second", and "third" of the first substrate region 111, the second substrate region 112, and the third substrate region 113 are merely structural functional limitations, and do not represent the number of the respective regions. Specifically, at least one first substrate region 111 is provided, at least one second substrate region 112 is provided, and at least one third substrate region 113 is provided.

Further, in order to realize mutual insulation among the first substrate region 111, the second substrate region 112, and the third substrate region 113, as shown in fig. 1, at least one first electrical isolation trench 14 and at least one second electrical isolation trench 15 penetrating through the middle silicon material layer 11 are formed on the substrate structure 1, and trench insulation layers are grown on inner walls of the first electrical isolation trench 14 and the second electrical isolation trench 15, respectively. The "first" and "second" of the first electrical isolation trench 14 and the second electrical isolation trench 15 are only structural functional limitations, and do not represent the number of the electrical isolation trenches.

The first electrical isolation trench 14 is formed on the substrate structure 1 to surround a first substrate region 111 in conduction with the first silicon layer 21, the second electrical isolation trench 15 is formed on the substrate structure 1 to surround a second substrate region 112 in conduction with the second silicon layer 22, and a third substrate region 113 is formed on the substrate structure 1 except for the first substrate region 111 and the second substrate region 112, so that mutual insulation among the first substrate region 111, the second substrate region 112 and the third substrate region 113 is realized, and further, insulation between the first electrical connection channel and the second electrical connection channel is realized.

In one embodiment, as shown in fig. 1, the pressure sensor further comprises a first insulating and protecting layer 5 deposited on the upper surface of the top layer structure 1 and a second insulating and protecting layer 6 deposited on the lower surface of the substrate structure 1.

The second insulating protective layer 6 has a first conductive contact hole 61 corresponding to the first substrate region 111, a second conductive contact hole 62 corresponding to the second substrate region 112, and a third conductive contact hole 63 corresponding to the third substrate region 113. Through the arrangement of the first conductive contact hole 61, the second conductive contact hole 62 and the third conductive contact hole 63, the pressure sensor is electrified. The "first", "second", and "third" of the first conductive contact hole 61, the second conductive contact hole 62, and the third substrate region 113 are merely structural functional limitations, and do not represent the number of conductive contact holes. Specifically, at least one first conductive contact hole 61 is provided, at least one second conductive contact hole 62 is provided, and at least one third conductive contact hole 63 is provided.

Further, one or more first conductive contact holes 61 may be disposed in each first substrate region 111, one or more second conductive contact holes 62 may be disposed in each second substrate region 112, and one or more third conductive contact holes 63 may be disposed in each third substrate region 113.

In one embodiment, as shown in FIG. 1, the pressure sensor further includes a first metal block 7 disposed at the first conductive contact hole 61 and electrically conducted at the first substrate region 111, a second metal block 8 disposed at the second conductive contact hole 62 and electrically conducted at the second substrate region 112, and a third metal block 9 disposed at the third conductive contact hole 63 and electrically conducted at the third substrate region 113, to facilitate the energization of the pressure sensor.

As shown in fig. 2 to 14, a method for manufacturing a pressure sensor according to an embodiment of the present invention includes:

s1, select the first silicon wafer a shown in fig. 2, grow the front insulating layer 201 and the back insulating layer 202 on the front and back of the first silicon wafer a, respectively, and pattern the front insulating layer 201 to form a notch 2011 (see fig. 3). As shown in fig. 2, the first silicon wafer a is a Double-SOI (DSOI) wafer having a Double-layer "silicon on insulator" structure, and includes a first silicon layer 21, a first insulating layer 23, a second silicon layer 22, a second insulating layer 26, and a third silicon layer 27, which are sequentially stacked and covered, and a surface of the first silicon layer 21 facing away from the third silicon layer 27 is a front surface of the first silicon layer 21, that is, a front surface of the first silicon wafer a.

Preferably, the first silicon layer 21, the second silicon layer 22 and the third silicon layer 27 are doped with the same type, so that the pressure sensor has improved stability of sensor output under high temperature (generally greater than 150 degrees), the failure probability of the pressure sensor is reduced, and the pressure sensor can operate in an environment with temperature higher than 150 ℃. Furthermore, the doping concentrations and the crystal orientations of the first silicon layer 21, the second silicon layer 22 and the third silicon layer 27 can be freely selected according to actual needs, and in this embodiment, the first silicon layer 21, the second silicon layer 22 and the third silicon layer 27 are both doped with (100) crystal orientation and P-type dopant.

Further, the first insulating layer 23 and the second insulating layer 26 are both silicon oxide layers.

S2, a thick layer of semiconductor material 24 (see fig. 4) is formed at the notches 2011 to serve as an island structure.

Specifically, in step S2, the thick semiconductor material layer 24 is formed by:

first, thick semiconductor materials, such as epitaxially grown polysilicon materials, are grown on the front and back surfaces of the first silicon wafer a. The thick semiconductor material is doped in-situ (in-situ doping) such that the doping type of the thick semiconductor material is the same as the doping type of the first silicon layer 21 (e.g., in this embodiment, the thick semiconductor material is also doped P-type). In this way, the thick semiconductor material of the front side of the first silicon wafer a and the first silicon layer 21 can be electrically conducted. The thickness of the thick semiconductor material can be tailored to the design requirements of the pressure sensor.

Then, the thick semiconductor material on the back side of the first silicon wafer a is etched away, and the thick semiconductor material on the front side of the first silicon wafer a is patterned to form a thick semiconductor material layer 24 serving as an island structure.

S3, removing the front surface insulating layer 201 grown in S1, and regenerating a top underlying insulating layer 25 (as shown in fig. 5) covering the first silicon layer 21 and the thick semiconductor material layer 21 on the front surface of the first silicon wafer a, thereby obtaining a top primary structure. Preferably, the top-layer lower insulating layer 25 is formed by using a silicon oxide material.

And S4, forming a substrate structure 1, wherein the substrate structure 1 is provided with a bonding groove 10.

Specifically, in step S4, the substrate structure 1 is formed by:

first, a second silicon wafer b is selected, and the second silicon wafer b is used as the middle silicon material layer 11, and the substrate insulating layer 101 is formed on the upper surface and the lower surface of the second silicon wafer 11.

Then, the second silicon wafer b and the insulating base layer 101 formed on the upper surface of the second silicon wafer b are patterned to form the bonding grooves 10 (see fig. 6).

Then, the insulating base layer 101 on the upper surface of the second silicon wafer b is removed, and the insulating base layer 12 covering the upper surface 101 of the second silicon wafer b and the inner wall of the bonding groove 10 is regenerated on the upper surface 101 of the second silicon wafer b (as shown in fig. 7), so as to obtain the substrate structure 1.

S5, as shown in fig. 8, inverting the primary structure of the top layer, and bonding the thick semiconductor material layer 24 in the bonding groove 10, wherein a gap is formed between the thick semiconductor material layer 24 and the bonding groove 10.

And S6, removing the redundant layer structure.

Specifically, in step S6, the removing the unnecessary layer structure includes:

removing the back insulating layer 202, the third silicon layer 27 and the second insulating layer 26 of the top primary structure to obtain a top structure 2; the insulating base layer 101 formed on the lower surface of the second silicon wafer b is removed (see fig. 9).

After the removal of the unnecessary layer structure of step S6 is completed, the following steps may be performed:

as shown in fig. 10, the second silicon layer 22 is doped to form a piezoresistive layer, and a top insulating layer 203 is grown on the upper surface of the piezoresistive layer. The doping elements, concentrations and doping processes of the second silicon layer 22 may be selected according to the requirements, and typically, a boron ion implantation is performed, and the second silicon layer 22 is uniformly doped by using a high temperature annealing method, wherein the doping concentration is greater than 1E20cm^-3。

Doping the lower surface of the second silicon wafer b to form a doped layer 13, and growing a lower substrate insulating layer 102 on the lower surface of the doped layer 13.

S7, as shown in fig. 11 to 13, a first electrical connection hole 3 and a second electrical connection hole 4 are formed on the pressure sensor.

Specifically, in S7, the first electrical connection hole 3 (as shown in fig. 11) is formed by:

the first electrical connection hole 3 is formed through the substrate structure 1 and the top underlying insulating layer 25 on the pressure sensor using a through-silicon-via technique.

And the electrical signal of the front side of the pressure sensor is introduced to the back side of the pressure sensor by adopting the through silicon via technology, so that the front side of the pressure sensor can be subjected to surface mounting. At the same time, the front-side pressure sensing technology of the pressure sensitive film (i.e. the first silicon layer 21) can be adopted, namely, the nonlinearity of the pressure sensor is reduced, and the pressure measurable range of the pressure sensor is increased.

In S7, the second electrical connection hole 4 (as shown in fig. 12 and 13) is formed by:

first, an electrical connection via 204 is formed through the top layer structure 2 on the pressure sensor using a deep reactive ion etching technique of silicon.

Then, a connecting via insulating layer (e.g., silicon oxide) is grown on the inner wall of the connecting via 204, and the connecting via insulating layer surrounds a filling hole 205 (see fig. 12).

Then, etching the position of the insulating layer 12 on the substrate corresponding to the filling hole 205 to form the second electrical connection hole 4 penetrating through the top layer structure 2 and the insulating layer 12 on the substrate (see fig. 13).

In an embodiment, as shown in fig. 12 and 13, the substrate structure 1 is etched while the second electrical connection hole is formed in the step S7, so as to form a first electrical isolation trench 14 and a second electrical isolation trench 15 penetrating through the middle silicon material layer 11, and trench insulation layers are grown on inner walls of the first electrical isolation trench 14 and the second electrical isolation trench 15, respectively.

The first electrical isolation trench 14 is surrounded by a first substrate region 111 on the middle silicon material layer 11, the first substrate region 111 is electrically connected with the first silicon layer 21, the second electrical isolation trench 15 is surrounded by a second substrate region 112 on the middle silicon material layer 11, the second substrate region 112 is electrically connected with the second silicon layer 22, and a third substrate region 113 is formed on the middle silicon material layer 11 except for the first substrate region 111 and the second substrate region 112.

S8, forming a first electrical connection channel and a second electrical connection channel insulated from each other: after the first electrical connection hole 3 is formed, filling a conductive semiconductor material into the first electrical connection hole 3, so that a first electrical connection channel is formed between the first silicon layer 21 and the substrate structure 1 (as shown in fig. 1); after the second electrical connection hole 4 is formed, filling a conductive semiconductor material into the second electrical connection hole 4, so that a second electrical connection channel is formed between the second silicon layer 22 and the substrate structure 1 (as shown in fig. 14); the second electrical connection channel is insulated from the first silicon layer 21. The first electrical connection channel serves as a self-test for the pressure sensor and the second electrical connection channel serves as a piezoresistive structure.

Preferably, the conductive semiconductor material filled into the first electrical connection hole 3 and the second electrical connection hole 4 is an in-situ doped polysilicon material.

Further, the insulating layer 203 on the top layer may be patterned to form a via 2031 on the insulating layer corresponding to the second electrical connection hole 4 and partially exposing the second silicon layer 22 (see fig. 13), and then the via 2031 and the second electrical connection hole 4 are filled with a conductive semiconductor material to form a second electrical connection channel between the second silicon layer 22 and the substrate structure 1 (see fig. 14).

In an embodiment, the alignment precision of the relative positions of the piezoresistive structure and the island structure is determined only by the bonding precision, so that the influence caused by lateral etching in a back etching process can be effectively eliminated.

S9, removing a portion of the top-layer upper insulating layer 203 and the substrate lower insulating layer 102, and patterning the second silicon layer 22 to form a piezoresistive structure (see fig. 15).

And S10, depositing a first insulating protection layer 5 on the upper surface of the top layer structure 2, and depositing a second insulating protection layer 6 on the lower surface of the substrate structure 1. Preferably, the second insulating and protecting layer 6 can be formed by depositing a silicon nitride material.

S11, patterning the second insulating protection layer 6 to form a first conductive contact hole 61 corresponding to the first substrate region 111, a second conductive contact hole 62 corresponding to the second substrate region 112, and a third conductive contact hole 63 corresponding to the third substrate region 113.

S12, forming a first metal block 7 electrically conductive to the first substrate region 111 at the first conductive contact hole 61, forming a second metal block 8 electrically conductive to the second substrate region 112 at the second conductive contact hole 62, and forming a third metal block 9 electrically conductive to the third substrate region 113 at the third conductive contact hole 63. Preferably, the first metal block 7, the second metal block 8 and the third metal block 9 may be formed by depositing and patterning a high temperature resistant conductive metal Pad.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only represent preferred embodiments of the present invention, which are described in more detail and detail, but are not to be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (4)

1. A pressure sensor, characterized by: the structure comprises a substrate structure and a top layer structure, wherein the top layer structure comprises a first silicon layer, a second silicon layer arranged on the back surface of the first silicon layer and a first insulating layer arranged between the first silicon layer and the second silicon layer; the first silicon layer serves as a pressure sensitive membrane; the second silicon layer serves as a piezoresistive layer; a thick semiconductor material layer electrically communicated with the first silicon layer is formed on the front surface of the first silicon layer, and the thick semiconductor material layer is used as an island structure; a top lower insulating layer which coats the first silicon layer and the thick semiconductor material layer is also formed on the front surface of the first silicon layer;

the upper surface of the substrate structure is recessed downwards to form a bonding groove, and the thick semiconductor material layer is bonded in the bonding groove and forms a gap with the bonding groove;

a first electrical connection hole and a second electrical connection hole are formed on the pressure sensor; the first electrical connecting hole is filled with a conductive semiconductor material so that a first electrical connecting channel used for self detection is formed between the first silicon layer and the substrate structure; the second electrical connecting hole is filled with a conductive semiconductor material so that a second electrical connecting channel serving as a piezoresistive structure is formed between the second silicon layer and the substrate structure;

the first electrical connection channel is insulated from the second electrical connection channel, which is insulated from the first silicon layer.

2. The pressure sensor of claim 1, wherein: the substrate structure comprises a middle silicon material layer and an insulating layer formed on the substrate on the upper surface of the middle silicon material layer, and the lower surface of the middle silicon material layer is doped to form a doped layer.

3. The pressure sensor of claim 1, wherein: a first substrate region, a second substrate region and a third substrate region which are insulated from each other are formed on the substrate structure, the first silicon layer is conducted with the first substrate region through the first electrical connection hole, the second silicon layer is conducted with the second substrate region through the second electrical connection hole, and the bonding groove is formed in the third substrate region;

the pressure sensor also comprises a first insulating protection layer deposited on the upper surface of the top layer structure and a second insulating protection layer deposited on the lower surface of the substrate structure;

and a first conductive contact hole corresponding to the first substrate region, a second conductive contact hole corresponding to the second substrate region and a third conductive contact hole corresponding to the third substrate region are formed on the second insulating and protecting layer.

4. The pressure sensor of claim 3, wherein: at least one first substrate area, at least one second substrate area and at least one third substrate area are arranged in the first substrate area and the second substrate area respectively;

the first conductive contact hole is provided with at least one, the second conductive contact hole is provided with at least one, and the third conductive contact hole is provided with at least one.

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