CN214671744U - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN214671744U CN214671744U CN202120663128.1U CN202120663128U CN214671744U CN 214671744 U CN214671744 U CN 214671744U CN 202120663128 U CN202120663128 U CN 202120663128U CN 214671744 U CN214671744 U CN 214671744U
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Abstract
The embodiment of the utility model discloses pixel circuit and display panel. The pixel circuit comprises at least one electric leakage suppression module, wherein the first end of the electric leakage suppression module is connected with the drain electrode of the driving transistor or the first end of the electric leakage suppression module is connected with the signal wire, and the second end of the electric leakage suppression module is electrically connected with the grid electrode of the driving transistor; the leakage suppression module comprises at least two first transistors which are connected in series, at least one first transistor in the leakage suppression module is a double-gate transistor, the grid electrode of the first transistor is used as the control end of the leakage suppression module to be connected with a control signal, and the leakage suppression module which is connected with the grid electrode of the driving transistor and comprises the first transistors with the double-gate structure can reduce the leakage of the leakage suppression module; and the same control signal is accessed to the control ends of the top gate and the bottom gate, so that the double-gate transistor is favorably and completely turned off when the double-gate transistor is turned off, and the leakage of the leakage suppression module can be further reduced.
Description
Technical Field
The embodiment of the utility model provides a relate to and show technical field, especially relate to a pixel circuit and display panel.
Background
Unlike liquid crystal display, the active light emitting organic diode display panel is a control circuit of a current driving type, and a light emitting current flowing through a light emitting diode is controlled by one driving transistor. In the conventional pixel driving circuit, the gate potential of the driving transistor is unstable in the light emitting stage, which affects the display quality.
SUMMERY OF THE UTILITY MODEL
The utility model provides a pixel circuit and display panel to reduce drive transistor's electric leakage, improve the stability of drive transistor gate potential, improve the demonstration picture quality.
In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the first end of the electric leakage suppression module is connected with the drain electrode of the driving transistor or the first end of the electric leakage suppression module is connected with a signal wire, and the second end of the electric leakage suppression module is electrically connected with the grid electrode of the driving transistor;
the leakage suppression module comprises at least two first transistors which are connected in series, wherein at least one first transistor in the leakage suppression module is a double-gate transistor, the grid electrode of the first transistor is used as the control end of the leakage suppression module to access a control signal, the grid electrode of the double-gate transistor comprises a top gate and a bottom gate, and the top gate and the bottom gate access the same control signal.
Optionally, the active layer of the double-gate transistor is located between the top gate and the bottom gate;
preferably, the vertical projection of the top gate on the active layer covers the channel region of the double-gate transistor;
preferably, the vertical projection of the bottom gate on the active layer covers the channel region of the double-gate transistor.
Optionally, the width of the channel region of the double-gate transistor is 1-1.5 microns.
Optionally, the first transistors are both double-gate transistors.
Optionally, the pixel circuit includes a first leakage suppression module electrically connected to the gate of the driving transistor, a control terminal of the first leakage suppression module is electrically connected to a first scan signal input terminal, a first terminal of the first leakage suppression module is electrically connected to a data voltage signal line, and a second terminal of the first leakage suppression module is electrically connected to the gate of the driving transistor.
Optionally, the pixel circuit further includes a data writing module and a light emitting control module, and the pixel circuit includes a first leakage suppression module electrically connected to the gate of the driving transistor;
the control end of the data writing module is electrically connected with a first scanning signal line, the first end of the data writing module is electrically connected with a data voltage signal line, and the second end of the data writing module is electrically connected with the source electrode of the driving transistor;
the control end of the first leakage suppression module is electrically connected with the first scanning signal line, the first end of the first leakage suppression module is electrically connected with the drain electrode of the driving transistor, and the second end of the first leakage suppression module is electrically connected with the grid electrode of the driving transistor;
the light-emitting control module, the driving transistor and the light-emitting device are connected in series between a first power supply voltage signal line and a second power supply voltage signal line and used for controlling the connection state of the source electrode of the driving transistor and the first power supply voltage signal line and the connection state of the drain electrode of the driving transistor and the second power supply voltage signal line.
Optionally, the pixel circuit further includes a second leakage suppression module, wherein a control terminal of the second leakage suppression module is electrically connected to the second scan signal line, a first terminal of the second leakage suppression module is electrically connected to the initialization voltage signal line, and a second terminal of the second leakage suppression module is electrically connected to the gate of the driving transistor.
Optionally, the pixel circuit further includes an anode reset module, a control terminal of the anode reset module is electrically connected to the third scanning signal line, a first terminal of the anode reset module is electrically connected to the initialization voltage signal line, and a second terminal of the anode reset module is electrically connected to the anode of the light emitting device.
Optionally, the pixel circuit further comprises a storage module for storing the gate potential of the driving transistor.
In a second aspect, the present invention further provides a display panel, which includes the pixel circuit as described in the first aspect.
The utility model provides a pixel circuit and display panel, pixel circuit include with the grid of drive transistor be connected at least one electric leakage suppression module, the first end of electric leakage suppression module is connected the drain electrode of drive transistor or the first end of electric leakage suppression module is connected the signal line, and the second end of electric leakage suppression module is connected with the grid electricity of drive transistor; the leakage suppression module comprises at least two first transistors which are connected in series, wherein at least one first transistor in the leakage suppression module is a double-gate transistor, the grid electrode of the first transistor is used as the control end of the leakage suppression module to be connected with a control signal, the grid electrode of the double-gate transistor comprises a top gate and a bottom gate, and the top gate and the bottom gate are connected with the same control signal. The utility model discloses technical scheme, two first transistors of establishing ties can form horizontal double-gate structure in the electric leakage suppression module, and the double-gate transistor including top gate and bottom gate structure can form vertical double-gate structure, because the double-gate transistor has fine grid-control characteristic, include the double-gate transistor who is connected with drive transistor's grid through setting up the electric leakage suppression module for the leakage current of electric leakage suppression module self is less, guarantees the stability of drive transistor grid potential; and, the utility model discloses pixel circuit inserts the same control signal at the top gate of double gate transistor and the control end of bottom gate for turn-off or switch on through top gate and bottom gate common control double gate transistor, be favorable to turning off double gate transistor thoroughly, can further reduce the electric leakage of electric leakage suppression module self, and then improve the display image quality.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit in an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a double gate transistor according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel circuit in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit in an embodiment of the present invention;
fig. 5 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit in an embodiment of the present invention;
fig. 7 is a driving timing diagram of another pixel circuit in an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another pixel circuit in an embodiment of the present invention;
fig. 9 is a driving timing chart of another pixel circuit in the embodiment of the present invention;
fig. 10 is a schematic structural diagram of another pixel circuit in an embodiment of the present invention;
fig. 11 is a driving timing diagram of another pixel circuit in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the gate potential of the driving transistor is unstable during the light emitting period of the conventional pixel driving circuit, which affects the display quality. Through the utility model discloses people's research discovery, the reason why above-mentioned problem appears lies in, including the switch transistor who is connected with the drive transistor grid electricity in current pixel circuit, and in the luminescence phase, the switch transistor who is connected with the drive transistor grid electricity is in the off-state, and under the off-state, the switch transistor can not avoid there being the leakage current, arouses that drive transistor's grid potential is unstable, and the leakage current is big more, and drive transistor's grid potential is unstable more. The driving current generated by the driving transistor is related to the gate potential of the driving transistor, so that the gate potential of the driving transistor is unstable, the driving current generated by the driving transistor is unstable, and the light-emitting brightness of the light-emitting device is related to the magnitude of the driving current, so that the light-emitting brightness of the light-emitting device changes along with the magnitude of the driving current in the light-emitting stage, which causes poor display uniformity and influences display image quality.
Based on the above problem, the embodiment of the present invention provides a pixel circuit, fig. 1 is the embodiment of the present invention provides a structural schematic diagram of a pixel circuit, refer to fig. 1, this pixel circuit includes: the driving transistor T1 and the at least one leakage suppression module 10 are connected, a first end of the leakage suppression module 10 is connected to a drain of the driving transistor T1 or a first end of the leakage suppression module 10 is connected to a signal line, and a second end of the leakage suppression module 10 is electrically connected to a gate of the driving transistor T1.
The leakage suppression module 10 includes at least two first transistors connected in series, at least one first transistor in the leakage suppression module 10 is a dual-gate transistor, a gate of the first transistor is used as a control end of the leakage suppression module 10 to access the control signal Ctrl, a gate of the dual-gate transistor includes a top gate and a bottom gate, and the top gate and the bottom gate are accessed to the same control signal Ctrl.
Fig. 1 exemplarily shows a case where the leakage current suppressing module 10 includes two first transistors connected in series, and shows a case where one of the first transistors is a double-gate transistor. Referring to fig. 1, the leakage suppression module 10 includes a first transistor T2_1 and a second transistor T2_2 connected in series, where the first transistor T2_1 is a double-gate transistor including a top gate G1 and a bottom gate G2; the top gate G1 and the bottom gate G2 are connected to the control signal Ctrl, and the gate of the first transistor two T2_2 is connected to the control signal Ctrl. The first terminal of the leakage suppression module 10 is connected to an input signal IN, when the first terminal of the leakage suppression module 10 is connected to the drain of the driving transistor T1, the input signal IN may be an output signal of the drain of the driving transistor T1 IN the pixel circuit, and when the first terminal of the leakage suppression module 10 is connected to a signal line, the input signal IN may be a signal output on the signal line connected to the first terminal of the leakage suppression module 10, which is not limited IN this embodiment.
Since the stability of the gate potential of the driving transistor T1 will directly affect the luminance of the OLED, and the leakage of the switching transistor electrically connected to the gate of the driving transistor T1 will affect the stability of the gate potential of the driving transistor, in order to ensure the stability of the gate potential of the driving transistor T1, by providing the leakage suppression module 10 at the gate of the driving transistor T1, and providing the leakage suppression module 10 to include at least two first transistors connected in series, and at least one of the first transistors is a dual-gate transistor including a top gate and a bottom gate, compared with a conventional single-gate transistor, the dual-gate transistor has a better gate control characteristic, so that the leakage of the leakage suppression module 10 itself can be effectively reduced, and the stability of the gate potential of the driving transistor can be ensured. The top gate and the bottom gate of the double-gate transistor are connected with the same control signal, so that the double-gate transistor can be completely switched off from the top gate and the bottom gate when the double-gate transistor is switched off, the electric leakage of the electric leakage suppression module is further reduced, and the display image quality is improved.
Fig. 2 is a schematic cross-sectional view of a double gate transistor provided in an embodiment of the present invention. Alternatively, referring to fig. 2, the active layer PSI of the double gate transistor is located between the top gate G1 and the bottom gate G2;
preferably, the vertical projection of the top gate G1 on the active layer PSI covers the channel region of the double-gate transistor;
preferably, the vertical projection of the bottom gate G2 on the active layer PSI covers the channel region of the double gate transistor.
Wherein the channel region is located between the Source region Source and the Drain region Drain. The channel region of the double-gate transistor is covered by the vertical projection of the top gate G1 on the active layer PSI, the channel region of the double-gate transistor is covered by the vertical projection of the bottom gate G2 on the active layer PSI, light can be prevented from irradiating the channel region of the double-gate transistor from the top gate side and the bottom gate side, the self leakage of the driving transistor is reduced, and the driving capability of the driving transistor is guaranteed.
With continued reference to fig. 2, the double gate transistor further comprises a first gate insulating layer GI1 and a second gate insulating layer GI2, the first gate insulating layer GI1 being located between the top gate G1 and the active layer PSI; the second gate insulating layer GI2 is located between the bottom gate G2 and the active layer PSI.
With continued reference to fig. 2, the channel region of the double-gate transistor optionally has a width h1 of 1-1.5 microns.
Wherein the channel width of a conventional double-gate transistor is typically 2-3 microns, and referring to fig. 2, the channel region width h1 of the double-gate transistor in the present application may be 1-1.5 microns. Compared with the conventional double-gate transistor, under the condition of keeping the driving capability unchanged, the self leakage of the driving transistor can be further reduced by reducing the width of the channel region of the double-gate transistor, and the driving capability of the driving transistor is improved.
Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Optionally, the first transistors are both double-gate transistors.
Referring to fig. 3, the leakage suppression module 10 includes a first transistor T2_1 and a second transistor T2_2 connected in series, and the first transistor T2_1 and the second transistor T2_2 are double-gate transistors. If the conditions allow, the leakage suppression module 10 includes a larger number of double-gate transistors, and thus has smaller leakage. For example, by providing the leakage suppressing module 10 with two series-connected dual-gate transistors, the leakage of the leakage suppressing module 10 can be reduced more than when the leakage suppressing module 10 includes only one dual-gate transistor, and the stability of the gate potential of the driving transistor T1 can be improved. Moreover, the leakage suppression module 10 includes two first transistors connected in series, so that the number of transistors included in the leakage suppression module 10 is not too large, and thus the number of devices in the pixel circuit is ensured to be small, which is beneficial to improving the pixel density.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Alternatively, referring to fig. 4, the pixel circuit includes a first leakage suppression module 11 electrically connected to the gate of the driving transistor T1, a control terminal of the first leakage suppression module 11 is electrically connected to the first Scan signal line Scan _1, a first terminal of the first leakage suppression module 11 is electrically connected to the data voltage signal line Vdata, and a second terminal of the first leakage suppression module 11 is electrically connected to the gate M of the driving transistor T1.
In this embodiment, the first leakage suppression module 11 is used as a data writing module in the pixel circuit, and fig. 4 schematically illustrates a case where the first leakage suppression module 11 includes two first transistors (a first transistor T2_1 and a second transistor T2_2, respectively) connected in series, and both the two transistors are double-gate transistors including a top-gate structure and a bottom-gate structure. Alternatively, referring to fig. 4, the pixel circuit further includes a memory block 20, and the memory block 20 is used for storing the gate potential of the driving transistor T1. The storage module 20 may be a storage capacitor Cst.
Fig. 5 is a timing diagram of driving a pixel circuit according to an embodiment of the present invention, where the timing diagram is suitable for driving the pixel circuit shown in fig. 4. In other optional embodiments of the present invention, the transistors included in the pixel circuit may also be N-type transistors, and this embodiment is not limited in this embodiment. Referring to fig. 4 and 5, the operation of the pixel circuit includes a data writing phase t11 and a light emitting phase t 12.
In the data writing phase T11, the first Scan signal line Scan _1 inputs a low level signal, the first transistor T2_1 and the first transistor T2_2 are turned on, and the data voltage is written to the gate M of the driving transistor T1 and the memory module 20 through the first leakage suppressing module 11 (the first transistor T2_1 and the first transistor T2_ 2).
In the light emitting period T12, due to the memory retention of the memory module 20, the gate voltage of the driving transistor T1 can still retain the data voltage, so that the driving transistor T1 is in a conducting state, and the driving current enters the light emitting device OLED through the driving transistor to drive the light emitting device OLED to emit light. In the light emitting period T12, the first Scan signal line Scan _1 inputs a high level signal, the first transistor T2_1 and the first transistor T2_2 are turned off, and since the first transistor T2_1 and the first transistor T2_2 are dual-gate transistors having a top-gate structure and a bottom-gate structure, and the same first Scan signal is input to the top gate and the bottom gate of each dual-gate structure, the dual-gate transistors can be completely turned off when turned off, and the leakage current of the dual-gate transistors is ensured to be small, so that the potential of the gate of the driving transistor T1 in the light emitting period T12 can be well maintained.
Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Optionally, referring to fig. 6, the pixel circuit further includes a second leakage suppression module 12, wherein a control terminal of the second leakage suppression module 12 is electrically connected to the second Scan signal line Scan _2, a first terminal of the second leakage suppression module 12 is electrically connected to the initialization voltage signal line Vref, and a second terminal of the second leakage suppression module 12 is electrically connected to the gate of the driving transistor T1.
In the present embodiment, the second leakage suppression module 12 is used as a gate initialization module for initializing the gate of the driving transistor T1 in the pixel circuit, and fig. 6 schematically illustrates a case where the second leakage suppression module 12 includes two second transistors (a first transistor three T6_1 and a first transistor four T6_2, respectively) connected in series, and both the two transistors are double-gate transistors including a top-gate structure and a bottom-gate structure.
Fig. 7 is a timing diagram of another pixel circuit according to an embodiment of the present invention, and the timing diagram is suitable for driving the pixel circuit shown in fig. 6. Wherein each transistor in the pixel circuit may be a P-type transistor or an N-type transistor, and fig. 6 schematically illustrates a case where each transistor is a P-type transistor. Referring to fig. 6 and 7, the operation process of the pixel circuit includes an initialization phase t10, a data writing phase t11, and a light emitting phase t 12.
In the initialization stage T10, a high-level signal is input to the first Scan signal line Scan _1, the first leakage suppression module 11 is not turned on, a low-level signal is input to the second Scan signal line Scan _2, the second leakage suppression module 12 is turned on, and the initialization voltage input by the initialization voltage signal line Vref is written into the gates of the memory module 20 and the driving transistor T1 through the second leakage suppression module 12, so that the gate of the driving transistor T1 is initialized. The operation of the pixel circuit data writing stage t11 and the light emitting stage t12 is the same as the operation of the pixel circuit shown in fig. 4, and will not be described herein again.
Since the second leakage suppression block 12 includes the double-gate transistor, the leakage current of the second leakage suppression block 12 itself is small, and the influence of the initialization voltage signal line Vref on the potential of the gate of the driving transistor T1 is small even at a low refresh frequency.
Fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Alternatively, referring to fig. 8, the pixel circuit further includes a data writing module 30 and a light emitting control module 40, and the pixel circuit includes a first leakage current suppressing module 11 electrically connected to the gate of the driving transistor T1;
a control end of the data writing module 30 is electrically connected to the first Scan signal line Scan _1, a first end of the data writing module 30 is electrically connected to the data voltage signal line Vdata, and a second end of the data writing module 30 is electrically connected to the source electrode of the driving transistor T1;
the control end of the first leakage suppression module 11 is electrically connected to the first Scan signal line Scan _1, the first end of the first leakage suppression module 11 is electrically connected to the drain of the driving transistor T1, and the second end of the first leakage suppression module 11 is electrically connected to the gate M of the driving transistor T1;
the light emission control module 40 is connected in series with the driving transistor T1 and the light emitting device OLED between the first power voltage signal line VDD and the second power voltage signal line VSS for controlling a connection state of the source of the driving transistor T1 and the first power voltage signal line VDD and a connection state of the drain of the driving transistor T1 and the second power voltage signal line VSS.
The data writing module 30 includes a second transistor T3, a gate of the second transistor T3 is electrically connected to the first Scan signal line Scan _1, a first pole of the second transistor T3 is electrically connected to the data voltage signal line Vdata, and a second pole of the second transistor T3 is electrically connected to the source of the driving transistor T1;
wherein, the light emitting control module 40 includes a first light emitting control unit 41 and a second light emitting control unit 42, the first light emitting control unit 41 being connected between the first power voltage signal line VDD and the source of the driving transistor T1; the second light emission control unit 42 is connected between the drain of the driving transistor T1 and the second power supply voltage signal line VSS; the control end of the first light emission control unit 41 and the control end of the second light emission control unit 42 are both electrically connected to the light emission control signal line Em. The first light emission control unit 41 includes a third transistor T4, a first pole of the third transistor T4 is connected to the first power voltage signal line VDD, a second pole of the third transistor T4 is connected to the source of the driving transistor T1, and a gate of the third transistor T4 is electrically connected to the light emission control signal line Em; the second light emission control unit 42 includes a fourth transistor T5, a first pole of the fourth transistor T5 is connected to the second pole of the driving transistor T1, a second terminal of the fourth transistor T5 is electrically connected to the first pole (which may be an anode) of the light emitting device OLED, a second pole (which may be a cathode) of the light emitting device OLED is connected to the second power voltage signal line VSS, and a gate of the fourth transistor T5 is electrically connected to the light emission control signal line Em. In this embodiment, the first leakage current suppressing module 11 is used as a threshold compensation module in the pixel circuit.
Fig. 9 is a timing diagram of another pixel circuit according to an embodiment of the present invention, and the timing diagram is suitable for driving the pixel circuit shown in fig. 8. Here, each transistor in the pixel circuit may be a P-type transistor or an N-type transistor, and fig. 8 illustrates that each transistor in the pixel circuit is a P-type transistor as an example. Referring to fig. 8 and 9, the operation of the pixel circuit includes a data writing phase t21 and a light emitting phase t 22.
In the data writing phase T21, the first Scan signal line Scan _1 inputs a low-level signal, the first leakage suppression module 11 (the first transistor T2_1 and the first transistor T2_2) and the data writing module 30 (the second transistor T3) are turned on, and the data voltage input by the data voltage signal line Vdata is written into the gates M of the memory module 20 and the driving transistor T1 through the data writing module 30, the driving transistor T1, and the first leakage suppression module 11.
In the light emitting period T22, the low potential signal is input to the light emitting control signal line Em, the first light emitting control unit 41 and the second light emitting control unit 42 are turned on, and the driving transistor T1 drives the OLED to emit light. In the light emitting period T22, the first Scan signal line Scan _1 inputs a high level signal, the first transistor T2_1 and the first transistor T2_2 are turned off, and since the first transistor T2_1 and the first transistor T2_2 are dual-gate transistors having a top-gate structure and a bottom-gate structure, and the same first Scan signal is input to the top gate and the bottom gate of each dual-gate structure, the dual-gate transistors can be completely turned off when turned off, the leakage current of the dual-gate transistors is ensured to be small, so that the potential of the gate of the driving transistor T1 in the light emitting period T22 can be well maintained.
Fig. 10 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, referring to fig. 10, optionally, the pixel circuit further includes a second leakage suppression module 12, wherein a control end of the second leakage suppression module 12 is electrically connected to the second Scan signal line Scan _2, a first end of the second leakage suppression module 12 is electrically connected to the initialization voltage signal line Vref, and a second end of the second leakage suppression module 12 is electrically connected to the gate of the driving transistor T1.
In this embodiment, the second leakage suppression module 12 is a gate initialization module that initializes the gate of the driving transistor T1. Fig. 10 schematically shows a case where the second leakage suppression module 12 includes two second transistors (a first transistor three T6_1 and a first transistor four T6_2, respectively) connected in series, and both of the two transistors are double-gate transistors including a top-gate and a bottom-gate structure. When the pixel circuit shown in fig. 10 is driven, the operation process of the pixel circuit includes a first initialization stage before the data writing stage, in which the second leakage suppression module is controlled to be turned on by the second Scan signal line Scan _2, the initialization voltage input by the initialization voltage signal line Vref is transmitted to the gate of the driving transistor, and the gate of the driving transistor T1 is initialized. Since the second leakage suppression block 12 includes the double-gate transistor, the leakage current of the second leakage suppression block 12 itself is small, and the influence of the initialization voltage input terminal Vref on the potential of the gate of the driving transistor T1 is small even at a low refresh frequency.
With continued reference to fig. 10, the pixel circuit further includes an anode reset module 50, wherein a control terminal of the anode reset module 50 is electrically connected to the third Scan signal line Scan _3, a first terminal of the anode reset module 50 is electrically connected to the initialization voltage signal line Vref, and a second terminal of the anode reset module 50 is electrically connected to the anode of the light emitting device OLED.
The anode reset module 50 includes a fifth transistor T7, a first electrode of the fifth transistor T7 is electrically connected to the initialization voltage signal line Vref, a second electrode of the fifth transistor T7 is electrically connected to the anode of the light emitting device OLED, and a gate of the fifth transistor T7 is electrically connected to the third Scan signal line Scan _ 3.
With continued reference to fig. 10, the pixel circuit further includes a memory block 20, and the memory block 20 is used to store the gate potential of the driving transistor T1.
Fig. 11 is a timing diagram of driving a pixel circuit according to an embodiment of the present invention, where the timing diagram is suitable for driving the pixel circuit shown in fig. 10. Here, each transistor in the pixel circuit may be a P-type transistor or an N-type transistor, and fig. 10 illustrates that each transistor in the pixel circuit is a P-type transistor as an example. Referring to fig. 10 and 11, the operation process of the pixel circuit includes a first initialization phase t31, a data writing phase t32, a second initialization phase t33, and a light emitting phase t 34.
In the first initialization stage T31, a high-level signal is input to the first Scan signal line Scan _1 and the third Scan signal line Scan _3, the first leakage suppression module 11 (the first transistor T2_1 and the first transistor T2_2) and the anode reset module 50 (the seventh transistor T7) are not turned on, a low-level signal is input to the second Scan signal line Scan _2, the second leakage suppression module 12 (the first transistor third T6_1 and the first transistor fourth T6_2) is turned on, and the initialization voltage is written to the gates M of the memory module 20 and the driving transistor T1 through the second leakage suppression module 12, so that the gate of the driving transistor T1 is initialized.
In the data writing phase T32, the first Scan signal line Scan _1 inputs a low-level signal, the first leakage suppression module 11 and the data writing module 20 are turned on, the second Scan signal line Scan _2 inputs a high-level signal, the second leakage suppression module 12 is turned off, and the data voltage input by the data voltage signal line Vdata is written into the memory module 20 and the gate M of the driving transistor through the data writing module 30 (the second transistor T3), the driving transistor T1, and the first leakage suppression module 11.
In the second initialization period t33, the third Scan signal line Scan _3 inputs a low-potential signal, the anode reset module 50 is turned on, and the initialization voltage is input to the anode of the light emitting device OLED through the anode reset module 50 to reset the anode of the OLED.
In the light emitting period T34, the low potential signal is input to the light emitting control signal line Em, the first light emitting control unit 41 and the second light emitting control unit 42 are turned on, and the driving transistor T1 drives the light emitting device OLED to emit light.
It should be noted that, in the above embodiments of the present invention, in the pixel circuit shown in fig. 6, it is optional that each transistor is a low-temperature polysilicon transistor, and each transistor is a P-type transistor, and then the signals accessed by the first scanning signal line and the second scanning signal line in the pixel circuit are provided by the same scanning driving circuit, and there is no need to additionally provide a scanning driving circuit corresponding to the N-type transistor, thereby being beneficial to the realization of a narrow frame. In addition, in two adjacent rows of pixel circuits in the selectable display panel, the first scanning signal line of the previous row of pixel circuits and the second scanning signal line of the next row of pixel circuits can be the same scanning line, so that the number of scanning lines in the display panel is reduced, and the simplification of wiring is facilitated. For the pixel circuit shown in fig. 10, each transistor may also be a P-type low temperature polysilicon transistor, so as to ensure that the scanning signals input by the first scanning signal line, the second scanning signal line and the third scanning signal line can be provided by the same scanning driving circuit. Optionally, for three adjacent rows of pixel circuits, the second scanning signal line of the first row of pixel circuits, the first scanning signal line of the second row of pixel circuits, and the third scanning signal line of the third row of pixel circuits may be the same scanning line, thereby reducing the number of signal lines.
The embodiment of the utility model provides a still provide a display panel, this display panel adopts the utility model discloses arbitrary embodiment pixel circuit.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A pixel circuit, comprising: the first end of the electric leakage suppression module is connected with the drain electrode of the driving transistor or the first end of the electric leakage suppression module is connected with a signal wire, and the second end of the electric leakage suppression module is electrically connected with the grid electrode of the driving transistor;
the leakage suppression module comprises at least two first transistors which are connected in series, wherein at least one first transistor in the leakage suppression module is a double-gate transistor, the grid electrode of the first transistor is used as the control end of the leakage suppression module to access a control signal, the grid electrode of the double-gate transistor comprises a top gate and a bottom gate, and the top gate and the bottom gate access the same control signal.
2. The pixel circuit of claim 1, wherein an active layer of the double gate transistor is located between the top gate and the bottom gate;
the vertical projection of the top gate on the active layer covers the channel region of the double-gate transistor;
and the vertical projection of the bottom gate on the active layer covers the channel region of the double-gate transistor.
3. The pixel circuit of claim 1, wherein the width of the channel region of the double gate transistor is 1-1.5 microns.
4. The pixel circuit according to claim 1, wherein the first transistors are double-gate transistors.
5. The pixel circuit according to claim 1, wherein the pixel circuit comprises a first leakage suppression module electrically connected to the gate of the driving transistor, a control terminal of the first leakage suppression module is electrically connected to a first scan signal input terminal, a first terminal of the first leakage suppression module is electrically connected to a data voltage signal line, and a second terminal of the first leakage suppression module is electrically connected to the gate of the driving transistor.
6. The pixel circuit according to claim 1, further comprising a data writing module and a light emitting control module, wherein the pixel circuit comprises a first leakage current suppressing module electrically connected to the gate of the driving transistor;
the control end of the data writing module is electrically connected with a first scanning signal line, the first end of the data writing module is electrically connected with a data voltage signal line, and the second end of the data writing module is electrically connected with the source electrode of the driving transistor;
the control end of the first leakage suppression module is electrically connected with the first scanning signal line, the first end of the first leakage suppression module is electrically connected with the drain electrode of the driving transistor, and the second end of the first leakage suppression module is electrically connected with the grid electrode of the driving transistor;
the light-emitting control module, the driving transistor and the light-emitting device are connected in series between a first power supply voltage signal line and a second power supply voltage signal line and used for controlling the connection state of the source electrode of the driving transistor and the first power supply voltage signal line and the connection state of the drain electrode of the driving transistor and the second power supply voltage signal line.
7. The pixel circuit according to claim 5 or 6, further comprising a second leakage suppression module, wherein a control terminal of the second leakage suppression module is electrically connected to a second scan signal line, a first terminal of the second leakage suppression module is electrically connected to an initialization voltage signal line, and a second terminal of the second leakage suppression module is electrically connected to the gate of the driving transistor.
8. The pixel circuit according to claim 5 or 6, further comprising an anode reset module, wherein a control terminal of the anode reset module is electrically connected to the third scan signal line, a first terminal of the anode reset module is electrically connected to the initialization voltage signal line, and a second terminal of the anode reset module is electrically connected to an anode of the light emitting device.
9. The pixel circuit according to any one of claims 1 to 6, further comprising a storage block for storing a gate potential of the driving transistor.
10. A display panel comprising the pixel circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120663128.1U CN214671744U (en) | 2021-03-31 | 2021-03-31 | Pixel circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120663128.1U CN214671744U (en) | 2021-03-31 | 2021-03-31 | Pixel circuit and display panel |
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| CN214671744U true CN214671744U (en) | 2021-11-09 |
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| CN114038409A (en) * | 2021-11-24 | 2022-02-11 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit and display panel |
| CN114120909A (en) * | 2021-12-07 | 2022-03-01 | 云谷（固安）科技有限公司 | Pixel circuit and display panel |
| CN114120907A (en) * | 2021-12-02 | 2022-03-01 | 合肥维信诺科技有限公司 | Pixel circuit, display device and driving method thereof |
| CN114758604A (en) * | 2022-05-10 | 2022-07-15 | 武汉天马微电子有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN114937436A (en) * | 2022-06-30 | 2022-08-23 | 天马微电子股份有限公司 | Display panel and display device |
| WO2024113225A1 (en) * | 2022-11-30 | 2024-06-06 | 京东方科技集团股份有限公司 | Pixel circuit, display device, and driving method |
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| CN114038409A (en) * | 2021-11-24 | 2022-02-11 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit and display panel |
| WO2023092616A1 (en) * | 2021-11-24 | 2023-06-01 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit and display panel |
| US12106701B2 (en) | 2021-11-24 | 2024-10-01 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Pixel circuit and display panel |
| CN114120907A (en) * | 2021-12-02 | 2022-03-01 | 合肥维信诺科技有限公司 | Pixel circuit, display device and driving method thereof |
| CN114120909A (en) * | 2021-12-07 | 2022-03-01 | 云谷（固安）科技有限公司 | Pixel circuit and display panel |
| CN114120909B (en) * | 2021-12-07 | 2023-02-10 | 云谷（固安）科技有限公司 | Pixel circuit and display panel |
| CN114758604A (en) * | 2022-05-10 | 2022-07-15 | 武汉天马微电子有限公司 | Pixel driving circuit, driving method thereof, display panel and display device |
| CN114937436A (en) * | 2022-06-30 | 2022-08-23 | 天马微电子股份有限公司 | Display panel and display device |
| WO2024113225A1 (en) * | 2022-11-30 | 2024-06-06 | 京东方科技集团股份有限公司 | Pixel circuit, display device, and driving method |
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