CN214477436U - Double-transistor thermoelectric separation packaging structure - Google Patents
Double-transistor thermoelectric separation packaging structure Download PDFInfo
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- CN214477436U CN214477436U CN202120247917.7U CN202120247917U CN214477436U CN 214477436 U CN214477436 U CN 214477436U CN 202120247917 U CN202120247917 U CN 202120247917U CN 214477436 U CN214477436 U CN 214477436U
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- 238000000926 separation method Methods 0.000 title claims abstract description 17
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical group 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
A dual-transistor thermoelectric separation packaging structure comprises a substrate, a first conductive part, a second conductive part, a third conductive part and a fourth conductive part, wherein the substrate is provided with a first contact and a drain output contact, the second conductive part is provided with a second contact and a source output contact, the third conductive part is provided with a third contact and a grid output contact, and the fourth conductive part is provided with a fourth contact. A first transistor has a drain connected to the first contact, a gate connected to the second contact, and a source connected to the fourth contact. A second transistor has a source connected to the second contact, a gate connected to the third contact, and a drain connected to the fourth contact. The substrate is provided with a through hole corresponding to the first transistor or the second transistor, and the heat sink extends into the through hole and contacts with the first transistor or the second transistor. The utility model discloses utilize the fin to derive the produced heat of transistor during operation, avoid the wire to generate heat and influence the working efficiency of transistor.
Description
Technical Field
The present invention relates to a semiconductor device package, and more particularly to a dual transistor package.
Background
Semiconductor devices are widely used in modern science and technology, and various electronic devices are all operated by using semiconductor devices. The internal structure of a semiconductor device, such as that disclosed in the utility model patent M511679, includes one or more transistors disposed on a substrate, each transistor having its drain, gate and source electrically connected to the leads of the substrate through wires to form a package structure. The transistor generates heat during operation, and the heat is transmitted through the metal wire and the pin with high heat conductivity, so that the temperature of the metal wire and the pin is increased. However, the temperature rise of the metal wires and the pins as electrically conductive members will cause the operation performance of the transistor to be drastically reduced.
In another semiconductor device, as disclosed in patent I69869, a heat dissipation plate is disposed under the substrate to dissipate heat and reduce temperature, thereby maintaining the normal operation performance of the transistor. In the conventional structure, although the heat dissipation backplate can assist in heat dissipation, the heat generated by the transistor still needs to be transferred to the substrate through the metal wires and the pins before being conducted out through the heat dissipation backplate, so that the temperature of the metal wires and the pins is still high, and the working performance of the transistor is still affected.
Therefore, how to improve the above problems is the primary subject to be solved by the present invention.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide a dual-transistor thermoelectric separation package structure, which utilizes the heat sink to conduct the heat generated by the transistor during operation, thereby avoiding the heat generated by the wire from affecting the performance of the transistor.
To achieve the aforesaid objective, the present invention provides a dual-transistor thermoelectric separation package structure, which comprises:
a substrate defined with a front surface and a back surface;
a first conductive part arranged in the substrate, wherein one end of the first conductive part extends to the front side to form a first contact, and the other end of the first conductive part extends to the back side to form a drain output contact;
a second conductive part arranged in the substrate, wherein one end of the second conductive part extends to the front surface to form a second contact, and the other end of the second conductive part extends to the back surface to form a source electrode output contact;
a third conductive part arranged in the substrate, wherein one end of the third conductive part extends to the front surface to form a third contact, and the other end of the third conductive part extends to the back surface to form a grid output contact;
a fourth conductive part arranged on the front surface of the substrate and provided with a fourth contact;
a first transistor having a first drain, a first gate and a first source, wherein the first drain is connected to the first contact, the first gate is connected to the second contact, and the first source is connected to the fourth contact;
a second transistor having a second drain, a second gate and a second source, wherein the second source is connected to the second contact, the second gate is connected to the third contact, and the second drain is connected to the fourth contact;
a heat sink disposed on the back of the substrate, wherein the substrate has a through hole corresponding to the first or second transistor, and the heat sink extends into the through hole and contacts with the first or second transistor.
Preferably, the first transistor is a gan hemt, the first drain is connected to the first contact by a wire, the first gate is connected to the second contact by a wire, and the first source is connected to the fourth contact by a wire. The GaN HEMT comprises a first GaN narrow band gap layer, an AlGaN wide band gap layer, a second GaN narrow band gap layer, a buffer layer, a base layer and a back-plated metal layer stacked in sequence.
Furthermore, the through hole is disposed on the substrate at a position corresponding to the first transistor.
Preferably, the second transistor is a metal oxide semiconductor field effect transistor, the second drain is directly connected to the fourth contact, the second source is connected to the second contact by a wire, and the second gate is connected to the third contact by a wire.
Preferably, the first transistor and the second transistor are respectively sealed by a packaging adhesive.
Preferably, the distance between the source output contact and the drain output contact is greater than 1mm, the distance between the gate output contact and the drain output contact is greater than 1mm, and the distance between the heat sink and the drain output contact is greater than 0.5 mm.
The utility model has the advantages that:
the utility model provides a two electric crystal thermoelectric separation packaging structure, it utilizes the produced heat of fin derivation electric crystal during operation, avoids the wire to generate heat and influences electric crystal's work efficiency.
The above objects and advantages of the present invention will be readily understood by the following detailed description of the selected embodiments and the accompanying drawings.
Drawings
Fig. 1 is a schematic plan view of the present invention;
FIG. 2 is a schematic cross-sectional view taken along the line A-A in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along the line B-B in FIG. 2;
fig. 4 is a schematic diagram of a structure of a gan hemt of the present invention.
Detailed Description
Referring to fig. 1 to 3, a dual-transistor thermoelectric separation package structure according to the present invention includes a substrate 1 made of aluminum nitride, aluminum oxide, resin (BT), epoxy resin molding plastic (EMC) or epoxy glass fiber cloth coated copper foil (FR-4). The substrate 1 has a front surface 11 and a back surface 12, the substrate 1 is provided with a first through hole 13, a second through hole 14 and a third through hole 15 penetrating from the front surface 11 to the back surface 12, and is respectively provided with a first conductive part 21, a second conductive part 22 and a third conductive part 23 by conductive materials, wherein one end of the first conductive part 21 extends to the front surface 11 of the substrate 1 to form a first contact 211, and the other end extends to the back surface 12 of the substrate 1 to form a drain output contact 212; one end of the second conductive part 22 extends to the front surface 11 of the substrate 1 to form a second contact 221, and the other end extends to the back surface 12 of the substrate 1 to form a source output contact 222; one end of the third conductive part 23 extends to the front surface 11 of the substrate 1 to form a third contact 231, and the other end extends to the back surface 12 of the substrate 1 to form a gate output contact 232. The front surface 11 of the substrate 1 is further laid with a fourth conductive portion 24 having a fourth contact 241.
Since the transistor operates with a high voltage at the drain output contact 212, in order to avoid affecting the transistor's performance, the distance D2 between the source output contact 222 and the drain output contact 212 is greater than 1mm, and the distance D3 between the gate output contact 232 and the drain output contact 212 is greater than 1 mm.
A first transistor 3 and a second transistor 4 are disposed on the front surface 11 of the substrate 1, and then sealed by a packaging adhesive 17, wherein the packaging adhesive 17 can be black silica gel or black epoxy resin. In this embodiment, the first transistor 3 is further defined as a gallium nitride high electron mobility transistor (GaN HEMT), and the second transistor 4 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As shown in fig. 4, the gan hemt includes a first gan narrow band gap layer 34, an algan wide band gap layer 35, a second gan narrow band gap layer 36, a buffer layer 37, a base layer 38 and a back metal layer 39 stacked in sequence, wherein the back metal layer 39 can reflect light so as to prevent the operational performance of the hemt from being affected.
The first transistor 3 has a first drain 31, a first gate 32 and a first source 33, wherein the first drain 31 is connected to the first contact 211 by a conductive wire 61, the first gate 32 is connected to the second contact 221 by a conductive wire 62, and the first source 33 is connected to the fourth contact 241 by a conductive wire 63. The second transistor 4 has a second drain 41, a second gate 42 and a second source 43, wherein the second drain 41 is located at the bottom of the second transistor 4 and directly connected to the fourth contact 241, the second source 43 is connected to the second contact 221 by a conducting wire 64, and the second gate 42 is connected to the third contact 231 by a conducting wire 65.
The substrate 1 is provided with a fourth through hole 16, wherein in the present embodiment, the position of the fourth through hole 16 corresponds to the first transistor 3. The back surface 12 of the substrate 1 is provided with a heat sink 5, and the heat sink 5 simultaneously extends into the fourth through hole 16 and contacts the first transistor 3 to conduct heat away from the first transistor 3. The distance between the heat sink 5 and the drain output contact 212 is larger than 0.5mm to prevent the operation performance of the transistor from being affected by overheating.
In another embodiment, the position of the fourth through hole corresponds to the second transistor, and the heat sink contacts the second transistor when extending into the fourth through hole, so as to conduct heat away from the second transistor.
Through the structure, the utility model discloses in the time of the in-service use, the produced heat of this first transistor 3 or this second transistor 4 can be directly derived via the fin 5 rather than the contact, and produce direct and huge effect to the cooling of this first transistor 3 or this second transistor 4, and then be used for electrically conductive metal wire or pin etc. on this first transistor 3 or this second transistor 4, its temperature can be at too high state by effective control, form the effect of electrothermal separation, reposition of redundant personnel in view of the above, in order to ensure that the working efficiency of transistor is not influenced by high temperature.
The above embodiments are only for illustrating the present invention, and are not to be construed as limiting the present invention, and the replacement of equivalent elements should be considered within the scope of the present invention.
From the above, it will be apparent to those skilled in the art that the present invention can achieve the above objects, and the present invention is in accordance with the provisions of the patent statutes and is filed by the following claims.
Claims (9)
1. A dual-transistor thermoelectric separation package structure is characterized by comprising:
a substrate defined with a front surface and a back surface;
a first conductive part arranged in the substrate, wherein one end of the first conductive part extends to the front side to form a first contact, and the other end of the first conductive part extends to the back side to form a drain output contact;
a second conductive part arranged in the substrate, wherein one end of the second conductive part extends to the front surface to form a second contact, and the other end of the second conductive part extends to the back surface to form a source electrode output contact;
a third conductive part arranged in the substrate, wherein one end of the third conductive part extends to the front surface to form a third contact, and the other end of the third conductive part extends to the back surface to form a grid output contact;
a fourth conductive part arranged on the front surface of the substrate and provided with a fourth contact;
a first transistor having a first drain, a first gate and a first source, wherein the first drain is connected to the first contact, the first gate is connected to the second contact, and the first source is connected to the fourth contact;
a second transistor having a second drain, a second gate and a second source, wherein the second source is connected to the second contact, the second gate is connected to the third contact, and the second drain is connected to the fourth contact;
a heat sink disposed on the back of the substrate, wherein the substrate has a through hole corresponding to the first or second transistor, and the heat sink extends into the through hole and contacts with the first or second transistor.
2. The dual-transistor thermoelectric separation package of claim 1, wherein the first transistor is a gan hemt, the first drain is connected to the first contact by a wire, the first gate is connected to the second contact by a wire, and the first source is connected to the fourth contact by a wire.
3. The dual-transistor thermoelectric separation package structure of claim 2, wherein the GaN HEMT comprises a first GaN narrow band gap layer, an AlGaN wide band gap layer, a second GaN narrow band gap layer, a buffer layer, a base layer, and a back-metal layer stacked in sequence.
4. The dual-transistor thermoelectric separation package structure of claim 2, wherein the through hole is formed in the substrate at a position corresponding to the first transistor.
5. The dual transistor thermoelectric separation package of claim 3 wherein the second transistor is a MOSFET, the second drain is directly connected to the fourth contact, the second source is connected to the second contact by a wire, and the second gate is connected to the third contact by a wire.
6. The dual-transistor thermoelectric separation package structure of claim 1, wherein the first transistor and the second transistor are each encapsulated by an encapsulant.
7. The dual-transistor thermoelectric separation package of claim 1, wherein the distance between the source output contact and the drain output contact is greater than 1 mm.
8. The dual-transistor thermoelectric separation package of claim 1, wherein the gate output contact is spaced from the drain output contact by a distance greater than 1 mm.
9. The dual-transistor thermoelectric separation package of claim 1 wherein the distance between the heat sink and the drain output contact is greater than 0.5 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120247917.7U CN214477436U (en) | 2021-01-28 | 2021-01-28 | Double-transistor thermoelectric separation packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120247917.7U CN214477436U (en) | 2021-01-28 | 2021-01-28 | Double-transistor thermoelectric separation packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214477436U true CN214477436U (en) | 2021-10-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120247917.7U Expired - Fee Related CN214477436U (en) | 2021-01-28 | 2021-01-28 | Double-transistor thermoelectric separation packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN214477436U (en) |
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2021
- 2021-01-28 CN CN202120247917.7U patent/CN214477436U/en not_active Expired - Fee Related
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Granted publication date: 20211022 |