CN214069906U

CN214069906U - Composite logic gate circuit and mining machine equipment

Info

Publication number: CN214069906U
Application number: CN202120223949.3U
Authority: CN
Inventors: 孔维新; 于东; 田文博; 范志军; 杨作兴
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2021-08-27
Anticipated expiration: 2031-01-26

Abstract

The present disclosure relates to a composite logic gate circuit and mining equipment. The composite logic gate circuit includes: the circuit comprises a simple logic gate circuit, a first PMOS (P-channel metal oxide semiconductor) tube and a first NMOS (N-channel metal oxide semiconductor) tube, wherein the simple logic gate circuit comprises a first logic gate circuit and a phase inverter circuit; the first logic gate circuit is configured to receive a first input signal and a second input signal and output a first output signal, the inverter circuit comprises a second PMOS tube and a second NMOS tube, the source electrode of the second PMOS tube is coupled to the power supply input end, the drain electrode of the second PMOS tube is coupled to the drain electrode of the second NMOS tube, the grid electrode of the second PMOS tube is configured to receive the first output signal, the source electrode of the second PMOS tube is coupled to the ground end, the drain electrode of the first PMOS tube is coupled to the drain electrode of the second PMOS tube, the grid electrode of the first NMOS tube is configured to receive a third input signal, the source electrode of the first NMOS tube is configured to receive the first output signal, the grid electrode of the first NMOS tube is configured to receive the third input signal, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit.

Description

Composite logic gate circuit and mining machine equipment

Technical Field

The present disclosure relates to composite logic gate circuits, AND more particularly to transistor-level based low power consumption AND-XOR (AND exclusive OR) gate circuits AND composite logic gate circuits such as OR-XOR (OR exclusive OR) gate circuits, AND-XNOR (AND OR) gate circuits, OR-XNOR (OR AND OR) gate circuits, AND mining equipment including such composite logic gate circuits.

Background

With the continuous reduction of the process size of integrated circuits and the rapid development of design technology, the integrated circuits are moving towards larger scale and more complex, and power consumption has become one of the serious challenges facing the development of integrated circuits. At present, almost all digital circuit design methods use Boolean (Boolean) logic based on and, or, and not operation sets, which may be referred to as Traditional Boolean (TB) logic. It is believed that part of the challenges faced by today's integrated circuit design are due to the limitations of the traditional boolean logic itself. In practice, the digital circuit may be implemented using conventional Boolean logic based on AND, OR, NOT gates, OR Reed-Muller (RM) logic based on AND-XOR, OR-XOR gates, OR the like.

Compared with the TB logic, the RM logic has the following advantages: (1) implementing logic functions such as arithmetic operations, parity functions, etc. with RM logic is much simpler than TB logic, e.g., for an n-variable parity checker, implementation with TB logic requires 2ⁿOnly n characters are needed by using RM logic, so that the area of a silicon chip is saved, and potential power consumption and speed are achieved; (2) RM logic has good testability; (3) RM logic is easy to map to a Field Programmable Gate Array (FPGA) since in an FPGA (e.g. a look-up table FPGA) the xor gates do not result in additional area increase. AND-XOR gate circuitThe RM composite logic gate circuit is a common RM composite logic gate circuit, can be used for realizing functions of arithmetic operation/parity check and the like, and has the advantages of cost and power consumption compared with the realization of a simple logic gate circuit based on AND, OR and NOT gates.

However, RM logic is not as widely used in the industry as TB logic, and one reason for this is the lack of a low power cell library suitable for RM logic synthesis. In recent years, AND-XOR gates have been studied, but all of them have a structure in which an AND gate AND an XOR/XNOR gate are connected in cascade, AND have problems of large area, high power consumption, AND the like.

It is therefore desirable to propose new transistor-level design based AND-XOR gates AND similar complex logic gates that can reduce cost AND power consumption.

SUMMERY OF THE UTILITY MODEL

According to an aspect of the present disclosure, there is provided a composite logic gate circuit, which may include: the device comprises a simple logic gate circuit, a first PMOS tube and a first NMOS tube; wherein the simple logic gate circuit may include a first logic gate circuit and an inverter circuit, wherein the first logic gate circuit may be configured to receive a first input signal and a second input signal and output a first output signal, wherein the inverter circuit may include a second PMOS transistor and a second NMOS transistor, the second PMOS transistor having a source coupled to a power input terminal, a drain coupled to a drain of the second NMOS transistor, and a gate configured to receive the first output signal, the second NMOS transistor having a source coupled to ground, a drain coupled to a drain of the second PMOS transistor, and a gate configured to receive the first output signal, wherein the first PMOS transistor has a source coupled to the drains of the second PMOS transistor and the second NMOS transistor, a drain coupled to the drain of the first NMOS transistor, and a gate configured to receive a third input signal, wherein the source of the first NMOS transistor is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS transistor, and the gate is configured to receive the third input signal, and wherein the simple logic gate circuit may be an AND gate circuit or an OR gate circuit, and the first logic gate circuit may be an NAND gate circuit or a NOR gate circuit, respectively.

In one embodiment, the composite logic gate circuit further comprises a transmission gate circuit, the transmission gate circuit comprises a third PMOS transistor and a third NMOS transistor, wherein a gate of the third PMOS transistor is coupled to a drain of the second PMOS transistor and a source of the first PMOS transistor, a source of the third PMOS transistor is coupled to a drain of the first PMOS transistor and a drain of the first NMOS transistor, a drain of the third NMOS transistor is coupled to a gate of the first PMOS transistor and a gate of the first NMOS transistor, a gate of the third NMOS transistor is coupled to a source of the first NMOS transistor and configured to receive the first output signal, a source of the third NMOS transistor is coupled to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and a drain of the third NMOS transistor is coupled to a drain of the first PMOS transistor and a drain of the first NMOS transistor.

In one embodiment, the composite logic gate circuit further comprises a second inverter circuit, the second inverter circuit comprises a fourth PMOS transistor and a fourth NMOS transistor, wherein the source of the fourth PMOS transistor is coupled to the power supply input terminal, the drain of the fourth PMOS transistor is coupled to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is coupled to the drains of the first PMOS transistor and the first NMOS transistor, the source of the fourth NMOS transistor is coupled to the ground terminal, the drain of the fourth PMOS transistor is coupled to the drain of the fourth PMOS transistor, and the gate of the fourth NMOS transistor is coupled to the drains of the first PMOS transistor and the first NMOS transistor.

In one embodiment, the first logic gate circuit is a nand gate circuit, the nand gate circuit comprising: a fifth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor and a sixth NMOS transistor, wherein the fifth PMOS transistor has a source coupled to the power input terminal, a drain coupled to the drains of the sixth PMOS transistor and the fifth NMOS transistor, and a gate configured to receive the first input signal, wherein the sixth PMOS transistor has a source coupled to the power input terminal, a drain coupled to the drains of the fifth PMOS transistor and the fifth NMOS transistor, and a gate configured to receive the second input signal, wherein the fifth NMOS transistor has a source coupled to the drain of the sixth NMOS transistor, a drain coupled to the drains of the fifth PMOS transistor and the sixth PMOS transistor, and a gate configured to receive the first input signal, and the sixth NMOS transistor has a source coupled to ground, a drain coupled to the source of the fifth NMOS transistor, and a gate configured to receive the second input signal, wherein the fifth PMOS transistor, the fifth NMOS transistor, the fifth PMOS, the drain, and the gate are coupled to the ground, A node at which drains of the sixth PMOS transistor and the fifth NMOS transistor are coupled to each other is configured to output the first output signal.

In one embodiment, the first logic gate circuit is a nor gate circuit, the nor gate circuit comprising: a seventh PMOS transistor, a seventh NMOS transistor, an eighth PMOS transistor and an eighth NMOS transistor, wherein the source of the seventh PMOS transistor is coupled to the power input terminal, the drain of the seventh PMOS transistor is coupled to the source of the eighth PMOS transistor, and the gate of the eighth PMOS transistor is configured to receive the first input signal, wherein the source of the eighth PMOS transistor is coupled to the drain of the seventh PMOS transistor, the drain of the seventh NMOS transistor is coupled to the drain of the seventh NMOS transistor, and the gate of the eighth NMOS transistor is configured to receive the second input signal, wherein the source of the seventh NMOS transistor is coupled to ground, the drain of the seventh NMOS transistor is coupled to the drain of the eighth PMOS transistor, and the gate of the eighth NMOS transistor is configured to receive the first input signal, wherein the source of the eighth NMOS transistor is coupled to ground, the drain of the seventh NMOS transistor is coupled to the drain of the eighth PMOS transistor, and the gate of the eighth NMOS transistor is configured to receive the second input signal, and wherein the eighth PMOS transistor, A node at which drains of the seventh NMOS transistor and the eighth NMOS transistor are coupled to each other is configured to output the first output signal.

According to another aspect of the disclosure, there is provided a mining apparatus comprising a composite logic gate circuit as described above.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 schematically shows a schematic structure diagram of a conventional transistor-level design-based AND-XOR gate circuit formed by a CMOS AND gate circuit AND a CMOS XOR gate circuit in cascade connection;

FIG. 2 schematically illustrates a schematic diagram of an XOR gate implemented by pass transistor logic;

FIG. 3 schematically illustrates a structural schematic of a composite logic gate circuit based on a transistor level design, according to an embodiment of the disclosure;

FIG. 4 schematically illustrates a structural schematic of a composite logic gate circuit based on a transistor level design, according to another embodiment of the present disclosure;

FIG. 5 schematically illustrates a structural schematic of another complex logic gate circuit based on a transistor level design, according to another embodiment of the present disclosure;

fig. 6A and 6B schematically show structural diagrams of a CMOS nand gate circuit and a CMOS NOR gate circuit, respectively, included in a composite logic gate circuit based on a transistor level design according to an embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosure is not limited to the positions, sizes, ranges, and the like disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the circuits and methods herein are shown by way of example to illustrate different embodiments of the circuits or methods in this disclosure and are not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of exemplary ways in which the present disclosure may be practiced and not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

Fig. 1 schematically shows a schematic structure diagram of a conventional AND-XOR gate 100 based on a transistor-level design AND formed by cascading a CMOS AND gate with a CMOS XOR gate.

In fig. 1, the AND-XOR gate 100 may be implemented as a conventional complementary static CMOS logic gate. The functional expression of the output signal of the AND-XOR gate 100 at the output Y1 may be satisfied

Wherein

Represents an exclusive or.

As shown in fig. 1, the AND-XOR gate 100 may include a NAND gate 110, an INV (inverter) gate 120, AND an XOR gate 130, wherein the NAND gate 110 AND the INV gate 120 may form a cmos AND gate.

The NAND gate 110 may include PMOS transistors P11, P12 and NMOS transistors N11, N12. The NAND gate 110 may receive a first input signal a at gates of a PMOS transistor P11 and an NMOS transistor N11, a second input signal B at gates of a PMOS transistor P12 and an NMOS transistor N12, and a first output signal B at an output terminal Y11 where drains of the PMOS transistors P11, P12 and an NMOS transistor N11 are coupled to each other

The INV gate circuit 120 may include a PMOS transistor P13 and an NMOS transistor N13. The INV gate 120 may receive the first output signal at the gates of the PMOS transistor P13 and the NMOS transistor N13

And outputs the signal AB at the output terminal Y21 where the drains of the PMOS transistor P13 and the NMOS transistor N13 are coupled to each other.

Thus, the NAND gate 110 AND the INV gate 120 may form an AND gate, AND the AND operation value of the input signal is output at the output of the AND gate.

XOR gate 130 may include a NOR gate and an AOI gate. The NOR gate circuit may include PMOS transistors P14, P15 and NMOS transistors N14, N15 receiving an input signal AB at the gates of PMOS transistor P14 and NMOS transistor N14, and an input signal C at the gates of PMOS transistor P15 and NMOS transistor N15. The AOI gate circuit may include PMOS transistors P16, P17 and P18 and NMOS transistors N16, N17 and N18, receives an input signal AB at gates of PMOS transistors P17 and NMOS transistor N17, receives an input signal C at gates of PMOS transistor P18 and NMOS transistor N18, and outputs a signal C at an output terminal Y1

In the AND-XOR gate 100 shown in fig. 1, the transistors are seen as switches controlled by their gate terminal signals. The advantage of the AND-XOR gate 100 formed by a static complementary CMOS gate is that: high noise margin, low output impedance, high input impedance, no static power consumption, etc. However, as can be seen from fig. 1, the AND-XOR gate 100 formed by the static complementary CMOS gate shares 16 transistors, AND the area AND power consumption are still relatively large.

Applicants recognized that XOR gate 130 in the above design consists of a NOR gate + AOI gate, using 10 transistors P14-P18 and N14-N18. The applicant considers that the implementation based on Pass Transistor Logic (PTL) has the advantages of low power consumption and a small number of transistors. In particular, where pass transistor logic is employed, the gate and source/drain terminals are driven with the original input to reduce the number of transistors required. That is, the input signal may not only control the gate terminal of the transistor but also drive the source/drain terminal. In particular, where pass transistor logic is employed, the XOR gate may be implemented with 4 transistors.

Fig. 2 schematically shows a schematic diagram of the structure of an XOR gate circuit 200 implemented by pass transistor logic.

As shown in fig. 2, XOR gate circuit 200 may include PMOS transistors P21, P22 and NMOS transistors N21, N22, wherein PMOS transistor P21 and NMOS transistor N21 may form an inverter circuit. The PMOS transistor P21 has a gate receiving the input signal A, a source coupled to the power input VDD, and a drain coupled to the drain of the NMOS transistor N21. The gate of the NMOS transistor N21 receives the input signal A, the drain is coupled to the drain of the PMOS transistor P21, and the source is coupled to the ground VSS. The source of the PMOS transistor P22 is coupled to the gate of the PMOS transistor P21 and receives the input signal A, the gate is coupled to the gate of the NMOS transistor and receives the input signal B, and the drain is coupled to the drain of the NMOS transistor N22. The gate of the NMOS transistor N22 is coupled to the gate of the PMOS transistor P22 and receives the input signal B, the drain is coupled to the drain of the PMOS transistor P22, and the source is coupled to the drains of the NMOS transistor N21 and the PMOS transistor P21. The XOR gate circuit 200 thus constructed can output a signal at the output terminal as the exclusive or value of the input signals a and B

In the AND-XOR gate 100 shown in FIG. 1, the CMOSAND gate may include the NAND gate 110 AND the INV gate 120 AND include 6 transistors, while in the XOR gate 200 shown in FIG. 2, the XOR gate 200 includes 4 transistors. Therefore, if the cmos AND gate circuit in fig. 1 is directly combined with the XOR gate circuit in fig. 2, an AND-XOR gate circuit constituted by 10 transistors can be formed. However, applicants have appreciated that the CMOS AND gate in fig. 1 may comprise an INV gate formed by a PMOS transistor P13 AND an NMOS transistor N13, AND the XOR gate 200 in fig. 2 may comprise an inverter circuit formed by a PMOS transistor P21 AND an NMOS transistor N21. Therefore, the applicant has appreciated that by using the INV gate circuit formed by the PMOS transistor P13 AND the NMOS transistor N13 as a part of the AND gate circuit in fig. 1 as the inverter circuit formed by the PMOS transistor P21 AND the NMOS transistor N21 shown in fig. 2 AND changing the corresponding signal connection manner, only the transistors corresponding to the PMOS transistor P22 AND the NMOS transistor N22 in fig. 2 need to be added in fig. 1, AND the AND-XOR gate circuit can be implemented by adding only two transistors compared to the AND gate circuit in fig. 1. That is, the AND-XOR gate may be implemented with only 6 transistors.

Of course, those skilled in the art will appreciate that when the NAND gate in the AND-XOR gate 100 of FIG. 1 is replaced with a NOR gate, the OR-XOR gate may also be implemented by adding only two transistors to the OR gate with the concepts of the present disclosure.

Fig. 3 schematically illustrates a structural schematic of a composite logic gate circuit 300 based on a transistor level design, according to an embodiment of the disclosure.

The complex logic gate circuit 300 as shown in fig. 3 may include a simple logic gate circuit, a PMOS transistor P32 (corresponding to a first PMOS transistor) and an NMOS transistor N32 (corresponding to a first NMOS transistor), wherein the simple logic gate circuit may include the first logic gate circuit 310 and an inverter circuit formed by a PMOS transistor P31 (corresponding to a second PMOS transistor) and an NMOS transistor N31 (corresponding to a second NMOS transistor).

The first logic gate circuit 310 may be configured to receive the first input signal a and the second input signal B and to output a first output signal at the output terminal Y31. The PMOS transistor P31 in the inverter circuit has a source coupled to the power input VDD, a drain coupled to the output Y32, and a gate configured to be coupled to the output Y31 for receiving the first output signal. The NMOS transistor N31 in the inverter circuit has a source coupled to the ground terminal VSS, a drain coupled to the output terminal Y32, and a gate configured to be coupled to the output terminal Y31 for receiving the first output signal.

The source of the PMOS transistor P32 is coupled to the drain of the PMOS transistor P31 instead of the gate of the PMOS transistor P21 as shown in fig. 2, the drain is coupled to the output terminal Y3, and the gate is configured to receive the third input signal C. The source of the NMOS transistor N32 is coupled to the gate of the PMOS transistor P31 instead of the drain of the PMOS transistor P21 as shown in fig. 2, the drain is coupled to the output terminal Y3, and the gate is configured to receive the third input signal C. By such a change in the connection manner, although the inverter formed by 2 transistors is reduced compared to directly combining the cmos AND gate circuit in fig. 1 with the XOR gate circuit in fig. 2, the AND/OR-XOR circuit can still be realized.

Further, the first logic gate circuit 310 may be a NAND gate circuit or a NOR gate circuit. In the case where the first logic gate circuit 310 is a NAND gate circuit, the above simple logic gate circuit may be an AND gate circuit, AND the complex logic gate circuit 300 may be an AND-XOR gate circuit; and in the case where the first logic gate circuit 310 is a NOR gate circuit, the above simple logic gate circuit may be an OR gate circuit, and the complex logic gate circuit 300 may be an OR-XOR gate circuit. The first logic gate circuit 310 may be formed of 4 transistors in general. The first logic gate circuit 310 is described below as an example of a NAND gate circuit.

When the first logic gate circuit 310 is a NAND gate circuit, the first output signal at the output terminal Y31 is

And the output signal at the output terminal Y32 is AB, so that the output signal at the output terminal Y3 may be AB

And the output signal at output Y3 meets the following truth table.

It follows that in the complex logic gate circuit 300 as an AND-XOR gate circuit OR an OR-XOR gate circuit, by using an inverter among the AND gate circuit OR the OR gate circuit, the AND-XOR gate circuit OR the NOR-XOR gate circuit can be realized by adding only two transistors to the AND gate circuit OR the OR gate circuit, as shown in fig. 3. Thus, the AND-XOR gate or the NOR-XOR gate is implemented with only 8 transistors, which is reduced by 50% compared to the original design shown in FIG. 1, thereby reducing the area AND power consumption of the AND-XOR gate or the NOR-XOR gate.

In the above embodiments, pass transistor logic may implement logic functions with a minimum number of transistors, but with the problem of node signal non-full swing. In fig. 3, when AB is 0 at the output terminal Y32, since the PMOS transistor P32 has weak ability to pass 0 and the NMOS transistor N32 has weak ability to pass 1, when C is 0, Y3 is 0+ Vthp (weak 0); and when C is 1, Y3 is VDD-Vthn (weak 1). There is a threshold penalty at the output node Y3 which causes significant delay and reduces noise margin in low voltage applications.

Fig. 4 schematically illustrates a structural schematic of a composite logic gate circuit 400 based on a transistor level design, according to another embodiment of the present disclosure.

As shown in fig. 4, by adding a transmission gate composed of a PMOS transistor P43 (corresponding to the third PMOS transistor) and an NMOS transistor N43 (corresponding to the third NMOS transistor), when AB is 0 at the output terminal Y42, the output is directly given through the transmission gate, and Y4 is C, so that the problem of non-full swing can be avoided.

In one embodiment, the gate of the PMOS transistor P43 is coupled to the output terminal Y42, the source is coupled to the output terminal Y4, the drain is coupled to the gates of the PMOS transistor P42 and the NMOS transistor N42 and configured to receive the input signal C. The source of the NMOS transistor N43 is coupled to the gates of the PMOS transistor P42 and the NMOS transistor N42 and is configured to receive the input signal C, the drain is coupled to the output terminal Y4, and the gate is coupled to the output terminal Y41 to receive the first output signal of the first logic gate circuit 410.

As described above, the first logic gate circuit 410 may be a NAND gate circuit or a NOR gate circuit, and is generally composed of 4 transistors. Thus, fig. 4 implements 10 transistors, a 37.5% reduction over the 16 transistors of the original design shown in fig. 1.

Thus, in conventional designs, the number of transistors used for the AND-XOR gate implemented with a common complementary static CMOS logic gate is large (e.g., 16), AND the area AND power consumption are large. In the present disclosure, in the design of the AND-XOR gate circuit OR the OR-XOR gate circuit, the AND-XOR circuit OR the OR-XOR gate circuit can be realized by adding only 2 transistors by using the inverter in the AND gate circuit OR the OR gate circuit. To solve the problem of the non-full swing of the node signal, one transmission gate circuit may be added, so that the AND-XOR circuit OR the OR-XOR circuit is implemented by, for example, 10 transistors, thereby reducing the area AND power consumption of the AND-XOR circuit OR the NOR-XOR circuit.

Further, the present disclosure is not limited thereto, AND the above-described method may also be applied to a similar complex logic gate circuit, such as an AND-XNOR gate circuit OR an OR-XNOR gate circuit, AND the like.

Fig. 5 schematically illustrates a structural schematic of another composite logic gate circuit 500 based on a transistor level design, according to another embodiment of the present disclosure.

In fig. 5, an inverter circuit composed of a PMOS transistor P53 (corresponding to a fourth PMOS transistor) and an NMOS transistor N53 (corresponding to a fourth NMOS transistor) is added as compared with that in fig. 3.

The source of the PMOS transistor P53 is coupled to the power input VDD, the drain is coupled to the output Y5, and the gate is coupled to the drains of the PMOS transistor P52 and the NMOS transistor N52. The source of the NMOS transistor N53 is coupled to the ground terminal VSS, the drain is coupled to the output terminal Y5, and the gate is coupled to the drains of the PMOS transistor P52 and the NMOS transistor N52. In the case where the first logic gate 510 is a NAND gate, the first output signal at the output terminal Y51 is

The output signal at output terminal Y52 is AB and the output signal at output terminal Y5 is

Thus, the composite logic gate circuit 500 in FIG. 5 may be an AND-XNOR gate circuit. Similarly, in the case where the first logic gate circuit 510 is a NOR gate circuit, the output signal at the output terminal Y5 may be

The composite logic gate circuit 500 in fig. 5 may be an OR-XNOR (OR-nor) gate circuit.

Fig. 6A and 6B schematically show structural diagrams of a CMOS nand gate circuit 600-1 and a CMOS NOR gate circuit 600-2, respectively, included in a composite logic gate circuit based on a transistor level design according to an embodiment of the present disclosure.

In one embodiment, the first logic gate circuit 310-510 shown in FIGS. 3-5 may be a NAND gate circuit as shown in FIG. 6A. As shown in fig. 6A, NAND gate circuit 600-1 includes PMOS transistor P61 (corresponding to the fifth PMOS transistor), PMOS transistor P62 (corresponding to the sixth PMOS transistor), NMOS transistor N61 (corresponding to the fifth NMOS transistor), and NMOS transistor N62 (corresponding to the sixth NMOS transistor). The sources of the PMOS transistor P61 and the PMOS transistor P62 are both coupled to the power input VDD and the drains are both coupled to the output N1, the gate of the PMOS transistor P61 is configured to receive the first input signal a and the gate of the PMOS transistor P62 is configured to receive the second input signal B. The source of the NMOS transistor N61 is coupled to the drain of the NMOS transistor N62, the drain is coupled to the output terminal N1, and the gate is configured to receive the first input signal a. The drain of the NMOS transistor N62 is coupled to the source of the NMOS transistor N61, the source is coupled to ground, and the gate is configured to receive the second input signal B. NAND gate 600-1 outputs a first output signal at output N1

In addition, the output terminal N1 in fig. 6A may correspond to the output terminals Y31-Y51 in fig. 3-5.

As shown in fig. 6B, the NOR gate circuit 600-2 includes a PMOS transistor P63 (corresponding to a seventh PMOS transistor), a PMOS transistor P64 (corresponding to an eighth PMOS transistor), an NMOS transistor N63 (corresponding to a seventh NMOS transistor), and an NMOS transistor N64 (corresponding to an eighth MOS transistor). The source of the PMOS transistor P63 is coupled to the power input VDD, the drain is coupled to the source of the PMOS transistor P64, and the gate is configured to receive the first input signal A. The source of the PMOS transistor P64 is coupled to the drain of the PMOS transistor P63, the drain is coupled to the output terminal N2, and the gate is configured to receive the second input signal B. The sources of NMOS transistor N63 and N64 are both coupled to ground VSS and the drains are both coupled to output N2, the gate of NMOS transistor N63 is configured to receive the first input signal A and the gate of NMOS transistor N64The pole is configured to receive a second input signal B. NOR gate 600-2 may output a first output signal at output N2

In addition, the output terminal N2 in fig. 6B may correspond to the output terminals Y31-Y51 in fig. 3-5.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

The circuit has the advantages that the number of transistors of the circuit is reduced under the condition of not influencing the performance of the circuit, the power consumption of the circuit is effectively reduced, and the circuit is not only used for the circuit with the logic function of exclusive OR, but also used for the circuit with the logic function of exclusive OR.

In one embodiment, a composite logic gate circuit is provided, the composite logic gate circuit comprising: the device comprises a simple logic gate circuit, a first PMOS tube and a first NMOS tube; wherein the simple logic gate circuit comprises a first logic gate circuit and an inverter circuit, wherein the first logic gate circuit is configured to receive a first input signal and a second input signal and output a first output signal, wherein the inverter circuit comprises a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is coupled to a power input terminal, the drain of the second NMOS transistor is coupled to a ground terminal, the drain of the second PMOS transistor is coupled to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is configured to receive the first output signal, wherein the source of the first PMOS transistor is coupled to the drains of the second PMOS transistor and the second NMOS transistor, the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is configured to receive a third input signal, wherein, the source of the first NMOS transistor is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS transistor, the gate is configured to receive the third input signal, and wherein the simple logic gate circuit is an AND gate circuit or an OR gate circuit, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit, respectively.

In one embodiment there is provided a mining apparatus comprising a composite logic gate circuit as described above. The mining machine equipment is an mining machine or data processing equipment for mining virtual currency such as bitcoin, letelt coin and the like.

The terms "front", "back", "top", "bottom", "over", "under" and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be reproduced exactly. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, utility model content, or detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in a practical implementation.

The above description may refer to elements or nodes or features being "coupled" or "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly coupled to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly coupled. That is, "coupled" is intended to include both direct and indirect coupling of elements or other features, including coupling using one or more intermediate elements.

It will be further understood that the terms "comprises/comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A composite logic gate circuit, comprising:

the device comprises a simple logic gate circuit, a first PMOS tube and a first NMOS tube;

wherein the simple logic gate circuit comprises a first logic gate circuit and an inverter circuit,

wherein the first logic gate circuit is configured to receive a first input signal and a second input signal and output a first output signal,

wherein the inverter circuit comprises a second PMOS transistor and a second NMOS transistor, the second PMOS transistor has a source coupled to a power input terminal, a drain coupled to a drain of the second NMOS transistor, and a gate configured to receive the first output signal, the second NMOS transistor has a source coupled to ground, a drain coupled to the drain of the second PMOS transistor, and a gate configured to receive the first output signal,

wherein the source of the first PMOS transistor is coupled to the drains of the second PMOS transistor and the second NMOS transistor, the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor, and the gate of the first PMOS transistor is configured to receive a third input signal,

wherein the source of the first NMOS transistor is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS transistor, the gate is configured to receive the third input signal, an

Wherein the simple logic gate circuit is an AND gate circuit or an OR gate circuit, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit, respectively.

2. The composite logic gate circuit of claim 1, further comprising a transmission gate circuit comprising a third PMOS transistor and a third NMOS transistor, wherein

The grid electrode of the third PMOS tube is coupled to the drain electrode of the second PMOS tube and the source electrode of the first PMOS tube, the source electrode is coupled to the drain electrodes of the first PMOS tube and the first NMOS tube, and the drain electrode is coupled to the grid electrodes of the first PMOS tube and the first NMOS tube,

the gate of the third NMOS transistor is coupled to the source of the first NMOS transistor and configured to receive the first output signal, the source is coupled to the gates of the first PMOS transistor and the first NMOS transistor, and the drain is coupled to the drains of the first PMOS transistor and the first NMOS transistor.

3. The composite logic gate circuit of claim 1, further comprising a second inverter circuit comprising a fourth PMOS transistor and a fourth NMOS transistor, wherein

The source electrode of the fourth PMOS tube is coupled to a power supply input end, the drain electrode of the fourth PMOS tube is coupled to the drain electrode of the fourth NMOS tube, the grid electrode of the fourth PMOS tube is coupled to the drain electrodes of the first PMOS tube and the first NMOS tube,

the source electrode of the fourth NMOS tube is coupled to the ground terminal, the drain electrode of the fourth NMOS tube is coupled to the drain electrode of the fourth PMOS tube, and the grid electrode of the fourth NMOS tube is coupled to the drain electrodes of the first PMOS tube and the first NMOS tube.

4. The composite logic gate circuit of claim 1, wherein the first logic gate circuit is a nand gate circuit, the nand gate circuit comprising:

a fifth PMOS tube, a fifth NMOS tube, a sixth PMOS tube and a sixth NMOS tube,

wherein the source of the fifth PMOS transistor is coupled to the power input terminal, the drain of the fifth PMOS transistor is coupled to the drain of the sixth PMOS transistor and the drain of the fifth NMOS, and the gate of the fifth PMOS transistor is configured to receive the first input signal,

wherein the source of the sixth PMOS transistor is coupled to the power input terminal, the drain of the sixth PMOS transistor is coupled to the drains of the fifth PMOS transistor and the fifth NMOS transistor, and the gate of the sixth PMOS transistor is configured to receive the second input signal,

wherein the source of the fifth NMOS transistor is coupled to the drain of the sixth NMOS transistor, the drain of the fifth NMOS transistor is coupled to the drain of the fifth PMOS transistor, the drain of the sixth PMOS transistor is coupled to the drain of the fifth PMOS transistor, and the gate of the fifth NMOS transistor is configured to receive the first input signal,

the source electrode of the sixth NMOS transistor is coupled to the ground terminal, the drain electrode of the sixth NMOS transistor is coupled to the source electrode of the fifth NMOS transistor, and the grid electrode of the sixth NMOS transistor is configured to receive the second input signal,

wherein a node at which drains of the fifth PMOS transistor, the sixth PMOS transistor, and the fifth NMOS transistor are coupled to each other is configured to output the first output signal.

5. The composite logic gate circuit of claim 1, wherein the first logic gate circuit is an nor gate circuit, the nor gate circuit comprising:

a seventh PMOS tube, a seventh NMOS tube, an eighth PMOS tube and an eighth NMOS tube,

wherein the source of the seventh PMOS transistor is coupled to the power input terminal, the drain of the seventh PMOS transistor is coupled to the source of the eighth PMOS transistor, and the gate of the seventh PMOS transistor is configured to receive the first input signal,

wherein the source of the eighth PMOS transistor is coupled to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is coupled to the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor, and the gate of the eighth PMOS transistor is configured to receive the second input signal,

wherein the source of the seventh NMOS transistor is coupled to ground, the drain of the seventh NMOS transistor is coupled to the drains of the eighth PMOS transistor and the eighth NMOS transistor, and the gate of the seventh NMOS transistor is configured to receive the first input signal,

wherein the source of the eighth NMOS transistor is coupled to ground, the drain of the eighth NMOS transistor and the drain of the eighth PMOS transistor, and the gate of the eighth NMOS transistor is configured to receive the second input signal,

wherein a node at which drains of the eighth PMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are coupled to each other is configured to output the first output signal.

6. A mining apparatus, characterized in that it comprises a composite logic gate circuit as claimed in any one of claims 1 to 5.