CN203788252U - Clock filter circuit - Google Patents
Clock filter circuit Download PDFInfo
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- CN203788252U CN203788252U CN201420076915.6U CN201420076915U CN203788252U CN 203788252 U CN203788252 U CN 203788252U CN 201420076915 U CN201420076915 U CN 201420076915U CN 203788252 U CN203788252 U CN 203788252U
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Abstract
The utility model provides a clock filter circuit. The clock filter circuit comprises a first filtering unit, a second filtering unit, a first logical unit, a second logical unit, a latch unit, a third logical unit, a fourth logical unit and a multiplexing unit. The first filtering unit and the second filtering unit are used for filtering input clock signals; the first input terminal of the first logical unit is connected with a clock signal source, and the second input terminal of the first logical unit is connected with the output terminal of the first filtering unit; the first input terminal of the second logical unit is connected with the clock signal source, and the second input terminal of the second logical unit is connected with the output terminal of the second filtering unit; the latch unit is used for giving response to output signals of the first logical unit and the second logical unit and generating a path of output; the first input terminal of the third logical unit is connected with the clock signal source, and the second input terminal of the third logical unit is connected with the output terminal of the latch unit; the first input terminal of the fourth logical unit is connected with the clock signal source, and the second input terminal of the fourth logical unit is connected with the output terminal of the latch unit; and the multiplexing unit is used for acquiring output signals of the latch unit, the third logical unit and the fourth logical unit. The clock filter circuit can protect clock signals more effectively, and is characterized by low power dissipation, short self-adaption period and the like, and can be applied to large scale integrated circuits.
Description
Technical field
The utility model relates to filter design field, is specifically related to clock filtering circuit.
Background technology
In the middle of large scale integrated circuit, the clock signal of signal source of clock affects service behaviour and the operating efficiency of integrated circuit.When meeting with sudden external high pressure (as thunderbolt, static etc.), clock signal tends to be subject to larger impact, so that the situations such as incompleteness, amplitude jump appear in signal.Lost accurate clock, the sequential of integrated circuit just can be chaotic, and cause the randomness consequences such as operation mistake after the multistage amplification of integrated circuit.In existing scheme, have the filter circuit much designing for clock, its filtering mode adopting comprises substantially: 1, utilize the combination of a plurality of schmitt triggers and d type flip flop, as shown in Figure 1; 2, utilize the combination that can edit time delay unit or Buffer Pool and d type flip flop, as shown in Figure 2; And other utilizes the circuit design of many group time delay unit and digital filter.The outstanding defect that such scheme exists is: filter function is comparatively single, fails really to realize the self adaptation to the work period of clock signal, directly causes thus the decline of the service behaviour of the applicability of filter circuit and the integrated circuit of its protection.
Utility model content
For the problem of mentioning in background technology, the utility model proposes clock filtering circuit, a kind of multi-functional, low-power consumption and the filters solutions in self-adaptation clock cycle are provided, avoid because sudden external high pressure, surge etc. impact clock signal, its technical scheme is as follows:
Clock filtering circuit, comprises
The first filter unit, its input connects signal source of clock, in order to the clock signal of input is carried out to filtering, then exports the first clock signal;
The first logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of the first filter unit;
The second filter unit, its input connects signal source of clock, in order to the clock signal of input is considered to ripple, then exports second clock signal;
The second logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of the second filter unit;
Latch units, be provided with first input end and the second input, its first input end is connected with the output of the first logical block, and its second input is connected with the output of the second logical block, in order to respond the output signal of the first logical block, the second logical block, produces a road output;
The 3rd logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of latch units;
The 4th logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of latch units; And
Multiplexed unit, is provided with first input end, the second input and the 3rd input, obtains respectively the output signal of latch units, the 3rd logical block and the 4th logical block, finally exports the 3rd clock signal.
In such scheme, utilize the first filter unit to carry out filtering to the low cycle of clock signal, to produce the first clock signal, utilize the second filter unit to carry out filtering to the high cycle of clock signal, to produce second clock signal.Described first, second clock signal is through first, second logical block access latch units, the 3rd clock signal that latch units is identical with signal source of clock effective period according to the output of latch principle.Described the 3rd logical block is obtained described the 3rd clock signal, to produce four clock signal longer than the effective period of the 3rd clock signal.Described the 4th logical block is obtained described the 3rd clock signal, to produce five clock signal shorter than the effective period of the 3rd clock signal.Described multiplexed unit is in order to obtain described the 3rd clock signal, the 4th clock signal, the 5th clock signal and source clock signal, the clock signal of finally closing road stable output.
The technical solution of the utility model further comprises:
Described the first filter unit comprises the first logic module, the first resistance, the first magnetic hysteresis logic module and some electric capacity;
Described the first logic module, is provided with input and output, and its input is as the input of the first filter unit;
Described the first magnetic hysteresis logic module, is provided with input and output, between its input and the output of described the first logic module, is connected to the first resistance, and its output is as the output of the first filter unit;
Between described the first resistance and magnetic hysteresis logic module input, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects voltage source.
Further, described the first filter unit also includes the first transistor, and the grid of described the first transistor connects the first input end of the first logical block, and drain electrode connects the input of the first magnetic hysteresis logic module, and source electrode connects voltage source.
Further, described the first logical block comprises a transistor, and described transistorized grid connects the first input end of the first logical block, and drain electrode connects the second input of the first logical block, and source electrode connects signal ground.
Further, described the second filter unit comprises the second logic module, the second resistance, the second magnetic hysteresis logic module and some electric capacity;
Further, described the second logic module, is provided with input and output, and its input is as the input of the second filter unit;
Further, described the second magnetic hysteresis logic module, is provided with input and output, between its input and the output of described the second logic module, is connected to the second resistance, and its output is as the output of the second filter unit;
Further, between described the second resistance and magnetic hysteresis logic module input, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects signal ground.
Further, described the second filter unit also includes transistor seconds, and the grid of described transistor seconds connects the first input end of the second logical block, and source electrode connects the input of the second magnetic hysteresis logic module, and drain electrode connects signal ground.
Further, described the second logical block is disjunction gate circuit.
Further, described multiplexed unit comprises multiplexing module, the first non-conjunction circuit, the second non-conjunction circuit and closes road module;
Described multiplexing module, is provided with first input end, the second input, input end of clock, and described first input end connects the output of latch units, and described the second input connects signal source of clock, and described input end of clock meets clock signal T0;
Described the first non-conjunction circuit, is provided with first input end and the second input, and described first input end connects the output of multiplexing module, the lively clock signal T1 of the second input;
Described the second non-conjunction circuit, be provided with first input end, the second input and the 3rd input, described first input end connects the output of the 3rd logical block, and the second input connects the output of the first non-conjunction circuit, and the 3rd input connects the output of the 4th logical block;
Describedly close the output signal that road module is obtained the second non-conjunction circuit, close road output;
Described clock signal T0, T1 are controlled and are generated by a processor.
Further, described the 3rd logical block comprises the 3rd non-conjunction circuit and the 4th non-conjunction circuit;
Described the 3rd non-conjunction circuit, is provided with first input end and the second input, and its first input end connects signal source of clock, and the second input connects the output of latch units;
Described the 4th non-conjunction circuit, is provided with first input end and the second input, and its first input end connects the output of the 3rd non-conjunction circuit, the second input termination clock signal T2; Its output connects the output of the 3rd logical block, and described clock signal T2 is controlled and generated by a processor.
Described the 4th logical block comprises the first " NOR gate " circuit and the 5th non-conjunction circuit;
Described first " NOR gate " circuit, is provided with first input end and the second input, and its first input end connects signal source of clock, and the second input connects the output of latch units;
Described the 5th non-conjunction circuit, is provided with first input end and the second input, and its first input end connects the output of first " NOR gate " circuit, the second input termination clock signal T3; Its output connects the output of the 4th logical block, and described clock signal T3 is controlled and generated by a processor.
Advantage of the present utility model and beneficial effect comprise:
1, the utility model comprises time delay filtering, steady-state filtering, clock signal and the multiple function such as latchs, and more efficiently clock signal protection is provided and is applicable to each adhesive integrated circuit.
2, the utility model scheme comprises multinomial clock cycle alignment mechanism, can realize the self adaptation to the clock cycle.
3, the utility model adopts passive electric circuit element, and circuit is stable, and power loss is lower.
Accompanying drawing explanation
Fig. 1 is existing filter circuit schematic diagram one.
Fig. 2 is existing filter circuit schematic diagram two.
Fig. 3 is frame structure schematic diagram of the present utility model.
Fig. 4 is electrical block diagram of the present utility model.
Fig. 5 is the generation circuit diagram of clock signal (T0, T1, T2, T3).
Fig. 6 is clock signal and the circuit output table of comparisons of Fig. 5.
Embodiment
As follows by reference to the accompanying drawings, the application's scheme is further described:
As shown in Figure 3, clock filtering circuit, obtains the clock signal of signal source of clock 1, and it comprises
The first filter unit 2, its input connects signal source of clock 1, in order to the clock signal of input is carried out to filtering, then exports the first clock signal;
The first logical block 3, is provided with first input end and the second input, and its first input end connects signal source of clock 1, and its second input connects the output of the first filter unit 2;
The second filter unit 4, its input connects signal source of clock 1, in order to the clock signal of input is considered to ripple, then exports second clock signal;
The second logical block 5, is provided with first input end and the second input, and its first input end connects signal source of clock 1, and its second input connects the output of the second filter unit 4;
Latch units 6, be provided with first input end and the second input, its first input end is connected with the output of the first logical block 3, and its second input is connected with the output of the second logical block 5, in order to respond the output signal of the first logical block 3, the second logical block 5, produces a road output;
The 3rd logical block 7, is provided with first input end and the second input, and its first input end connects signal source of clock 1, and its second input connects the output of latch units 6;
The 4th logical block 8, is provided with first input end and the second input, and its first input end connects signal source of clock 1, and its second input connects the output of latch units 6; And
Multiplexed unit 9, is provided with first input end, the second input and the 3rd input, obtains respectively the output signal of latch units 6, the 3rd logical block 7 and the 4th logical block 8, finally exports the 3rd clock signal.
In such scheme, utilize the first filter unit to carry out filtering to the low cycle of clock signal, to produce the first clock signal, utilize the second filter unit to carry out filtering to the high cycle of clock signal, to produce second clock signal.Described first, second clock signal is through first, second logical block access latch units, the 3rd clock signal that latch units is identical with signal source of clock effective period according to the output of latch principle.Described the 3rd logical block is obtained described the 3rd clock signal, to produce four clock signal longer than the effective period of the 3rd clock signal.Described the 4th logical block is obtained described the 3rd clock signal, to produce five clock signal shorter than the effective period of the 3rd clock signal.Described multiplexed unit is in order to obtain described the 3rd clock signal, the 4th clock signal, the 5th clock signal and source clock signal, the clock signal of finally closing road stable output.
As shown in Figure 4, described the first filter unit 2 comprises the first logic module 21, the first resistance 22, the first magnetic hysteresis logic module 23 and some electric capacity;
Described the first logic module 21, is specially "NOT" circuit, and its input is as the input of the first filter unit 2, and effect is that clock signal is anti-phase and produces a little time delay;
Described the first magnetic hysteresis logic module 23, be specially smith trigger, between the output of its input and described the first logic module 21, be connected to the first resistance 22, its output is as the output of the first filter unit 2, its effect is the saltus step by a small margin of buffered clock signal, stable clock signal output;
Between described the first resistance 22 and the first magnetic hysteresis logic module 23 inputs, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects voltage source.
Described the first filter unit 2 also includes the first transistor 24, and the grid of described the first transistor 24 connects the first input end of the first logical block 2, and drain electrode connects the input of the first magnetic hysteresis logic module 24, and source electrode connects voltage source.
Described the first logical block 3 comprises a transistor, and described transistorized grid connects the first input end of the first logical block 2, and drain electrode connects the second input of the first logical block 2, and source electrode connects signal ground.
Described the second filter unit 3 comprises the second logic module 31, the second resistance 32, the second magnetic hysteresis logic module 33 and some electric capacity;
Described the second logic module 4, is specially "NOT" circuit, and its input is as the input of the second filter unit 3, and effect is that clock signal is anti-phase and produces a little time delay;
Described the second magnetic hysteresis logic module 33, be specially smith trigger, between the output of its input and described the second logic module 31, be connected to the second resistance 32, its output is as the output of the second filter unit 3, its effect is the saltus step by a small margin of buffered clock signal, stable clock signal output;
Between described the second resistance 32 and the second magnetic hysteresis logic module 33 inputs, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects signal ground.
Described the second filter unit 3 also includes transistor seconds 34, and the grid of described transistor seconds 34 connects the first input end of the second logical block 31, and source electrode connects the input of the second magnetic hysteresis logic module 33, and drain electrode connects signal ground.
Above-mentioned first, second filter unit symmetrical configuration, in order to the high or low cycle to clock signal is carried out filtering respectively, and between its each electric capacity and node, be also connected to a transistor switch, the control signal S0-S7 being produced by a processor controls the break-make of each transistor switch to realize the adaptive control to filtering.
Described the second logical block is disjunction gate circuit.
Described multiplexed unit 9 comprises multiplexing module 91, the first non-conjunction circuit 92, the second non-conjunction circuit 93 and closes road module 94;
Described multiplexing module 91, is provided with first input end, the second input, input end of clock, and described first input end connects the output of latch units 6, and described the second input connects signal source of clock 1, and described input end of clock meets clock signal T0;
Described the first non-conjunction circuit 92, is provided with first input end and the second input, and described first input end connects the output of multiplexing module 91, the lively clock signal T1 of the second input;
Described the second non-conjunction circuit 93, be provided with first input end, the second input and the 3rd input, described first input end connects the output of the 3rd logical block 7, the second input connects the output of the first non-conjunction circuit 92, and the 3rd input connects the output of the 4th logical block 8;
Describedly close the output signal that road module 94 is obtained the second non-conjunction circuit 93, close road output;
Described clock signal T0, T1 are controlled and are generated by a processor.
Further, described the 3rd logical block 7 comprises the 3rd non-conjunction circuit 71 and the 4th non-conjunction circuit 72;
Described the 3rd non-conjunction circuit 71, is provided with first input end and the second input, and its first input end connects the output that signal source of clock 1, the second input connects latch units 6;
Described the 4th non-conjunction circuit 72, is provided with first input end and the second input, and its first input end connects the output of the 3rd non-conjunction circuit 71, the second input termination clock signal T2; Its output connects the output of the 3rd logical block 7, and described clock signal T2 is controlled and generated by a processor.
Described the 4th logical block 8 comprises first " NOR gate " circuit 81 and the 5th non-conjunction circuit 82;
Described first " NOR gate " circuit 81, is provided with first input end and the second input, and its first input end connects the output that signal source of clock 1, the second input connects latch units 6;
Described the 5th non-conjunction circuit 82, is provided with first input end and the second input, and its first input end connects the output of first " NOR gate " circuit 81, the second input termination clock signal T3; Its output connects the output of the 4th logical block 8, and described clock signal T3 is controlled and generated by a processor.
As shown in Figure 5, the generation circuit of clock signal (T0, T1, T2, T3), comprises a processor, the register being connected by data/address bus with processor, the first decoder being connected with register, the second decoder.Described the first decoder produces in order to control the control signal S0-S7 of each transistor folding of filter circuit, described the second decoder clocking T0-T3.、
As shown in Figure 6, when T0T1T2T3=0000, filter circuit is not worked; When T0T1T2T3=1100, filter circuit to clock signal high the low cycle carry out filtering, export the clock signal identical with the former clock cycle; When T0T1T2T3=1010, filter circuit carries out filtering to the high cycle of clock signal, exports and the clock signal that is greater than the former clock cycle; When T0T1T2T3=1001, filter circuit carries out filtering to the low cycle of clock signal, and output is less than the clock signal of former clock cycle.
Above-mentioned preferred implementation should be considered as illustrating of the application's scheme implementation mode, and identical, the approximate or technology deduction made based on this of all and the application's scheme, replacement, improvement etc. all should be considered as the protection range of this patent.
Claims (10)
1. a clock filtering circuit, is characterized in that: comprise
The first filter unit, its input connects signal source of clock, in order to the clock signal of input is carried out to filtering, then exports the first clock signal;
The first logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of the first filter unit;
The second filter unit, its input connects signal source of clock, in order to the clock signal of input is considered to ripple, then exports second clock signal;
The second logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of the second filter unit;
Latch units, be provided with first input end and the second input, its first input end is connected with the output of the first logical block, and its second input is connected with the output of the second logical block, in order to respond the output signal of the first logical block, the second logical block, produces a road output;
The 3rd logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of latch units;
The 4th logical block, is provided with first input end and the second input, and its first input end connects signal source of clock, and its second input connects the output of latch units; And
Multiplexed unit, is provided with first input end, the second input and the 3rd input, obtains respectively the output signal of latch units, the 3rd logical block and the 4th logical block, finally exports the 3rd clock signal.
2. clock filtering circuit according to claim 1, is characterized in that: described the first filter unit comprises the first logic module, the first resistance, the first magnetic hysteresis logic module and some electric capacity;
Described the first logic module, is provided with input and output, and its input is as the input of the first filter unit;
Described the first magnetic hysteresis logic module, is provided with input and output, between its input and the output of described the first logic module, is connected to the first resistance, and its output is as the output of the first filter unit;
Between described the first resistance and magnetic hysteresis logic module input, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects voltage source.
3. clock filtering circuit according to claim 2, it is characterized in that: described the first filter unit also includes the first transistor, the grid of described the first transistor connects the first input end of the first logical block, and drain electrode connects the input of the first magnetic hysteresis logic module, and source electrode connects voltage source.
4. clock filtering circuit according to claim 1, it is characterized in that: described the first logical block comprises a transistor, described transistorized grid connects the first input end of the first logical block, and drain electrode connects the second input of the first logical block, and source electrode connects signal ground.
5. clock filtering circuit according to claim 1, is characterized in that: described the second filter unit comprises the second logic module, the second resistance, the second magnetic hysteresis logic module and some electric capacity;
Described the second logic module, is provided with input and output, and its input is as the input of the second filter unit;
Described the second magnetic hysteresis logic module, is provided with input and output, between its input and the output of described the second logic module, is connected to the second resistance, and its output is as the output of the second filter unit;
Between described the second resistance and magnetic hysteresis logic module input, be provided with a plurality of nodes, be connected respectively some electric capacity, the other end of each electric capacity connects signal ground.
6. clock filtering circuit according to claim 5, it is characterized in that: described the second filter unit also includes transistor seconds, the grid of described transistor seconds connects the first input end of the second logical block, and source electrode connects the input of the second magnetic hysteresis logic module, and drain electrode connects signal ground.
7. clock filtering circuit according to claim 1, is characterized in that: described the second logical block is disjunction gate circuit.
8. clock filtering circuit according to claim 1, is characterized in that: described multiplexed unit comprises multiplexing module, the first non-conjunction circuit, the second non-conjunction circuit and closes road module;
Described multiplexing module, is provided with first input end, the second input, input end of clock, and described first input end connects the output of latch units, and described the second input connects signal source of clock, and described input end of clock meets clock signal T0;
Described the first non-conjunction circuit, is provided with first input end and the second input, and described first input end connects the output of multiplexing module, the lively clock signal T1 of the second input;
Described the second non-conjunction circuit, be provided with first input end, the second input and the 3rd input, described first input end connects the output of the 3rd logical block, and the second input connects the output of the first non-conjunction circuit, and the 3rd input connects the output of the 4th logical block;
Describedly close the output signal that road module is obtained the second non-conjunction circuit, close road output;
Described clock signal T0, T1 are controlled and are generated by a processor.
9. clock filtering circuit according to claim 1, is characterized in that: described the 3rd logical block comprises the 3rd non-conjunction circuit and the 4th non-conjunction circuit;
Described the 3rd non-conjunction circuit, is provided with first input end and the second input, and its first input end connects signal source of clock, and the second input connects the output of latch units;
Described the 4th non-conjunction circuit, is provided with first input end and the second input, and its first input end connects the output of the 3rd non-conjunction circuit, the second input termination clock signal T2; Its output connects the output of the 3rd logical block, and described clock signal T2 is controlled and generated by a processor.
10. clock filtering circuit according to claim 1, is characterized in that: described the 4th logical block comprises the first " NOR gate " circuit and the 5th non-conjunction circuit;
Described first " NOR gate " circuit, is provided with first input end and the second input, and its first input end connects signal source of clock, and the second input connects the output of latch units;
Described the 5th non-conjunction circuit, is provided with first input end and the second input, and its first input end connects the output of first " NOR gate " circuit, the second input termination clock signal T3; Its output connects the output of the 4th logical block, and described clock signal T3 is controlled and generated by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420076915.6U CN203788252U (en) | 2014-02-21 | 2014-02-21 | Clock filter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420076915.6U CN203788252U (en) | 2014-02-21 | 2014-02-21 | Clock filter circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203788252U true CN203788252U (en) | 2014-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420076915.6U Withdrawn - After Issue CN203788252U (en) | 2014-02-21 | 2014-02-21 | Clock filter circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103795378A (en) * | 2014-02-21 | 2014-05-14 | 中山芯达电子科技有限公司 | Clock filter circuit |
| WO2020135955A1 (en) * | 2018-12-27 | 2020-07-02 | Ams International Ag | Filters for removing disturbances from signals |
-
2014
- 2014-02-21 CN CN201420076915.6U patent/CN203788252U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103795378A (en) * | 2014-02-21 | 2014-05-14 | 中山芯达电子科技有限公司 | Clock filter circuit |
| CN103795378B (en) * | 2014-02-21 | 2017-03-15 | 中山芯达电子科技有限公司 | Clock filter circuits |
| WO2020135955A1 (en) * | 2018-12-27 | 2020-07-02 | Ams International Ag | Filters for removing disturbances from signals |
| CN113228510A (en) * | 2018-12-27 | 2021-08-06 | ams国际有限公司 | Filter for removing interference from a signal |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20140820 Effective date of abandoning: 20171114 |