CN203522681U

CN203522681U - Double-time-delay power-on sequential control circuit

Info

Publication number: CN203522681U
Application number: CN201320642454.XU
Authority: CN
Inventors: 谢华超
Original assignee: SHENZHEN NEW GREENNET TECHNOLOGIES Co Ltd
Current assignee: SHENZHEN NEW GREENNET TECHNOLOGIES Co Ltd
Priority date: 2013-10-18
Filing date: 2013-10-18
Publication date: 2014-04-02
Anticipated expiration: 2023-10-18

Abstract

The utility model discloses a double-time-delay power-on sequential control circuit, and the sequential control circuit comprises a switch power module. The sequential control circuit is characterized in that the sequential control circuit also comprises a low drop-out linear voltage regulator LDO, a PMOS tube, and an NPN tube which is connected with the PMOS tube; a first-stage time-delay circuit is disposed between the low drop-out linear voltage regulator LDO and the PMOS tube; a second-stage time-delay circuit is disposed between the power module and the NPN tube; the switch power module outputs a VIN voltage which serves as the input voltage of the LDO, and the switch power module is connected with the source electrode of the PMOS tube; the LDO generates a VCC_Core voltage and is connected with the input end of the switch power module; the VCC_Core voltage can serve as a power supply voltage of the circuit; and the PMOS tube outputs a VCC_I/O voltage. The sequential control circuit provided by the utility model is simple in structure, is low in cost, and has a function of double-time-delay power-on slow start.

Description

A kind of dual-delay power-on time sequence control circuit

Technical field

The utility model relates to power supply control technology field, more particularly, relates to a kind of dual-delay power-on time sequence control circuit.

Background technology

In recent years, along with the develop rapidly of broadband connections technology, many high performance flush bonding processors, as: CPU, DSP, FPGA etc., these devices need two power supplies, i.e. I/O mouth voltage and core voltage conventionally.Whether these two kinds of voltages correctness that powers on, be not only related to system and can normally start, and also most important for the stability of the long-term work of circuit.If plurality of voltages sequential is not right, may there is latch-up, even burn out device.When input and output voltage should be as the I/O voltage of processor, for generation of a road core voltage, and must meet core voltage, first power on again, the requirement powering on after I/O mouth voltage, because both voltages have electric sequence requirement, therefore must add certain power-on time sequence control circuit.Common electrifying timing sequence scheme has following two kinds: the first is to adopt special-purpose power management chip, and power management chip is controlled the electrifying timing sequence of every road voltage according to inner time schedule controller, but this chip periphery circuit is complicated, and cost is higher.The second is to utilize band enable pin DC-DC power supply chip to control electrifying timing sequence, and general this chip needs external inductance, and metal-oxide-semiconductor peripheral components, takies PCB area larger, and cost is higher.

Summary of the invention

The utility model is to provide a kind of circuit simple, with low cost, has power on a kind of dual-delay power-on time sequence control circuit of soft start function of dual-delay.

In order to solve the problems of the technologies described above, the utility model has adopted following technical scheme:

A kind of dual-delay power-on time sequence control circuit, comprise a switch power module, it is characterized in that: also comprise that the low pressure difference linear voltage regulator LDO being connected with described switch power module manages with PMOS pipe and with described PMOS the NPN pipe being connected, between described low pressure difference linear voltage regulator LDO and NPN pipe, be provided with first order delay circuit, between described power module and NPN pipe, be provided with second level delay circuit, described switch power module output VIN voltage, as the input voltage of LDO, is also connected with the source electrode of PMOS pipe simultaneously; LDO produces VCC_Core voltage and connects first order delay circuit input, simultaneously also as supply power voltage required in circuit, and PMOS pipe output VCC_I/O voltage.

Described first order delay circuit is by resistance (R2), electric capacity (C3) forms, one end of resistance (R2) connects VCC_core, and the other end connects the NPN pipe base stage of (Q2) and one end of electric capacity (C3), and the other end of electric capacity (C3) connects the grounded emitter of NPN pipe (Q2).

Described second level delay circuit is by resistance (R1), electric capacity (C1) forms, one end of resistance (R1) connects the collector electrode of NPN pipe (Q2), the other end connects one end of electric capacity (C1) and the grid of PMOS pipe (Q1), and the other end of electric capacity (C1) connects the source electrode of VIN and PMOS pipe (Q1).

Described PMOS pipe is selected the chip of P raceway groove SI4465DY.

Compared with prior art, the utility model circuit possesses following advantage:

1, the utility model circuit is simple, with low cost, has the dual-delay soft start function that powers on, and can be widely used in, in flush bonding processor power supply sequence circuit, especially for communication system, having the requirement of plurality of voltages sequential, has more practicality;

2, the utility model circuit is by LDO output voltage V CC_Core, one side is as the supply power voltage of circuit, during on the other hand by this voltage electrifying startup, control the conducting of VCC_IN voltage input end and output, thereby realize the function that VCC_I/O voltage powers on after VCC_Core voltage;

3, the utility model first order delay circuit, second level delay circuit all adopt RC circuit, by regulating the resistance of RC resistance capacitance to change the time of electrifying startup, to reach, delay the effect starting;

4, the utility model LDO is not with and enables to control pin, and when having plurality of voltages and need to go up sequential function, cost advantage is particularly evident.

After reading by reference to the accompanying drawings the detailed description of execution mode of the present utility model, it is clearer that feature of the present utility model and advantage will become.

Accompanying drawing explanation

Fig. 1 is electrical block diagram of the present utility model;

Fig. 2 is circuit theory diagrams of the present utility model.

Embodiment

With embodiment, the utility model is described in further detail below, but should be noted that protection range of the present utility model is not limited only to this.

Consult Fig. 1, the utility model circuit is by a switch power module, a low pressure difference linear voltage regulator LDO, a PMOS pipe, a NPN triode, and 2 delay circuits form.Wherein, switch power module output VCC_VIN voltage, as the input voltage of LDO, is also connected to the source electrode of PMOS pipe simultaneously; LDO connects first order delay circuit input for generation of VCC_Core voltage, simultaneously also as supply power voltage required in circuit; PMOS pipe is as output VCC_I/O voltage; The base stage of NPN triode connects first order delay circuit, grounded emitter, collector electrode connects second level delay circuit, grid control end as PMOS pipe, when VCC_Corel output voltage reaches NPN triode gate limit value, NPN manages conducting, gate pmos pole tension is pulled down to ground by resistance, now reached threshold voltage, PMOS manages conducting, due to the capacitor charging characteristic of second level delay circuit, VCC_I/O voltage is exported in the drain electrode of PMOS pipe gently, thereby guarantees after VCC_I/O voltage in the requirement of VCC_Core voltage electrifying timing sequence.

Consult Fig. 2, what LDO adopted is three port AME1084 chips with low cost, and the 3rd pin is connected to the VIN of power supply, the common port of the 1st pin contact resistance R3 and resistance R 4, the other end of the 2nd pin contact resistance R3, by resistance R 3, resistance R 4 forms adjusting VCC_Core output voltage; First order delay circuit is by resistance R 2, and capacitor C 3 forms, and one end of resistance R 2 connects VCC_core, and the base stage that the other end connects NPN pipe Q2 is connected with capacitor C 3 one end, and the other end of capacitor C 3 connects the grounded emitter of NPN pipe Q2; What NPN pipe Q2 triode was selected is NPN type pipe, and model is BC847ALT1, and its collector electrode connects one end of R1; The second utmost point delay circuit is by resistance R 1, and capacitor C 1 forms, and the other end of resistance R 1 connects one end of capacitor C 1 and the grid of PMOS pipe Q1, and the other end of capacitor C 1 connects the source electrode of VIN and PMOS pipe Q1; The P raceway groove SI4465DY chip that PMOS pipe is selected, this chip has field effect transistor characteristic functions.

Operation principle of the present utility model is as follows:

When input VCC_VIN voltage is through U1 chip output VCC_Core voltage, VCC_Core is through first order delay circuit resistance R 2, C3, can regulating resistance R2, the resistance of C3 resistance capacitance is to reach the time of triode conducting, when VCC_Core is greater than the threshold value of Vge of triode Q1, Q2 conducting, according to triode switch characteristic, collector electrode level becomes low level, and resistance R 1 resistance can be similar to ground connection, Q1 conducting, voltage VCC_I/O voltage is suitable with input voltage VCC_VIN, and by change resistance R 1, the resistance of the resistance capacitance of C1 can change the ON time of Q1.Thereby VCC_Core voltage first VCC_I/O voltage powers on, and completes electrifying timing sequence functional requirement.

Although described by reference to the accompanying drawings execution mode of the present utility model; but those skilled in the art can make various distortion or modification within the scope of the appended claims; as long as be no more than the described protection range of claim of the present utility model, all should be within protection range of the present utility model.

Claims

1. a dual-delay power-on time sequence control circuit, comprise a switch power module, it is characterized in that: also comprise that the low pressure difference linear voltage regulator LDO being connected with described switch power module manages with PMOS pipe and with described PMOS the NPN pipe being connected, between described low pressure difference linear voltage regulator LDO and NPN pipe, be provided with first order delay circuit, between described power module and NPN pipe, be provided with second level delay circuit, described switch power module output VIN voltage, as the input voltage of LDO, is also connected with the source electrode of PMOS pipe simultaneously; LDO produces VCC_Core voltage and connects first order delay circuit input, simultaneously also as supply power voltage required in circuit, and PMOS pipe output VCC_I/O voltage.

2. a kind of dual-delay power-on time sequence control circuit as claimed in claim 1, it is characterized in that: described first order delay circuit is by resistance (R2), electric capacity (C3) forms, one end of resistance (R2) connects VCC_core, the other end connects the NPN pipe base stage of (Q2) and one end of electric capacity (C3), and the other end of electric capacity (C3) connects the grounded emitter of NPN pipe (Q2).

3. a kind of dual-delay power-on time sequence control circuit as claimed in claim 1, it is characterized in that: described second level delay circuit is by resistance (R1), electric capacity (C1) forms, one end of resistance (R1) connects the collector electrode of NPN pipe (Q2), the other end connects one end of electric capacity (C1) and the grid of PMOS pipe (Q1), and the other end of electric capacity (C1) connects the source electrode of VIN and PMOS pipe (Q1).

4. a kind of dual-delay power-on time sequence control circuit as claimed in claim 1, is characterized in that: described PMOS pipe is selected the chip of P raceway groove SI4465DY.