CN203340051U - Phase-locked loop system - Google Patents
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- CN203340051U CN203340051U CN2013203703300U CN201320370330U CN203340051U CN 203340051 U CN203340051 U CN 203340051U CN 2013203703300 U CN2013203703300 U CN 2013203703300U CN 201320370330 U CN201320370330 U CN 201320370330U CN 203340051 U CN203340051 U CN 203340051U
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Abstract
The utility model relates to a phase-locked loop system. The phase-locked loop system comprises at least two phase-locked loop circuits which are suitable for generating signals to be detected according to reference signals and decoding parameters, and a detection selection unit, wherein the detection selection unit is suitable for selecting any one of the signals to be detected having predetermined frequency as an output signal when at least one phase-locked circuit is detected to generate signals to be detected of which frequency is the predetermined frequency. According to the technical scheme, the phase-locked loop system comprises multiple phase-locked loop circuits, when one phase-locked loop circuit which generates the signal to be detected taken as the output signal is in abnormal work state, one signal can be instantly selected from the signals to be detected generated by other normally-operated phase-locked loop circuits and is taken as the output signal of the phase-locked loop system, so reliability of the phase-locked loop system is improved.
Description
Technical field
The utility model relates to the PHASE-LOCKED LOOP PLL TECHNIQUE field, particularly a kind of phase-locked loop systems.
Background technology
Phase-locked loop (PLL, Phase-locked loops) is a kind of frequency of feedback control principle realization and simultaneous techniques of phase place utilized, and its effect is that the reference clock that the clock of circuit output is outside with it keeps synchronizeing.When the frequency of reference clock or phase place change, phase-locked loop can detect this variation, and inner reponse system is carried out the regulation output frequency by it, until both re-synchronizations.
Phase-locked loop is and frame synchronization synchronous for the row that improves television receiver at first, to improve antijamming capability.Later stage the 1950's, phase-locked loop was for tracking, telemetry and telecommand to the space flight target along with the development of space technology.The beginning of the sixties, the application of phase-locked loop was more and more extensive along with the development of digital communication system, such as for coherent demodulation, extracting reference carrier, set up bit synchronization etc.FM signal phase-locked frequency discriminator with thresholding extended capability also grows up at the beginning of the sixties.Aspect electronic instrument, phase-locked loop has played important function in the instruments such as frequency synthesizer and phase meter.The current application of PHASE-LOCKED LOOP PLL TECHNIQUE concentrates on following three aspects: the modulation and demodulation of signal; The frequency modulation of signal and demodulation; The frequency synthesizer circuit of signal.
Following miniaturization, modular trend, increasing electronic circuit is substituted by chip, and phase-locked loop systems also is integrated in chip.For example, and, along with scientific and technological development, the probability of chip (, space, deep-sea, ,Ji Han area, very hot area etc.) application in some extreme environment is more and more higher.As everyone knows, chip is Sensitive Apparatus, and the more fragile part especially of the phase-locked loop systems in chip.In these extreme environments, phase-locked loop systems very easily breaks down, and causes chip to work.And, after phase-locked loop systems breaks down, it is very difficult changing chip in these extreme environments.Therefore, it is very urgent and necessary providing a kind of phase-locked loop systems of high reliability.
The utility model content
What the utility model solved is the low problem of existing phase-locked loop systems reliability.
For addressing the above problem, the utility model provides a kind of phase-locked loop systems, comprising: at least two phase-locked loop circuits that are suitable for according to reference signal and decoding parameter generating signal to be detected; Be suitable for selecting the arbitrary detection selected cell of the signal to be detected of described preset frequency as output signal that have when the frequency of the signal to be detected that at least one phase-locked loop circuit generation detected is preset frequency.
Optionally, described phase-locked loop systems also comprises: the crystal oscillator unit that is suitable for producing described reference signal; Be suitable for equating with the product of described preset frequency and the second parameter that according to the frequency of described reference signal and the product of the first parameter acquisition comprises the parameter decoding unit of the decoding parameter of described the first parameter and described the second parameter.
Optionally, described detection selected cell comprises: being suitable for producing testing result according to described reference signal, decoding parameter and signal to be detected is normal or abnormal detecting unit; Being suitable for selecting while being normal at least one testing result arbitrary is the selected cell of the corresponding signal to be detected of normal testing result as output signal.
Optionally, described selected cell is MUX.
Optionally, described detecting unit comprises: be suitable for that described reference signal is carried out to frequency division and take first frequency unit of the first fractional frequency signal of the ratio that produces frequency that frequency is described reference signal and described the second parameter; Be suitable for that described signal to be detected is carried out to frequency division and take second frequency unit of the second fractional frequency signal of the ratio that produces frequency that frequency is described signal to be detected and described the first parameter; Being suitable for the testing result that produces when the frequency of the frequency of described the first fractional frequency signal and described the second fractional frequency signal equates is abnormal comparing unit for testing result normal, that produce when the frequency of the frequency of described the first fractional frequency signal and described the second fractional frequency signal is unequal.
Optionally, described comparing unit comprises: generation unit fiducial time that is suitable for producing according to reference signal fiducial time; Be suitable for the pulse number of described the first fractional frequency signal being counted to produce within described fiducial time the first counter unit of the first numerical value; Be suitable for the pulse number of described the second fractional frequency signal being counted to produce within described fiducial time the second counter unit of second value; The frequency that is suitable for determining the frequency of described the first fractional frequency signal and described the second fractional frequency signal when described the first numerical value and described second value equate equates, at described the first numerical value and described second value, determine the frequency of described the first fractional frequency signal and the unequal numerical value comparing unit of frequency of described the second fractional frequency signal when unequal.
Optionally, described phase-locked loop systems also comprises and is suitable for described reference signal is carried out to frequency division to produce the three frequency division unit of described reference signal.
Optionally, described phase-locked loop systems also comprises the fault-signal generation unit that is suitable for output fault-signal when the frequency that the signal to be detected that arbitrary phase-locked loop circuit produces do not detected is described preset frequency.
Optionally, described fault-signal generation unit is AND circuit.
Compared with prior art, the technical solution of the utility model has the following advantages: phase-locked loop systems comprises at least two phase-locked loop circuits and detection selected cell, and each phase-locked loop circuit is suitable for exporting signal to be detected according to reference signal and decoding parameter.When the frequency that detects selected cell and detect the signal to be detected that at least one phase-locked loop circuit produces is preset frequency, select the arbitrary output signal of the signal to be detected of described preset frequency as phase-locked loop systems that have.Because phase-locked loop systems has a plurality of phase-locked loop circuits, when the signal to be detected produced breaks down as the phase-locked loop circuit work of the output signal of phase-locked loop systems, select a signal the signal to be detected of phase-locked loop circuit output that can be working properly from other by described detection selected cell, again as the output signal of phase-locked loop systems, therefore, improved the reliability of phase-locked loop systems.
Further, in a possibility of the present utility model, detecting unit in described detection selected cell produces the first fractional frequency signal to described reference signal frequency division, described signal frequency split to be detected is produced to the second fractional frequency signal, and within fiducial time, the pulse number of described the first fractional frequency signal and described the second fractional frequency signal is counted, whether the frequency of determining described signal to be detected by the pulse number of more described the first fractional frequency signal and described the second fractional frequency signal is preset frequency, whether the frequency of determining described signal to be detected is stable, thereby whether the work that detects exactly described phase-locked loop circuit is abnormal.
Further, in another possibility of the present utility model, phase-locked loop systems also comprises the fault-signal generation unit, when the equal operation irregularity of all phase-locked loop circuits, the frequency of all signals to be detected is not all described preset frequency, and described fault generation unit can be exported fault-signal.Described fault-signal can be used as the work interrupt signal of the chip of application phase-locked loop systems, when all phase-locked loop circuits are all worked while breaking down, the chip of application phase-locked loop systems quits work immediately, prevents that chip from still working on and damaging after all phase-locked loop circuits break down.
The accompanying drawing explanation
Fig. 1 is the structural representation of the phase-locked loop systems of the utility model execution mode;
Fig. 2 is the structural representation of the phase-locked loop systems of the utility model embodiment 1;
Fig. 3 is the structural representation of the detecting unit of the utility model embodiment 1;
Fig. 4 is the structural representation of the comparing unit of the utility model embodiment 1;
Fig. 5 is the structural representation of the phase-locked loop systems of the utility model embodiment 2.
Embodiment
Just as described in the background art, phase-locked loop keeps the circuit of synchronizeing as a kind of reference clock that can output clock is outside with it, applies very extensive.Along with scientific and technological development, phase-locked loop systems is integrated in chip, at some, in extreme environment, occurs.Be subject to the impact of extreme environment, the phase-locked loop systems in chip very easily produces fault, causes chip to work.And, after phase-locked loop systems breaks down, it is very difficult changing chip in these extreme environments.Through research, the inventor of the technical program provides a kind of phase-locked loop systems of high reliability.
For above-mentioned purpose of the present utility model, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiment of the utility model is described in detail.
Fig. 1 is the structural representation of the phase-locked loop systems of the utility model execution mode.With reference to figure 1, described phase-locked loop systems comprises a plurality of phase-locked loop circuits and detects selected cell 12.
Particularly, described phase-locked loop systems comprises n phase-locked loop circuit: the first phase-locked loop circuit 111, the second phase-locked loop circuit 112,, n phase-locked loop circuit 11n, n is natural number, and n >=2, described phase-locked loop systems comprises at least two phase-locked loop circuits.The quantity n of described phase-locked loop circuit can be set according to the reliability requirement to described phase-locked loop systems, higher to the reliability requirement of described phase-locked loop systems, and the value of the quantity n of described phase-locked loop circuit is larger.
Described phase-locked loop circuit is suitable for producing signal to be detected according to reference signal Fin and decoding parameter P: described the first phase-locked loop circuit 111 be suitable for producing the first signal Fout1 to be detected, described the second phase-locked loop circuit 112 be suitable for producing the second signal Fout2 to be detected,, described n phase-locked loop circuit 11n is suitable for producing n signal Foutn to be detected.
Described detection selected cell 12, be suitable for when the frequency of the signal to be detected that at least one phase-locked loop circuit generation detected is preset frequency, select the arbitrary output signal Fout of the signal to be detected of described preset frequency as described phase-locked loop systems that have, described output signal Fout can be used as the clock signal of the chip of the described phase-locked loop systems of application, and the frequency of described clock signal is described preset frequency.
Structure and operation principle below in conjunction with accompanying drawing and specific embodiment to the phase-locked loop systems of technical solutions of the utility model are elaborated.
Embodiment 1
Fig. 2 is the structural representation of the phase-locked loop systems of the utility model embodiment 1.With reference to figure 2, in the present embodiment, described phase-locked loop systems comprises three phase-locked loop circuits: the first phase-locked loop circuit 111, the second phase-locked loop circuit 112 and the 3rd phase-locked loop circuit 113, wherein, described the first phase-locked loop circuit 111 is suitable for producing the first signal Fout1 to be detected, described the second phase-locked loop circuit 112 is suitable for producing the second signal Fout2 to be detected, and described the 3rd phase-locked loop circuit 113 is suitable for producing the 3rd signal Fout3 to be detected.
Described phase-locked loop systems also comprises crystal oscillator unit 21 and parameter decoding unit 22.
Described crystal oscillator unit 21 can be quartz oscillator, is suitable for producing described reference signal Fin, and described reference signal Fin is an input signal of described phase-locked loop circuit.Described phase-locked loop circuit is suitable for the frequency of described reference signal Fin is zoomed in or out, and produces the signal to be detected with described preset frequency.For example, the frequency of described reference signal Fin can be 40MHz.
If the frequency of described signal to be detected is described phase-locked loop circuit, the frequency of described reference signal Fin is amplified and produced, when described phase-locked loop circuit is working properly, the frequency of described signal to be detected is described preset frequency, therefore, the ratio of the frequency of described preset frequency and described reference signal Fin is exactly the frequency multiplication factor of described phase-locked loop circuit, and described parameter decoding unit 22 is suitable for the frequency multiplication factor of described phase-locked loop circuit is decoded into to the described decoding parameter P that described phase-locked loop circuit can be understood.
Described decoding parameter P can comprise the first parameter and the second parameter, meets following relation between the frequency of described reference signal Fin and described preset frequency: described the first parameter of the frequency * of described preset frequency=described reference signal Fin/described the second parameter.Particularly, described parameter decoding unit 22 comprises computing unit, setting unit and determining unit (Fig. 2 is not shown).
Described computing unit is suitable for calculating the ratio of the frequency of described preset frequency and described reference signal Fin, according to the frequency of described preset frequency/described reference signal Fin=described the first parameter/described the second parameter, to obtain the ratio of described the first parameter and described the second parameter.Described setting unit is suitable for the ratio according to described the first parameter and described the second parameter, and the first parameter or the second parameter are set, and determines a parameter in described the first parameter and described the second parameter.Described determining unit is suitable for described the first parameter of calculating according to a parameter of described setting unit setting and described computing unit and the ratio of described the second parameter is determined another parameter.
Further, described the second parameter can also be decoded into the product of the 3rd parameter and the 4th parameter, i.e. described the first parameter of the frequency * of described preset frequency=described reference signal Fin/(described the 4th parameter of described the 3rd parameter *).
Described preset frequency is to require to be set according to the chip of the described phase-locked loop systems of application, and in the present embodiment, described preset frequency is 240MHz, therefore, the frequency multiplication factor of described phase-locked loop circuit is 6, through decoding, described the first parameter is 48, and described the second parameter is 8.Further, described the 3rd parameter is 8, and described the 4th parameter is 1.
It should be noted that, described the first parameter is that the 48, second parameter is 8 specific embodiments just, and in other embodiments, described decoding parameter can also have different values.The frequency multiplication factor of described phase-locked loop circuit is carried out to decoding and can adopt existing techniques in realizing, for avoiding repeating, the structure of described parameter decoding unit 22 is no longer too much illustrated.
It should be noted that, in the present embodiment, described the first phase-locked loop circuit 111, described the second phase-locked loop circuit 112 and described the 3rd phase-locked loop circuit 113 share same crystal oscillator unit 21 and parameter decoding unit 22, can reduce the cost of described phase-locked loop systems.In other embodiments, described the first phase-locked loop circuit 111, described the second phase-locked loop circuit 112 and described the 3rd phase-locked loop circuit 113 also can be connected respectively three different crystal oscillator unit and parameter decoding unit, as long as guarantee that the set of frequency of the described first signal Fout1 to be detected, the described second signal Fout2 to be detected and described the 3rd signal Fout3 to be detected is described preset frequency.
Continuation is with reference to figure 2, and described detection selected cell 12 comprises detecting unit 121 and selected cell 122.
Described detecting unit 121 is suitable for producing testing result according to described reference signal Fin, decoding parameter P and signal to be detected, and described testing result is normal or abnormal.In the present embodiment, described phase-locked loop systems comprises three phase-locked loop circuits, and therefore, described testing result is to there being three: the first testing result R1, the second testing result R2 and the 3rd testing result R3.
Described testing result is for normally referring to that described phase-locked loop circuit is in normal operating conditions, and the frequency of the signal to be detected of output is described preset frequency.Described testing result can mean with binary data 1 and 0, for example, with 0, means that described testing result is for normal, with 1, means that described testing result is for abnormal.
Described selected cell 122 is suitable at least one testing result while being normal, select arbitrary for the corresponding signal to be detected of normal testing result as output signal.Particularly, when to only have described the first testing result R1 be normal, select the output signal Fout of the described first signal Fout1 to be detected as described phase-locked loop systems; When described the first testing result R1 and described the second testing result R2 are when normal, the output signal Fout as described phase-locked loop systems from the described first signal Fout1 to be detected and the optional signal of the described second signal Fout2 to be detected; When described the first testing result R1, described the second testing result R2 and the described the 3rd as a result R3 be when normal, the output signal Fout as described phase-locked loop systems from the described first signal Fout1 to be detected, the described second signal Fout2 to be detected and the optional signal of the described the 3rd signal Fout2 to be detected.
While having at least two to be normal in described testing result, can be by the priority orders of described signal to be detected be set, from described testing result, be signal of according to priority selective sequential normal corresponding signal described to be detected, as the output signal of described phase-locked loop systems.
Described selected cell 122 can be MUX, and the input signal of described MUX is described signal to be detected, and the control signal of described MUX is described testing result, and the output of described MUX is the output of described phase-locked loop systems.
In the present embodiment, by the frequency that detects described signal to be detected, whether be that described preset frequency judges that whether the work of described phase-locked loop circuit is normal.With reference to figure 3, described detecting unit 121 comprises the first frequency unit 31, the second frequency unit 32 and comparing unit 33, the the first signal Fout1 to be detected that described the first phase-locked loop circuit 111 is exported of below take detects as example, and described detecting unit 121 is elaborated.
Described the first frequency unit 31 is suitable for described reference signal Fin is carried out to frequency division, to produce the first fractional frequency signal f1, the ratio of the frequency that the frequency of described the first fractional frequency signal f1 is described reference signal Fin and described the second parameter.
Described the second frequency unit 32 is suitable for the described first signal Fout1 to be detected is carried out to frequency division, to produce the second fractional frequency signal f2, and the ratio that the frequency of described the second fractional frequency signal f2 is the described first signal Fout1 to be detected and described the first parameter.
Described the first testing result R1 that described comparing unit 33 is suitable for producing when the frequency of the frequency of described the first fractional frequency signal f1 and described the second fractional frequency signal f2 equates is for normal, and described the first testing result R1 produced when the frequency of the frequency of described the first fractional frequency signal f1 and described the second fractional frequency signal f2 is unequal is abnormal.
As previously mentioned, meet following relation between the frequency of described reference signal Fin and described preset frequency: described the first parameter of the frequency * of described preset frequency=described reference signal Fin/described the second parameter, therefore, when the frequency of the frequency of described the first fractional frequency signal f1 and described the second fractional frequency signal f2 equates, the frequency that can determine the described first signal fout1 to be detected is exactly described preset frequency, and the operating state of described the first phase-locked loop circuit 111 is normal.
In the present embodiment, the frequency of described reference signal Fin is 40MHz, and described the second parameter is 8, and the frequency of described the first fractional frequency signal f1 is 5MHz.Described the first parameter is 48, therefore, when the frequency that described the second fractional frequency signal f2 detected also is 5MHz, can determine that described the first phase-locked loop circuit 111 is in normal operating state, the frequency of the described first signal Fout1 to be detected is 240MHz, can be as the output signal of described phase-locked loop systems.
Described the first frequency unit 31 and described the second frequency unit 32 can be realized by available circuit, do not repeat them here.With reference to figure 4, described comparing unit 33 comprises generation unit 41 fiducial time, the first counter unit 42, the second counter unit 43 and numerical value comparing unit 44.
Described fiducial time, generation unit 41 was suitable for producing T fiducial time according to reference signal fr.Described reference signal fr can be produced by three frequency division unit 45, and described three frequency division unit 45 is suitable for described reference signal Fin is carried out to frequency division to produce described reference signal fr.In the present embodiment, the described reference signal Fin in 45 pairs of described three frequency division unit has carried out the frequency division of 40000 times, the frequency of the described reference signal produced is 1KHz, therefore, the frequency of described the first fractional frequency signal f1 and described the second fractional frequency signal f2 all is greater than the frequency of described reference signal fr, described fiducial time T=1/1KHz=1ms.
Described the first counter unit 42 is suitable for, in described fiducial time T, the pulse number of described the first fractional frequency signal f1 being counted to produce the first numerical value of N 1.
Described the second counter unit 43 is suitable for, in described fiducial time T, the pulse number of described the second fractional frequency signal f2 being counted to produce second value N2.
Described numerical value comparing unit 44 is suitable for when described the first numerical value of N 1 is equal with described second value N2, determines that the frequency of described the first fractional frequency signal f1 and the frequency of described the second fractional frequency signal f2 equate; At described the first numerical value of N 1 and described second value N2 when unequal, determine that the frequency of the frequency of described the first fractional frequency signal f1 and described the second fractional frequency signal f2 is unequal.
Described numerical value comparing unit 44 is to determine by the difference computing whether described the first numerical value of N 1 and described second value N2 equate, consider that there is error in described numerical value comparing unit 44, if the absolute value of the difference of described the first numerical value of N 1 and described second value N2 is in certain error range, | N1-N2|≤A still can judge that described the first numerical value of N 1 and described second value N2 equate, A means error.Described error A can require to be arranged according to the frequency stability to described signal to be detected, and higher to the frequency stability requirement of described signal to be detected, the value of described error A is less.
It should be noted that, described detecting unit 121 is detected all phase-locked loop circuits simultaneously, during as the phase-locked loop circuit operation irregularity of the output signal of phase-locked loop systems, can select immediately the output signal of the signal to be detected of another phase-locked loop circuit output working properly as described phase-locked loop systems when the signal to be detected produced.
In the present embodiment, whether the frequency that detects described signal to be detected by described detecting unit 121 equates with described preset frequency, judges that whether the work of described phase-locked loop circuit is normal.Because described phase-locked loop systems has a plurality of phase-locked loop circuits, when the signal to be detected produced during as the phase-locked loop circuit operation irregularity of the output signal of phase-locked loop systems, select a signal the signal to be detected of phase-locked loop circuit output that can be working properly from other by described detection selected cell, output signal as phase-locked loop systems, therefore, improved the reliability of phase-locked loop systems.
In embodiment 2, described phase-locked loop systems also comprises fault-signal generation unit 51.Described fault-signal generation unit 51 is suitable for when the frequency of the signal to be detected that arbitrary phase-locked loop circuit generation do not detected is described preset frequency, output fault-signal Fault.
Described fault-signal generation unit 51 can be AND circuit, and whether the frequency that is input as the output signal that detects described phase-locked loop circuit of described AND circuit is the testing result of described preset frequency.Described fault-signal Fault can mean with binary data 0 and 1, for example, by 1 frequency that means not detect the signal to be detected that arbitrary phase-locked loop circuit produces, being described preset frequency, is described preset frequency by 0 frequency that means to detect the signal to be detected that has a phase-locked loop circuit generation at least.
When the frequency that the signal to be detected that arbitrary phase-locked loop circuit produces do not detected is described preset frequency, according to described fault-signal Fault, the chip of applying described phase-locked loop systems can quit work immediately, prevents that chip from still working on and damaging after all phase-locked loop circuits break down.
In sum, the phase-locked loop systems that technical solutions of the utility model provide comprises a plurality of phase-locked loop circuits, the frequency of the signal to be detected by detecting the output of described phase-locked loop circuit, when the signal to be detected produced during as the phase-locked loop circuit operation irregularity of the output signal of phase-locked loop systems, can select a signal from other the signal to be detected of phase-locked loop circuit output working properly immediately, as the output signal of phase-locked loop systems, therefore, improved the reliability of phase-locked loop systems.
Although the utility model discloses as above, the utility model not is defined in this.Any those skilled in the art, within not breaking away from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with the claim limited range.
Claims (9)
1. a phase-locked loop systems, is characterized in that, comprising:
At least two phase-locked loop circuits that are suitable for according to reference signal and decoding parameter generating signal to be detected;
Be suitable for selecting the arbitrary detection selected cell of the signal to be detected of described preset frequency as output signal that have when the frequency of the signal to be detected that at least one phase-locked loop circuit generation detected is preset frequency.
2. phase-locked loop systems according to claim 1, is characterized in that, also comprises:
Be suitable for producing the crystal oscillator unit of described reference signal;
Be suitable for equating with the product of described preset frequency and the second parameter that according to the frequency of described reference signal and the product of the first parameter acquisition comprises the parameter decoding unit of the decoding parameter of described the first parameter and described the second parameter.
3. phase-locked loop systems according to claim 2, is characterized in that, described detection selected cell comprises:
Being suitable for producing testing result according to described reference signal, decoding parameter and signal to be detected is normal or abnormal detecting unit;
Being suitable for selecting while being normal at least one testing result arbitrary is the selected cell of the corresponding signal to be detected of normal testing result as output signal.
4. phase-locked loop systems according to claim 3, is characterized in that, described selected cell is MUX.
5. phase-locked loop systems according to claim 3, is characterized in that, described detecting unit comprises:
Be suitable for that described reference signal is carried out to frequency division and take first frequency unit of the first fractional frequency signal of the ratio that produces frequency that frequency is described reference signal and described the second parameter;
Be suitable for that described signal to be detected is carried out to frequency division and take second frequency unit of the second fractional frequency signal of the ratio that produces frequency that frequency is described signal to be detected and described the first parameter;
Being suitable for the testing result that produces when the frequency of the frequency of described the first fractional frequency signal and described the second fractional frequency signal equates is abnormal comparing unit for testing result normal, that produce when the frequency of the frequency of described the first fractional frequency signal and described the second fractional frequency signal is unequal.
6. phase-locked loop systems according to claim 5, is characterized in that, described comparing unit comprises:
Be suitable for producing according to reference signal generation unit fiducial time of fiducial time;
Be suitable for the pulse number of described the first fractional frequency signal being counted to produce within described fiducial time the first counter unit of the first numerical value;
Be suitable for the pulse number of described the second fractional frequency signal being counted to produce within described fiducial time the second counter unit of second value;
The frequency that is suitable for determining the frequency of described the first fractional frequency signal and described the second fractional frequency signal when described the first numerical value and described second value equate equates, at described the first numerical value and described second value, determine the frequency of described the first fractional frequency signal and the unequal numerical value comparing unit of frequency of described the second fractional frequency signal when unequal.
7. phase-locked loop systems according to claim 6, is characterized in that, also comprises and be suitable for described reference signal is carried out to frequency division to produce the three frequency division unit of described reference signal.
8. phase-locked loop systems according to claim 1, is characterized in that, also comprises the fault-signal generation unit that is suitable for output fault-signal when the frequency of the signal to be detected that arbitrary phase-locked loop circuit generation do not detected is described preset frequency.
9. phase-locked loop systems according to claim 8, is characterized in that, described fault-signal generation unit is AND circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203703300U CN203340051U (en) | 2013-06-25 | 2013-06-25 | Phase-locked loop system |
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| CN2013203703300U CN203340051U (en) | 2013-06-25 | 2013-06-25 | Phase-locked loop system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103414468A (en) * | 2013-06-25 | 2013-11-27 | 广州思信电子科技有限公司 | Phase-locked loop system |
| CN107251361A (en) * | 2015-01-30 | 2017-10-13 | 英捷电力技术有限公司 | Synchronization system and correlating method for generator unit |
-
2013
- 2013-06-25 CN CN2013203703300U patent/CN203340051U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103414468A (en) * | 2013-06-25 | 2013-11-27 | 广州思信电子科技有限公司 | Phase-locked loop system |
| CN103414468B (en) * | 2013-06-25 | 2016-08-31 | 广州思信电子科技有限公司 | Phase-locked loop systems |
| CN107251361A (en) * | 2015-01-30 | 2017-10-13 | 英捷电力技术有限公司 | Synchronization system and correlating method for generator unit |
| CN107251361B (en) * | 2015-01-30 | 2020-05-19 | 英捷电力技术有限公司 | Synchronization system and synchronization method for power generation units |
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