CN203224819U - Mainboard - Google Patents
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- CN203224819U CN203224819U CN 201320170096 CN201320170096U CN203224819U CN 203224819 U CN203224819 U CN 203224819U CN 201320170096 CN201320170096 CN 201320170096 CN 201320170096 U CN201320170096 U CN 201320170096U CN 203224819 U CN203224819 U CN 203224819U
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- 238000001514 detection method Methods 0.000 claims abstract description 29
- 239000007787 solid Substances 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 3
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- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
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Abstract
The utility model discloses a mainboard, comprising an SATA controller, a PCIE controller, a MINI PCIE interface, a detecting circuit and a switching circuit, wherein the MINI PCIE interface is used for MSATA equipment or MINI PCIE equipment to plug, the detecting circuit is used for detecting whether the MSATA equipment or the MINI PCIE equipment is plugged into the MINI PCIE interface, and the switching circuit is used for conducting the MSATA equipment plugged into the MINI PCIE interface with the SATA controller for being in data communication with the SATA controller or conducting the MINI PCIE equipment plugged into the MINI PCIE interface with the PCIE controller for being in data communication with the PCIE controller according to the detection results of the detection circuit, the detection circuit is connected with a preserved pin of the MINI PCIE interface, the switching circuit is connected with the detection circuit, and the SATA controller and the PCIE controller are both connected with the switching circuit. The mainboard has the beneficial effects that the MINI PCIE interface of the mainboard is enabled to be compatible with the MSATA equipment and the MINI PCIE equipment, so that use by a user is facilitated, and since one interface is compatible with different solid state discs, the cost is reduced.
Description
Technical Field
The utility model relates to a computer field, more specifically say, relate to a mainboard.
Background
The MSATA interface is a novel interface standard issued by SATA-IO (SATA international interface standard organization), and the solid state disk with the MSATA interface is widely applied to the fields of tablet computers, mobile phones, netbooks, POS, Set Top Boxes (STB), printers, and the like.
The MINI PCIE interface is an interface based on a PCIE bus, and a wireless local area network card, a 3G network card, a television card, a solid state disk and the like can be installed through the interface.
The MSATA interface looks the same as the MINI PCIE interface and the physical pins are compatible, but generally not directly interoperable. Because the interface of MSATA is identical in appearance to the MINI PCIE interface, but the data signal needs to be connected to the SATA controller, not the PCIE controller. Therefore, most MINI PCIE interfaces of the tablet computer, the notebook computer, the all-in-one machine, and the embedded motherboard cannot realize compatibility with the MSATA device and the MINI PCIE device at the same time, and an MSATA interface needs to be additionally provided on the motherboard to support the MSATA device, which increases the complexity of the motherboard, and is not beneficial to reducing the size and the cost.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in, the defect that can not compatible MSATA equipment and MINI PCIE equipment simultaneously to the above-mentioned MINI PCIE interface of prior art provides a mainboard.
The utility model provides a technical scheme that its technical problem adopted is:
a motherboard comprising a SATA controller for data communication with a MSATA device, a PCIE controller for data communication with a MINI PCIE device, the motherboard further comprising:
the MINI PCIE interface is used for being plugged with MSATA equipment or MINI PCIE equipment;
the detection circuit is used for detecting whether the MINI PCIE interface is inserted into an MSATA device or an MINI PCIE device;
the switching circuit is used for conducting the MSATA equipment inserted into the MINI PCIE interface and the SATA controller to carry out data communication or conducting the MINI PCIE equipment inserted into the MINI PCIE interface and the PCIE controller to carry out data communication according to the detection result of the detection circuit; wherein,
the detection circuit is connected with a reserved pin of the MINI PCIE interface, the switching circuit is connected with the detection circuit, and the SATA controller and the PCIE controller are both connected with the switching circuit.
Preferably, the motherboard further comprises a dc power supply for supplying power to the motherboard circuit.
Preferably, the detection circuit includes a pull-up resistor, wherein one end of the pull-up resistor is connected to a reserved pin of the MINI PCIE interface, and the other end of the pull-up resistor is connected to the dc power supply.
Preferably, the switching circuit includes a multiplexer, wherein a low-voltage single-ended input pin of the multiplexer is connected to the pull-up resistor and a reserved pin of the MINI PCIE interface, respectively;
a first differential pass-through input pin, a second differential pass-through input pin, a third differential pass-through input pin and a fourth differential pass-through input pin of the multiplexer are all connected with the PCIE controller;
and a fifth differential through input pin, a sixth differential through input pin, a seventh differential through input pin and an eighth differential through input pin of the multiplexer are all connected with the SATA controller.
Preferably, the first differential transmission pin, the second differential transmission pin, the first differential reception pin, and the second differential reception pin of the MINI PCIE interface are respectively connected to the first differential input pin, the second differential input pin, the third differential input pin, and the fourth differential input pin of the multiplexer.
Preferably, the type of the multiplexer is PI3PCIE2215, and the low-voltage single-ended input pin of the multiplexer is the 16 th pin thereof;
a first differential input pin, a second differential input pin, a third differential input pin and a fourth differential input pin of the multiplexer are a No. 2 pin, a No. 1 pin, a No. 6 pin and a No. 5 pin of the multiplexer respectively;
a first differential through input pin, a second differential through input pin, a third differential through input pin and a fourth differential through input pin of the multiplexer are a No. 3 pin, a No. 4 pin, a No. 7 pin and a No. 8 pin of the multiplexer respectively;
and a fifth differential through input pin, a sixth differential through input pin, a seventh differential through input pin and an eighth differential through input pin of the multiplexer are respectively a 23 th pin, a 22 nd pin, a 19 th pin and an 18 th pin of the multiplexer.
Preferably, the first differential transmission pin, the second differential transmission pin, the first differential reception pin, and the second differential reception pin of the MINI PCIE interface are a 31 st pin, a 33 rd pin, a 23 rd pin, and a 25 th pin thereof, respectively.
Preferably, the reserved pin of the MINI PCIE interface is the 51 st pin thereof.
Implement the utility model discloses a mainboard has following beneficial effect: the MINI PCIE interface of the mainboard can be compatible with MSATA equipment and MINI PCIE equipment, the use of a user is facilitated, one interface can be compatible with different solid state disks, and the cost can be saved.
Drawings
The invention will be further explained with reference to the drawings and examples, wherein:
fig. 1 is a schematic structural diagram of a main board according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a part of the structure and detection circuit of the MINI PCIE interface of the motherboard shown in fig. 1;
fig. 3 is a circuit diagram of a multiplexer of the motherboard shown in fig. 1.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a motherboard structure according to an embodiment of the present invention. In the present invention, the main board 10 includes: the system comprises an SATA controller 105, a PCIE controller 104, a MINI PCIE interface 102, a detection circuit 106 and a switching circuit 107, wherein the detection circuit 106 is connected with a reserved pin of the MINI PCIE interface 102, the switching circuit 107 is connected with the detection circuit 106, and both the SATA controller 105 and the PCIE controller 104 are connected with the switching circuit 107.
Wherein SATA controller 105 is configured to communicate data with a MSATA device;
the PCIE controller 104 is configured to perform data communication with the MINI PCIE device;
the MINI PCIE interface 102 is used to plug in the MSATA device 101 or the MINI PCIE device 100;
the detection circuit 106 is configured to detect whether an MSATA device or an MINI PCIE device is inserted into the MINI PCIE interface;
the switching circuit 107 is configured to conduct the MSATA device inserted into the MINI PCIE interface 102 and the SATA controller 105 for data communication or conduct the MINI PCIE device inserted into the MINI PCIE interface 102 and the PCIE controller 104 for data communication according to a detection result of the detection circuit 106.
In the embodiment of the present invention, with the 51 st pin of the MINI PCIE interface 102 as the detection pin, the detection circuit 106 identifies whether the MSATA device 101 or the MINI PCIE device 100 is currently inserted into the slot according to the signal of the 51 st pin. Then, the switching circuit 107 selects to connect the SATA controller 105 or the PCIE controller 104, so that the MINI PCIE interface 102 can be compatible with the MSATA device 101 and the MINI PCIE device 100.
Fig. 2 is a circuit diagram of a part of the structure and the detection circuit of the MINI PCIE interface of the motherboard shown in fig. 1. Fig. 3 is a circuit diagram of the multiplexer of the motherboard shown in fig. 1. The utility model discloses a mainboard 10 is still including being used for the DC power supply for the power supply of mainboard circuit, and this DC power supply includes a 3.3V power at least.
In an embodiment of the present invention, which is according to the prior art, the MINI PCIE interface 102 contains 52 standard pins. Each pin has a corresponding function, and the specific pin function is the prior art and need not be described herein. The 31 st pin and the 33 rd pin of the MINI PCIE interface 102 are differential transmission pins, the 23 rd pin and the 25 th pin are differential reception pins, and the 51 st pin is a reserved pin. The 31 th pin is a first differential transmission pin, the 33 th pin is a second differential transmission pin, the 23 rd pin is a first differential reception pin, and the 25 th pin is a second differential reception pin.
Referring to fig. 2, the detection circuit 106 includes a pull-up resistor R1. Referring to fig. 3, the switching circuit 107 includes a multiplexer 103, and the type of the multiplexer 103 is PI3PCIE2215, which includes 28 pins according to the prior art. Each pin has a corresponding function, and the specific pin function is the prior art and need not be described herein. The 2 nd, 1 st, 6 th and 5 th pins of the multiplexer 103 are respectively a first differential input pin, a second differential input pin, a third differential input pin and a fourth differential input pin, the 3 rd, 4 th, 7 th, 8 th, 23 th, 22 th, 19 th and 18 th pins are respectively a first differential through input pin, a second differential through input pin, a third differential through input pin, a fourth differential through input pin, a fifth differential through input pin, a sixth differential through input pin, a seventh differential through input pin and an eighth differential through input pin, and the 16 th pin is a low-voltage single-ended input pin.
Referring to fig. 2 and 3, pin 51 of the MINI PCIE interface 102 is connected to pin 16 of the multiplexer 103 through a resistor R2. And one end of the pull-up resistor R1 is connected to the 51 st pin of the MINI PCIE interface 102, and the other end is connected to the 16 th pin of the multiplexer 103 and the 3.3V power supply through the pull-up resistor R1. The 31 st, 33 rd, 23 rd and 25 th pins of the MINI PCIE interface 102 are connected to the 2 nd, 1 st, 6 th and 5 th pins of the multiplexer 103, respectively. The 3 rd pin, the 4 th pin, the 7 th pin and the 8 th pin of the multiplexer 103 are all connected to the PCIE controller 104. The 23 rd pin, the 22 nd pin, the 19 th pin and the 18 th pin of the multiplexer 103 are all connected with the SATA controller 105. The other pins of the MINI PCIE interface 102 are connected according to the connection method in the prior art to realize the corresponding functions.
The 11 th, 13 th, 15 th, 21 th, 24 th, 26 th and 28 th pins of the multiplexer 103 are all grounded; the 9 th, 12 th, 14 th, 17 th, 20 th, 25 th and 27 th pins of the multiplexer 103 are all connected with a 3.3V power supply. A capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4 are respectively connected between the 3.3V power supply and the ground so as to realize the filtering effect.
In the present invention, the 51 st pin of the MINI PCIE interface 102 is selected as the detection pin because the 51 st pin of the MINI PCIE device 100 is defined as unconnected, and the 51 st pin of the MSATA device 101 is defined as GND ground. Therefore, when a different device is plugged into the MINI PCIE interface 102, the multiplexer 103 can determine what device is according to the signal of the 51 st pin, and then turn on the data signal channel of the different device.
In operation, since the 51 st pin of the MINI PCIE device 100 is defined as unconnected, when the MINI PCIE device 100 is plugged into the MINI PCIE interface, the 16 th pin of the multiplexer 103 receives a high level through the pull-up resistor R1. The 1 st pin and the 2 nd pin of the multiplexer 103 are respectively communicated with the 3 rd pin and the 4 th pin, and the 5 th pin and the 6 th pin are respectively communicated with the 7 th pin and the 8 th pin, so that the data signal of the MINI PCIE interface 102 is communicated with the PCIE controller 104.
Whereas pin 51 of MSATA device 101 is defined as GND ground, therefore, when MSATA device 101 is plugged into MINI PCIE interface 102, pin 16 of multiplexer 103 receives a low level. The 1 st pin and the 2 nd pin of the multiplexer 103 are respectively communicated with the 23 rd pin and the 22 nd pin, and the 5 th pin and the 6 th pin are respectively communicated with the 19 th pin and the 18 th pin, so that the data signal of the MINIPCIE interface 102 is conducted with the SATA controller 105.
The utility model discloses in, reserve the pin as detecting the pin through one with the MINI PCIE interface on the mainboard for the MINI PCIE interface of mainboard can compatible MSATA equipment and MINI PCIE equipment, convenience of customers's use, and an interface can compatible different solid state hard drives, is favorable to simplifying hardware architecture and saves the cost.
It should be understood that the selection of the 51 st pin of the MINI PCIE interface as the detection pin in the present invention is merely exemplary, and in addition, other reserved pins of the MINI PCIE interface may be selected to achieve the same function.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (8)
1. A motherboard comprising a SATA controller (105) for data communication with a MSATA device, a PCIE controller (104) for data communication with a MINI PCIE device, the motherboard further comprising:
a MINI PCIE interface (102) for plugging MSATA devices or MINI PCIE devices;
a detection circuit (106) for detecting whether an MSATA device or an MINI PCIE device is inserted into the MINI PCIE interface;
the switching circuit (107) is used for conducting the MSATA device inserted into the MINI PCIE interface (102) and the SATA controller (105) to carry out data communication or conducting the MINI PCIE device inserted into the MINI PCIE interface (102) and the PCIE controller (104) to carry out data communication according to the detection result of the detection circuit (106);
the detection circuit (106) is connected with a reserved pin of the MINI PCIE interface (102), the switching circuit (107) is connected with the detection circuit (106), and the SATA controller (105) and the PCIE controller (104) are both connected with the switching circuit (107).
2. The motherboard of claim 1, further comprising a dc power supply for powering the motherboard circuitry.
3. The motherboard of claim 2, wherein the detection circuit (106) comprises a pull-up resistor (R1), wherein one end of the pull-up resistor (R1) is connected to a reserved pin of the MINI PCIE interface (102), and the other end is connected to the dc power supply.
4. The motherboard of claim 3, wherein the switching circuit (107) comprises a multiplexer (103), wherein a low voltage single ended input pin of the multiplexer (103) is connected to the pull-up resistor (R1) and a reserved pin of the MINI PCIE interface (102), respectively;
a first differential pass-through input pin, a second differential pass-through input pin, a third differential pass-through input pin and a fourth differential pass-through input pin of the multiplexer (103) are all connected with the PCIE controller (104);
and a fifth differential pass-through input pin, a sixth differential pass-through input pin, a seventh differential pass-through input pin and an eighth differential pass-through input pin of the multiplexer (103) are all connected with the SATA controller (105).
5. The motherboard of claim 4, wherein the first differential transmit pin, the second differential transmit pin, the first differential receive pin, and the second differential receive pin of the MINI PCIE interface (102) are connected to the first differential input pin, the second differential input pin, the third differential input pin, and the fourth differential input pin of the multiplexer (103), respectively.
6. The mainboard of claim 5, wherein the multiplexer (103) is of type PI3PCIE2215, and the low-voltage single-ended input pin of the multiplexer (103) is the 16 th pin thereof;
a first differential input pin, a second differential input pin, a third differential input pin and a fourth differential input pin of the multiplexer (103) are a No. 2 pin, a No. 1 pin, a No. 6 pin and a No. 5 pin of the multiplexer respectively;
a first differential through input pin, a second differential through input pin, a third differential through input pin and a fourth differential through input pin of the multiplexer (103) are a No. 3 pin, a No. 4 pin, a No. 7 pin and a No. 8 pin of the multiplexer respectively;
and a fifth differential through input pin, a sixth differential through input pin, a seventh differential through input pin and an eighth differential through input pin of the multiplexer (103) are respectively a 23 th pin, a 22 nd pin, a 19 th pin and an 18 th pin thereof.
7. The motherboard of claim 5, wherein the first differential transmit pin, the second differential transmit pin, the first differential receive pin, and the second differential receive pin of the MINI PCIE interface (102) are respectively the 31 st pin, the 33 rd pin, the 23 rd pin, and the 25 th pin thereof.
8. The motherboard of claim 1, wherein the reserved pin of the MINI PCIE interface (102) is its 51 st pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170096 CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170096 CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
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| CN203224819U true CN203224819U (en) | 2013-10-02 |
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| CN 201320170096 Expired - Fee Related CN203224819U (en) | 2013-04-08 | 2013-04-08 | Mainboard |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409937A (en) * | 2014-11-25 | 2015-03-11 | 合肥宝龙达信息技术有限公司 | USB3.0 (universal serial bus 3.0) and eSATA (external serial advanced technology attachment) combined interface |
| CN105893298A (en) * | 2016-06-29 | 2016-08-24 | 联想(北京)有限公司 | Interface connecting method and electronic equipment |
| CN107092570A (en) * | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
| CN107291649A (en) * | 2017-06-20 | 2017-10-24 | 郑州云海信息技术有限公司 | The design method and device of a kind of flexible support PCIE and SATA agreements M.2 self-identifying |
| CN107704272A (en) * | 2017-10-24 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system, device and storage medium |
| CN107765995A (en) * | 2017-09-22 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of hard-disk interface multichannel compatible system and implementation method |
| CN107832094A (en) * | 2017-10-24 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system and relevant apparatus |
| CN109815182A (en) * | 2019-01-28 | 2019-05-28 | 合肥联宝信息技术有限公司 | A kind of hardware device recognition methods and device |
| CN109857695A (en) * | 2018-12-27 | 2019-06-07 | 曙光信息产业(北京)有限公司 | The interface switch system of server master board |
| CN110554990A (en) * | 2018-06-01 | 2019-12-10 | 鸿富锦精密工业(武汉)有限公司 | Mainboard circuit compatible with PCIE and SATA circuits |
| CN111104360A (en) * | 2019-11-30 | 2020-05-05 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| US11150842B1 (en) | 2020-04-20 | 2021-10-19 | Western Digital Technologies, Inc. | Dynamic memory controller and method for use therewith |
| WO2021262255A1 (en) * | 2020-06-24 | 2021-12-30 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11442665B2 (en) | 2020-12-04 | 2022-09-13 | Western Digital Technologies, Inc. | Storage system and method for dynamic selection of a host interface |
| WO2023273140A1 (en) * | 2021-06-28 | 2023-01-05 | 深圳市商汤科技有限公司 | Signal transmission apparatus and method, and computer device and storage medium |
-
2013
- 2013-04-08 CN CN 201320170096 patent/CN203224819U/en not_active Expired - Fee Related
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409937A (en) * | 2014-11-25 | 2015-03-11 | 合肥宝龙达信息技术有限公司 | USB3.0 (universal serial bus 3.0) and eSATA (external serial advanced technology attachment) combined interface |
| CN105893298A (en) * | 2016-06-29 | 2016-08-24 | 联想(北京)有限公司 | Interface connecting method and electronic equipment |
| CN107092570A (en) * | 2017-05-27 | 2017-08-25 | 郑州云海信息技术有限公司 | The adaptive configuring method and system of a kind of onboard M.2 hard disk of server |
| CN107291649A (en) * | 2017-06-20 | 2017-10-24 | 郑州云海信息技术有限公司 | The design method and device of a kind of flexible support PCIE and SATA agreements M.2 self-identifying |
| WO2018233222A1 (en) * | 2017-06-20 | 2018-12-27 | 郑州云海信息技术有限公司 | Design method and apparatus for self-recognition of m.2 capable of flexibly supporting pcie and sata protocols |
| CN107765995A (en) * | 2017-09-22 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of hard-disk interface multichannel compatible system and implementation method |
| CN107704272A (en) * | 2017-10-24 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system, device and storage medium |
| CN107832094A (en) * | 2017-10-24 | 2018-03-23 | 郑州云海信息技术有限公司 | A kind of mainboard and its BIOS configuration determination method, system and relevant apparatus |
| CN110554990A (en) * | 2018-06-01 | 2019-12-10 | 鸿富锦精密工业(武汉)有限公司 | Mainboard circuit compatible with PCIE and SATA circuits |
| CN109857695A (en) * | 2018-12-27 | 2019-06-07 | 曙光信息产业(北京)有限公司 | The interface switch system of server master board |
| CN109815182A (en) * | 2019-01-28 | 2019-05-28 | 合肥联宝信息技术有限公司 | A kind of hardware device recognition methods and device |
| CN111104360A (en) * | 2019-11-30 | 2020-05-05 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| CN111104360B (en) * | 2019-11-30 | 2021-08-10 | 北京浪潮数据技术有限公司 | NVMe protocol-based solid state disk |
| US11150842B1 (en) | 2020-04-20 | 2021-10-19 | Western Digital Technologies, Inc. | Dynamic memory controller and method for use therewith |
| WO2021262255A1 (en) * | 2020-06-24 | 2021-12-30 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11281399B2 (en) | 2020-06-24 | 2022-03-22 | Western Digital Technologies, Inc. | Dual-interface storage system and method for use therewith |
| US11442665B2 (en) | 2020-12-04 | 2022-09-13 | Western Digital Technologies, Inc. | Storage system and method for dynamic selection of a host interface |
| WO2023273140A1 (en) * | 2021-06-28 | 2023-01-05 | 深圳市商汤科技有限公司 | Signal transmission apparatus and method, and computer device and storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131002 Termination date: 20200408 |
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| CF01 | Termination of patent right due to non-payment of annual fee |