CN203133816U - Hardware reset system - Google Patents
Hardware reset system Download PDFInfo
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- CN203133816U CN203133816U CN 201320120245 CN201320120245U CN203133816U CN 203133816 U CN203133816 U CN 203133816U CN 201320120245 CN201320120245 CN 201320120245 CN 201320120245 U CN201320120245 U CN 201320120245U CN 203133816 U CN203133816 U CN 203133816U
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Abstract
The utility model discloses a hardware reset system which comprises a plurality of processor units and processor reset circuits. The processor reset circuits correspond to the processor units, and each processor unit is communicated with another processor unit, is connected with the processor reset circuit corresponding to the other processor unit and is used for monitoring the other processor unit. The hardware reset system has the advantages that one processor unit monitors another processor unit, so that crash of the system is assuredly prevented, the stability of the system is improved, the design of the system is simplified, new hardware is omitted, and accordingly the cost of the system is lowered.
Description
Technical field
The utility model belongs to embedded hardware system design field, is specifically related to the design of a kind of hardware reset system.
Background technology
At present, in the design of embedded hardware system, for preventing that program from existing factors such as mistake or rugged surroundings interference to cause system in case of system halt, improve system stability, all can adopt house dog, and house dog is divided into two kinds: software watchdog and hardware watchdog.Software watchdog is the simplest, but is not so good as hardware timer aspect reliability, but the hardware watchdog expense is bigger, especially works as MCU more for a long time.Existing solution is to adopt independent hardware watchdog circuit or chip to realize, namely each MCU uses a hardware watchdog, and the problem that causes like this is: increased the complicacy of new hardware and system design, and improved the cost of system's design.
The utility model content
The purpose of this utility model is in order to solve the problems referred to above that existing hardware watchdog exists, and has proposed a kind of hardware reset system.
The technical solution of the utility model is: a kind of hardware reset system, comprise a plurality of processor units and the processor reset circuit corresponding with each processor unit, wherein, a processor unit is communicated by letter with the another one processor unit, and the processor reset circuit corresponding with the another one processor unit is connected for monitoring another one processor unit.
The beneficial effects of the utility model: hardware reset of the present utility model system is by a processor unit monitoring another one processor unit, guaranteed that system can not crash, when improving system stability, simplified the design of system, do not increase new hardware, reduced the cost of system.
Description of drawings
Fig. 1 is hardware reset system architecture synoptic diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the utility model is further elaborated.
Hardware reset of the present utility model system, comprise a plurality of processor units and the processor reset circuit corresponding with each processor unit, wherein, a processor unit is communicated by letter with the another one processor unit, and the processor reset circuit corresponding with the another one processor unit is connected for monitoring another one processor unit.
For instance, total system has 3 processor units: processor unit 1, processor unit 2 and the corresponding processor reset circuit of 3,3 processor units of processor unit are processor reset circuit 1, processor reset circuit 2 and processor reset circuit 3.
System of the present utility model can realize by following a kind of form: processor unit 1 is communicated by letter with processor unit 3, and is connected with processor reset circuit 3, is used for monitoring processor unit 3; Processor unit 3 is communicated by letter with processor unit 2, and is connected with processor reset circuit 2, is used for monitoring processor unit 2; Processor unit 2 is communicated by letter with processor unit 1, and is connected with processor reset circuit 1, is used for monitoring processor unit 1.
System of the present utility model also can realize by following a kind of form: processor unit 1 is communicated by letter with processor unit 2, and is connected with processor reset circuit 2, is used for monitoring processor unit 2; Processor unit 2 is communicated by letter with processor unit 3, and is connected with processor reset circuit 3, is used for monitoring processor unit 3; Processor unit 3 is communicated by letter with processor unit 1, and is connected with processor reset circuit 1, is used for monitoring processor unit 1.
Fig. 1 has provided the example of two processor units, two MCU(processor units) reach mutual monitoring to the purpose of method, system by interconnected 4 lines between, guarantee that system can not crash, MCU is as the hardware watchdog of another MCU, as long as there are two or more MCU can use this scheme in the designed system, each MCU can both use hardware watchdog like this.
As can be seen, hardware reset of the present utility model system has guaranteed that by a processor unit monitoring another one processor unit system can not crash, when improving system stability, simplify the design of system, do not increased new hardware, reduced the cost of system.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present utility model, should to be understood that protection domain of the present utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these technology enlightenments of the utility model, and these distortion and combination are still in protection domain of the present utility model.
Claims (2)
1. hardware reset system, it is characterized in that, comprise a plurality of processor units and the processor reset circuit corresponding with each processor unit, wherein, a processor unit is communicated by letter with the another one processor unit, and the processor reset circuit corresponding with the another one processor unit is connected for monitoring another one processor unit.
2. hardware reset according to claim 1 system is characterized in that the number of described processor unit is 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320120245 CN203133816U (en) | 2013-03-18 | 2013-03-18 | Hardware reset system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320120245 CN203133816U (en) | 2013-03-18 | 2013-03-18 | Hardware reset system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203133816U true CN203133816U (en) | 2013-08-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320120245 Expired - Lifetime CN203133816U (en) | 2013-03-18 | 2013-03-18 | Hardware reset system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203133816U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506689A (en) * | 2020-12-10 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
-
2013
- 2013-03-18 CN CN 201320120245 patent/CN203133816U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112506689A (en) * | 2020-12-10 | 2021-03-16 | 盛立金融软件开发（杭州）有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
| CN112506689B (en) * | 2020-12-10 | 2023-08-11 | 盛立安元科技(杭州)股份有限公司 | Heterogeneous counter system risk monitoring method, device, equipment and medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130814 |